1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Linear Technology LTC4306 and LTC4305 I2C multiplexer/switch
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2017 Analog Devices Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on: i2c-mux-pca954x.c
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Datasheet: http://cds.linear.com/docs/en/datasheet/4306.pdf
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
13*4882a593Smuzhiyun #include <linux/gpio/driver.h>
14*4882a593Smuzhiyun #include <linux/i2c-mux.h>
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/of_device.h>
19*4882a593Smuzhiyun #include <linux/property.h>
20*4882a593Smuzhiyun #include <linux/regmap.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define LTC4305_MAX_NCHANS 2
24*4882a593Smuzhiyun #define LTC4306_MAX_NCHANS 4
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define LTC_REG_STATUS 0x0
27*4882a593Smuzhiyun #define LTC_REG_CONFIG 0x1
28*4882a593Smuzhiyun #define LTC_REG_MODE 0x2
29*4882a593Smuzhiyun #define LTC_REG_SWITCH 0x3
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define LTC_DOWNSTREAM_ACCL_EN BIT(6)
32*4882a593Smuzhiyun #define LTC_UPSTREAM_ACCL_EN BIT(7)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define LTC_GPIO_ALL_INPUT 0xC0
35*4882a593Smuzhiyun #define LTC_SWITCH_MASK 0xF0
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun enum ltc_type {
38*4882a593Smuzhiyun ltc_4305,
39*4882a593Smuzhiyun ltc_4306,
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun struct chip_desc {
43*4882a593Smuzhiyun u8 nchans;
44*4882a593Smuzhiyun u8 num_gpios;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct ltc4306 {
48*4882a593Smuzhiyun struct regmap *regmap;
49*4882a593Smuzhiyun struct gpio_chip gpiochip;
50*4882a593Smuzhiyun const struct chip_desc *chip;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static const struct chip_desc chips[] = {
54*4882a593Smuzhiyun [ltc_4305] = {
55*4882a593Smuzhiyun .nchans = LTC4305_MAX_NCHANS,
56*4882a593Smuzhiyun },
57*4882a593Smuzhiyun [ltc_4306] = {
58*4882a593Smuzhiyun .nchans = LTC4306_MAX_NCHANS,
59*4882a593Smuzhiyun .num_gpios = 2,
60*4882a593Smuzhiyun },
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
ltc4306_is_volatile_reg(struct device * dev,unsigned int reg)63*4882a593Smuzhiyun static bool ltc4306_is_volatile_reg(struct device *dev, unsigned int reg)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun return (reg == LTC_REG_CONFIG) ? true : false;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static const struct regmap_config ltc4306_regmap_config = {
69*4882a593Smuzhiyun .reg_bits = 8,
70*4882a593Smuzhiyun .val_bits = 8,
71*4882a593Smuzhiyun .max_register = LTC_REG_SWITCH,
72*4882a593Smuzhiyun .volatile_reg = ltc4306_is_volatile_reg,
73*4882a593Smuzhiyun .cache_type = REGCACHE_FLAT,
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
ltc4306_gpio_get(struct gpio_chip * chip,unsigned int offset)76*4882a593Smuzhiyun static int ltc4306_gpio_get(struct gpio_chip *chip, unsigned int offset)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun struct ltc4306 *data = gpiochip_get_data(chip);
79*4882a593Smuzhiyun unsigned int val;
80*4882a593Smuzhiyun int ret;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun ret = regmap_read(data->regmap, LTC_REG_CONFIG, &val);
83*4882a593Smuzhiyun if (ret < 0)
84*4882a593Smuzhiyun return ret;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return !!(val & BIT(1 - offset));
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
ltc4306_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)89*4882a593Smuzhiyun static void ltc4306_gpio_set(struct gpio_chip *chip, unsigned int offset,
90*4882a593Smuzhiyun int value)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct ltc4306 *data = gpiochip_get_data(chip);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun regmap_update_bits(data->regmap, LTC_REG_CONFIG, BIT(5 - offset),
95*4882a593Smuzhiyun value ? BIT(5 - offset) : 0);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
ltc4306_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)98*4882a593Smuzhiyun static int ltc4306_gpio_get_direction(struct gpio_chip *chip,
99*4882a593Smuzhiyun unsigned int offset)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct ltc4306 *data = gpiochip_get_data(chip);
102*4882a593Smuzhiyun unsigned int val;
103*4882a593Smuzhiyun int ret;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun ret = regmap_read(data->regmap, LTC_REG_MODE, &val);
106*4882a593Smuzhiyun if (ret < 0)
107*4882a593Smuzhiyun return ret;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return !!(val & BIT(7 - offset));
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
ltc4306_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)112*4882a593Smuzhiyun static int ltc4306_gpio_direction_input(struct gpio_chip *chip,
113*4882a593Smuzhiyun unsigned int offset)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct ltc4306 *data = gpiochip_get_data(chip);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun return regmap_update_bits(data->regmap, LTC_REG_MODE,
118*4882a593Smuzhiyun BIT(7 - offset), BIT(7 - offset));
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
ltc4306_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)121*4882a593Smuzhiyun static int ltc4306_gpio_direction_output(struct gpio_chip *chip,
122*4882a593Smuzhiyun unsigned int offset, int value)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun struct ltc4306 *data = gpiochip_get_data(chip);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun ltc4306_gpio_set(chip, offset, value);
127*4882a593Smuzhiyun return regmap_update_bits(data->regmap, LTC_REG_MODE,
128*4882a593Smuzhiyun BIT(7 - offset), 0);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
ltc4306_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)131*4882a593Smuzhiyun static int ltc4306_gpio_set_config(struct gpio_chip *chip,
132*4882a593Smuzhiyun unsigned int offset, unsigned long config)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct ltc4306 *data = gpiochip_get_data(chip);
135*4882a593Smuzhiyun unsigned int val;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun switch (pinconf_to_config_param(config)) {
138*4882a593Smuzhiyun case PIN_CONFIG_DRIVE_OPEN_DRAIN:
139*4882a593Smuzhiyun val = 0;
140*4882a593Smuzhiyun break;
141*4882a593Smuzhiyun case PIN_CONFIG_DRIVE_PUSH_PULL:
142*4882a593Smuzhiyun val = BIT(4 - offset);
143*4882a593Smuzhiyun break;
144*4882a593Smuzhiyun default:
145*4882a593Smuzhiyun return -ENOTSUPP;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return regmap_update_bits(data->regmap, LTC_REG_MODE,
149*4882a593Smuzhiyun BIT(4 - offset), val);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
ltc4306_gpio_init(struct ltc4306 * data)152*4882a593Smuzhiyun static int ltc4306_gpio_init(struct ltc4306 *data)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun struct device *dev = regmap_get_device(data->regmap);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun if (!data->chip->num_gpios)
157*4882a593Smuzhiyun return 0;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun data->gpiochip.label = dev_name(dev);
160*4882a593Smuzhiyun data->gpiochip.base = -1;
161*4882a593Smuzhiyun data->gpiochip.ngpio = data->chip->num_gpios;
162*4882a593Smuzhiyun data->gpiochip.parent = dev;
163*4882a593Smuzhiyun data->gpiochip.can_sleep = true;
164*4882a593Smuzhiyun data->gpiochip.get_direction = ltc4306_gpio_get_direction;
165*4882a593Smuzhiyun data->gpiochip.direction_input = ltc4306_gpio_direction_input;
166*4882a593Smuzhiyun data->gpiochip.direction_output = ltc4306_gpio_direction_output;
167*4882a593Smuzhiyun data->gpiochip.get = ltc4306_gpio_get;
168*4882a593Smuzhiyun data->gpiochip.set = ltc4306_gpio_set;
169*4882a593Smuzhiyun data->gpiochip.set_config = ltc4306_gpio_set_config;
170*4882a593Smuzhiyun data->gpiochip.owner = THIS_MODULE;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun /* gpiolib assumes all GPIOs default input */
173*4882a593Smuzhiyun regmap_write(data->regmap, LTC_REG_MODE, LTC_GPIO_ALL_INPUT);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun return devm_gpiochip_add_data(dev, &data->gpiochip, data);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
ltc4306_select_mux(struct i2c_mux_core * muxc,u32 chan)178*4882a593Smuzhiyun static int ltc4306_select_mux(struct i2c_mux_core *muxc, u32 chan)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun struct ltc4306 *data = i2c_mux_priv(muxc);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun return regmap_update_bits(data->regmap, LTC_REG_SWITCH,
183*4882a593Smuzhiyun LTC_SWITCH_MASK, BIT(7 - chan));
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
ltc4306_deselect_mux(struct i2c_mux_core * muxc,u32 chan)186*4882a593Smuzhiyun static int ltc4306_deselect_mux(struct i2c_mux_core *muxc, u32 chan)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun struct ltc4306 *data = i2c_mux_priv(muxc);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun return regmap_update_bits(data->regmap, LTC_REG_SWITCH,
191*4882a593Smuzhiyun LTC_SWITCH_MASK, 0);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static const struct i2c_device_id ltc4306_id[] = {
195*4882a593Smuzhiyun { "ltc4305", ltc_4305 },
196*4882a593Smuzhiyun { "ltc4306", ltc_4306 },
197*4882a593Smuzhiyun { }
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ltc4306_id);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun static const struct of_device_id ltc4306_of_match[] = {
202*4882a593Smuzhiyun { .compatible = "lltc,ltc4305", .data = &chips[ltc_4305] },
203*4882a593Smuzhiyun { .compatible = "lltc,ltc4306", .data = &chips[ltc_4306] },
204*4882a593Smuzhiyun { }
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ltc4306_of_match);
207*4882a593Smuzhiyun
ltc4306_probe(struct i2c_client * client)208*4882a593Smuzhiyun static int ltc4306_probe(struct i2c_client *client)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun struct i2c_adapter *adap = client->adapter;
211*4882a593Smuzhiyun const struct chip_desc *chip;
212*4882a593Smuzhiyun struct i2c_mux_core *muxc;
213*4882a593Smuzhiyun struct ltc4306 *data;
214*4882a593Smuzhiyun struct gpio_desc *gpio;
215*4882a593Smuzhiyun bool idle_disc;
216*4882a593Smuzhiyun unsigned int val = 0;
217*4882a593Smuzhiyun int num, ret;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun chip = of_device_get_match_data(&client->dev);
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun if (!chip)
222*4882a593Smuzhiyun chip = &chips[i2c_match_id(ltc4306_id, client)->driver_data];
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun idle_disc = device_property_read_bool(&client->dev,
225*4882a593Smuzhiyun "i2c-mux-idle-disconnect");
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun muxc = i2c_mux_alloc(adap, &client->dev,
228*4882a593Smuzhiyun chip->nchans, sizeof(*data),
229*4882a593Smuzhiyun I2C_MUX_LOCKED, ltc4306_select_mux,
230*4882a593Smuzhiyun idle_disc ? ltc4306_deselect_mux : NULL);
231*4882a593Smuzhiyun if (!muxc)
232*4882a593Smuzhiyun return -ENOMEM;
233*4882a593Smuzhiyun data = i2c_mux_priv(muxc);
234*4882a593Smuzhiyun data->chip = chip;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun i2c_set_clientdata(client, muxc);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun data->regmap = devm_regmap_init_i2c(client, <c4306_regmap_config);
239*4882a593Smuzhiyun if (IS_ERR(data->regmap)) {
240*4882a593Smuzhiyun ret = PTR_ERR(data->regmap);
241*4882a593Smuzhiyun dev_err(&client->dev, "Failed to allocate register map: %d\n",
242*4882a593Smuzhiyun ret);
243*4882a593Smuzhiyun return ret;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun /* Reset and enable the mux if an enable GPIO is specified. */
247*4882a593Smuzhiyun gpio = devm_gpiod_get_optional(&client->dev, "enable", GPIOD_OUT_LOW);
248*4882a593Smuzhiyun if (IS_ERR(gpio))
249*4882a593Smuzhiyun return PTR_ERR(gpio);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun if (gpio) {
252*4882a593Smuzhiyun udelay(1);
253*4882a593Smuzhiyun gpiod_set_value(gpio, 1);
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /*
257*4882a593Smuzhiyun * Write the mux register at addr to verify
258*4882a593Smuzhiyun * that the mux is in fact present. This also
259*4882a593Smuzhiyun * initializes the mux to disconnected state.
260*4882a593Smuzhiyun */
261*4882a593Smuzhiyun if (regmap_write(data->regmap, LTC_REG_SWITCH, 0) < 0) {
262*4882a593Smuzhiyun dev_warn(&client->dev, "probe failed\n");
263*4882a593Smuzhiyun return -ENODEV;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun if (device_property_read_bool(&client->dev,
267*4882a593Smuzhiyun "ltc,downstream-accelerators-enable"))
268*4882a593Smuzhiyun val |= LTC_DOWNSTREAM_ACCL_EN;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun if (device_property_read_bool(&client->dev,
271*4882a593Smuzhiyun "ltc,upstream-accelerators-enable"))
272*4882a593Smuzhiyun val |= LTC_UPSTREAM_ACCL_EN;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if (regmap_write(data->regmap, LTC_REG_CONFIG, val) < 0)
275*4882a593Smuzhiyun return -ENODEV;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun ret = ltc4306_gpio_init(data);
278*4882a593Smuzhiyun if (ret < 0)
279*4882a593Smuzhiyun return ret;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /* Now create an adapter for each channel */
282*4882a593Smuzhiyun for (num = 0; num < chip->nchans; num++) {
283*4882a593Smuzhiyun ret = i2c_mux_add_adapter(muxc, 0, num, 0);
284*4882a593Smuzhiyun if (ret) {
285*4882a593Smuzhiyun i2c_mux_del_adapters(muxc);
286*4882a593Smuzhiyun return ret;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun dev_info(&client->dev,
291*4882a593Smuzhiyun "registered %d multiplexed busses for I2C switch %s\n",
292*4882a593Smuzhiyun num, client->name);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun return 0;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
ltc4306_remove(struct i2c_client * client)297*4882a593Smuzhiyun static int ltc4306_remove(struct i2c_client *client)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun struct i2c_mux_core *muxc = i2c_get_clientdata(client);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun i2c_mux_del_adapters(muxc);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun return 0;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun static struct i2c_driver ltc4306_driver = {
307*4882a593Smuzhiyun .driver = {
308*4882a593Smuzhiyun .name = "ltc4306",
309*4882a593Smuzhiyun .of_match_table = of_match_ptr(ltc4306_of_match),
310*4882a593Smuzhiyun },
311*4882a593Smuzhiyun .probe_new = ltc4306_probe,
312*4882a593Smuzhiyun .remove = ltc4306_remove,
313*4882a593Smuzhiyun .id_table = ltc4306_id,
314*4882a593Smuzhiyun };
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun module_i2c_driver(ltc4306_driver);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
319*4882a593Smuzhiyun MODULE_DESCRIPTION("Linear Technology LTC4306, LTC4305 I2C mux/switch driver");
320*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
321