1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * i2c-stm32.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) M'boumba Cedric Madianga 2017 6*4882a593Smuzhiyun * Copyright (C) STMicroelectronics 2017 7*4882a593Smuzhiyun * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _I2C_STM32_H 12*4882a593Smuzhiyun #define _I2C_STM32_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/dma-direction.h> 15*4882a593Smuzhiyun #include <linux/dmaengine.h> 16*4882a593Smuzhiyun #include <linux/dma-mapping.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun enum stm32_i2c_speed { 19*4882a593Smuzhiyun STM32_I2C_SPEED_STANDARD, /* 100 kHz */ 20*4882a593Smuzhiyun STM32_I2C_SPEED_FAST, /* 400 kHz */ 21*4882a593Smuzhiyun STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */ 22*4882a593Smuzhiyun STM32_I2C_SPEED_END, 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /** 26*4882a593Smuzhiyun * struct stm32_i2c_dma - DMA specific data 27*4882a593Smuzhiyun * @chan_tx: dma channel for TX transfer 28*4882a593Smuzhiyun * @chan_rx: dma channel for RX transfer 29*4882a593Smuzhiyun * @chan_using: dma channel used for the current transfer (TX or RX) 30*4882a593Smuzhiyun * @dma_buf: dma buffer 31*4882a593Smuzhiyun * @dma_len: dma buffer len 32*4882a593Smuzhiyun * @dma_transfer_dir: dma transfer direction indicator 33*4882a593Smuzhiyun * @dma_data_dir: dma transfer mode indicator 34*4882a593Smuzhiyun * @dma_complete: dma transfer completion 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun struct stm32_i2c_dma { 37*4882a593Smuzhiyun struct dma_chan *chan_tx; 38*4882a593Smuzhiyun struct dma_chan *chan_rx; 39*4882a593Smuzhiyun struct dma_chan *chan_using; 40*4882a593Smuzhiyun dma_addr_t dma_buf; 41*4882a593Smuzhiyun unsigned int dma_len; 42*4882a593Smuzhiyun enum dma_transfer_direction dma_transfer_dir; 43*4882a593Smuzhiyun enum dma_data_direction dma_data_dir; 44*4882a593Smuzhiyun struct completion dma_complete; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun struct stm32_i2c_dma *stm32_i2c_dma_request(struct device *dev, 48*4882a593Smuzhiyun dma_addr_t phy_addr, 49*4882a593Smuzhiyun u32 txdr_offset, u32 rxdr_offset); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun void stm32_i2c_dma_free(struct stm32_i2c_dma *dma); 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun int stm32_i2c_prep_dma_xfer(struct device *dev, struct stm32_i2c_dma *dma, 54*4882a593Smuzhiyun bool rd_wr, u32 len, u8 *buf, 55*4882a593Smuzhiyun dma_async_tx_callback callback, 56*4882a593Smuzhiyun void *dma_async_param); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif /* _I2C_STM32_H */ 59