1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 3*4882a593Smuzhiyun /* i2c-iop3xx.h algorithm driver definitions private to i2c-iop3xx.c */ 4*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 5*4882a593Smuzhiyun /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd 6*4882a593Smuzhiyun * <Peter dot Milne at D hyphen TACQ dot com> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef I2C_IOP3XX_H 13*4882a593Smuzhiyun #define I2C_IOP3XX_H 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * iop321 hardware bit definitions 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define IOP3XX_ICR_FAST_MODE 0x8000 /* 1=400kBps, 0=100kBps */ 19*4882a593Smuzhiyun #define IOP3XX_ICR_UNIT_RESET 0x4000 /* 1=RESET */ 20*4882a593Smuzhiyun #define IOP3XX_ICR_SAD_IE 0x2000 /* 1=Slave Detect Interrupt Enable */ 21*4882a593Smuzhiyun #define IOP3XX_ICR_ALD_IE 0x1000 /* 1=Arb Loss Detect Interrupt Enable */ 22*4882a593Smuzhiyun #define IOP3XX_ICR_SSD_IE 0x0800 /* 1=Slave STOP Detect Interrupt Enable */ 23*4882a593Smuzhiyun #define IOP3XX_ICR_BERR_IE 0x0400 /* 1=Bus Error Interrupt Enable */ 24*4882a593Smuzhiyun #define IOP3XX_ICR_RXFULL_IE 0x0200 /* 1=Receive Full Interrupt Enable */ 25*4882a593Smuzhiyun #define IOP3XX_ICR_TXEMPTY_IE 0x0100 /* 1=Transmit Empty Interrupt Enable */ 26*4882a593Smuzhiyun #define IOP3XX_ICR_GCD 0x0080 /* 1=General Call Disable */ 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * IOP3XX_ICR_GCD: 1 disables response as slave. "This bit must be set 29*4882a593Smuzhiyun * when sending a master mode general call message from the I2C unit" 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun #define IOP3XX_ICR_UE 0x0040 /* 1=Unit Enable */ 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * "NOTE: To avoid I2C bus integrity problems, 34*4882a593Smuzhiyun * the user needs to ensure that the GPIO Output Data Register - 35*4882a593Smuzhiyun * GPOD bits associated with an I2C port are cleared prior to setting 36*4882a593Smuzhiyun * the enable bit for that I2C serial port. 37*4882a593Smuzhiyun * The user prepares to enable I2C port 0 and 38*4882a593Smuzhiyun * I2C port 1 by clearing GPOD bits 7:6 and GPOD bits 5:4, respectively. 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define IOP3XX_ICR_SCLEN 0x0020 /* 1=SCL enable for master mode */ 41*4882a593Smuzhiyun #define IOP3XX_ICR_MABORT 0x0010 /* 1=Send a STOP with no data 42*4882a593Smuzhiyun * NB TBYTE must be clear */ 43*4882a593Smuzhiyun #define IOP3XX_ICR_TBYTE 0x0008 /* 1=Send/Receive a byte. i2c clears */ 44*4882a593Smuzhiyun #define IOP3XX_ICR_NACK 0x0004 /* 1=reply with NACK */ 45*4882a593Smuzhiyun #define IOP3XX_ICR_MSTOP 0x0002 /* 1=send a STOP after next data byte */ 46*4882a593Smuzhiyun #define IOP3XX_ICR_MSTART 0x0001 /* 1=initiate a START */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define IOP3XX_ISR_BERRD 0x0400 /* 1=BUS ERROR Detected */ 50*4882a593Smuzhiyun #define IOP3XX_ISR_SAD 0x0200 /* 1=Slave ADdress Detected */ 51*4882a593Smuzhiyun #define IOP3XX_ISR_GCAD 0x0100 /* 1=General Call Address Detected */ 52*4882a593Smuzhiyun #define IOP3XX_ISR_RXFULL 0x0080 /* 1=Receive Full */ 53*4882a593Smuzhiyun #define IOP3XX_ISR_TXEMPTY 0x0040 /* 1=Transmit Empty */ 54*4882a593Smuzhiyun #define IOP3XX_ISR_ALD 0x0020 /* 1=Arbitration Loss Detected */ 55*4882a593Smuzhiyun #define IOP3XX_ISR_SSD 0x0010 /* 1=Slave STOP Detected */ 56*4882a593Smuzhiyun #define IOP3XX_ISR_BBUSY 0x0008 /* 1=Bus BUSY */ 57*4882a593Smuzhiyun #define IOP3XX_ISR_UNITBUSY 0x0004 /* 1=Unit Busy */ 58*4882a593Smuzhiyun #define IOP3XX_ISR_NACK 0x0002 /* 1=Unit Rx or Tx a NACK */ 59*4882a593Smuzhiyun #define IOP3XX_ISR_RXREAD 0x0001 /* 1=READ 0=WRITE (R/W bit of slave addr */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define IOP3XX_ISR_CLEARBITS 0x07f0 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define IOP3XX_ISAR_SAMASK 0x007f 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define IOP3XX_IDBR_MASK 0x00ff 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define IOP3XX_IBMR_SCL 0x0002 68*4882a593Smuzhiyun #define IOP3XX_IBMR_SDA 0x0001 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define IOP3XX_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */ 71*4882a593Smuzhiyun #define IOP3XX_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define MYSAR 0 /* default slave address */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define I2C_ERR 321 76*4882a593Smuzhiyun #define I2C_ERR_BERR (I2C_ERR+0) 77*4882a593Smuzhiyun #define I2C_ERR_ALD (I2C_ERR+1) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define CR_OFFSET 0 81*4882a593Smuzhiyun #define SR_OFFSET 0x4 82*4882a593Smuzhiyun #define SAR_OFFSET 0x8 83*4882a593Smuzhiyun #define DBR_OFFSET 0xc 84*4882a593Smuzhiyun #define CCR_OFFSET 0x10 85*4882a593Smuzhiyun #define BMR_OFFSET 0x14 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define IOP3XX_I2C_IO_SIZE 0x18 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct i2c_algo_iop3xx_data { 90*4882a593Smuzhiyun void __iomem *ioaddr; 91*4882a593Smuzhiyun wait_queue_head_t waitq; 92*4882a593Smuzhiyun spinlock_t lock; 93*4882a593Smuzhiyun u32 SR_enabled, SR_received; 94*4882a593Smuzhiyun int id; 95*4882a593Smuzhiyun struct gpio_desc *gpio_scl; 96*4882a593Smuzhiyun struct gpio_desc *gpio_sda; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif /* I2C_IOP3XX_H */ 100