1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Synopsys DesignWare I2C adapter driver (master only).
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on the TI DAVINCI I2C adapter driver.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2006 Texas Instruments.
8*4882a593Smuzhiyun * Copyright (C) 2007 MontaVista Software Inc.
9*4882a593Smuzhiyun * Copyright (C) 2009 Provigent Ltd.
10*4882a593Smuzhiyun * Copyright (C) 2011, 2015, 2016 Intel Corporation.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun #include <linux/acpi.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/err.h>
15*4882a593Smuzhiyun #include <linux/errno.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/io.h>
19*4882a593Smuzhiyun #include <linux/kernel.h>
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/pci.h>
22*4882a593Smuzhiyun #include <linux/pm_runtime.h>
23*4882a593Smuzhiyun #include <linux/sched.h>
24*4882a593Smuzhiyun #include <linux/slab.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "i2c-designware-core.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define DRIVER_NAME "i2c-designware-pci"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun enum dw_pci_ctl_id_t {
31*4882a593Smuzhiyun medfield,
32*4882a593Smuzhiyun merrifield,
33*4882a593Smuzhiyun baytrail,
34*4882a593Smuzhiyun cherrytrail,
35*4882a593Smuzhiyun haswell,
36*4882a593Smuzhiyun elkhartlake,
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct dw_scl_sda_cfg {
40*4882a593Smuzhiyun u16 ss_hcnt;
41*4882a593Smuzhiyun u16 fs_hcnt;
42*4882a593Smuzhiyun u16 ss_lcnt;
43*4882a593Smuzhiyun u16 fs_lcnt;
44*4882a593Smuzhiyun u32 sda_hold;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct dw_pci_controller {
48*4882a593Smuzhiyun u32 bus_num;
49*4882a593Smuzhiyun u32 flags;
50*4882a593Smuzhiyun struct dw_scl_sda_cfg *scl_sda_cfg;
51*4882a593Smuzhiyun int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
52*4882a593Smuzhiyun u32 (*get_clk_rate_khz)(struct dw_i2c_dev *dev);
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Merrifield HCNT/LCNT/SDA hold time */
56*4882a593Smuzhiyun static struct dw_scl_sda_cfg mrfld_config = {
57*4882a593Smuzhiyun .ss_hcnt = 0x2f8,
58*4882a593Smuzhiyun .fs_hcnt = 0x87,
59*4882a593Smuzhiyun .ss_lcnt = 0x37b,
60*4882a593Smuzhiyun .fs_lcnt = 0x10a,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* BayTrail HCNT/LCNT/SDA hold time */
64*4882a593Smuzhiyun static struct dw_scl_sda_cfg byt_config = {
65*4882a593Smuzhiyun .ss_hcnt = 0x200,
66*4882a593Smuzhiyun .fs_hcnt = 0x55,
67*4882a593Smuzhiyun .ss_lcnt = 0x200,
68*4882a593Smuzhiyun .fs_lcnt = 0x99,
69*4882a593Smuzhiyun .sda_hold = 0x6,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Haswell HCNT/LCNT/SDA hold time */
73*4882a593Smuzhiyun static struct dw_scl_sda_cfg hsw_config = {
74*4882a593Smuzhiyun .ss_hcnt = 0x01b0,
75*4882a593Smuzhiyun .fs_hcnt = 0x48,
76*4882a593Smuzhiyun .ss_lcnt = 0x01fb,
77*4882a593Smuzhiyun .fs_lcnt = 0xa0,
78*4882a593Smuzhiyun .sda_hold = 0x9,
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
mfld_get_clk_rate_khz(struct dw_i2c_dev * dev)81*4882a593Smuzhiyun static u32 mfld_get_clk_rate_khz(struct dw_i2c_dev *dev)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun return 25000;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
mfld_setup(struct pci_dev * pdev,struct dw_pci_controller * c)86*4882a593Smuzhiyun static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun switch (pdev->device) {
91*4882a593Smuzhiyun case 0x0817:
92*4882a593Smuzhiyun dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
93*4882a593Smuzhiyun fallthrough;
94*4882a593Smuzhiyun case 0x0818:
95*4882a593Smuzhiyun case 0x0819:
96*4882a593Smuzhiyun c->bus_num = pdev->device - 0x817 + 3;
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun case 0x082C:
99*4882a593Smuzhiyun case 0x082D:
100*4882a593Smuzhiyun case 0x082E:
101*4882a593Smuzhiyun c->bus_num = pdev->device - 0x82C + 0;
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun return -ENODEV;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
mrfld_setup(struct pci_dev * pdev,struct dw_pci_controller * c)107*4882a593Smuzhiyun static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun * On Intel Merrifield the user visible i2c buses are enumerated
111*4882a593Smuzhiyun * [1..7]. So, we add 1 to shift the default range. Besides that the
112*4882a593Smuzhiyun * first PCI slot provides 4 functions, that's why we have to add 0 to
113*4882a593Smuzhiyun * the first slot and 4 to the next one.
114*4882a593Smuzhiyun */
115*4882a593Smuzhiyun switch (PCI_SLOT(pdev->devfn)) {
116*4882a593Smuzhiyun case 8:
117*4882a593Smuzhiyun c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
118*4882a593Smuzhiyun return 0;
119*4882a593Smuzhiyun case 9:
120*4882a593Smuzhiyun c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
121*4882a593Smuzhiyun return 0;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun return -ENODEV;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
ehl_get_clk_rate_khz(struct dw_i2c_dev * dev)126*4882a593Smuzhiyun static u32 ehl_get_clk_rate_khz(struct dw_i2c_dev *dev)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun return 100000;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static struct dw_pci_controller dw_pci_controllers[] = {
132*4882a593Smuzhiyun [medfield] = {
133*4882a593Smuzhiyun .bus_num = -1,
134*4882a593Smuzhiyun .setup = mfld_setup,
135*4882a593Smuzhiyun .get_clk_rate_khz = mfld_get_clk_rate_khz,
136*4882a593Smuzhiyun },
137*4882a593Smuzhiyun [merrifield] = {
138*4882a593Smuzhiyun .bus_num = -1,
139*4882a593Smuzhiyun .scl_sda_cfg = &mrfld_config,
140*4882a593Smuzhiyun .setup = mrfld_setup,
141*4882a593Smuzhiyun },
142*4882a593Smuzhiyun [baytrail] = {
143*4882a593Smuzhiyun .bus_num = -1,
144*4882a593Smuzhiyun .scl_sda_cfg = &byt_config,
145*4882a593Smuzhiyun },
146*4882a593Smuzhiyun [haswell] = {
147*4882a593Smuzhiyun .bus_num = -1,
148*4882a593Smuzhiyun .scl_sda_cfg = &hsw_config,
149*4882a593Smuzhiyun },
150*4882a593Smuzhiyun [cherrytrail] = {
151*4882a593Smuzhiyun .bus_num = -1,
152*4882a593Smuzhiyun .scl_sda_cfg = &byt_config,
153*4882a593Smuzhiyun },
154*4882a593Smuzhiyun [elkhartlake] = {
155*4882a593Smuzhiyun .bus_num = -1,
156*4882a593Smuzhiyun .get_clk_rate_khz = ehl_get_clk_rate_khz,
157*4882a593Smuzhiyun },
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun #ifdef CONFIG_PM
i2c_dw_pci_suspend(struct device * dev)161*4882a593Smuzhiyun static int i2c_dw_pci_suspend(struct device *dev)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun i_dev->suspended = true;
166*4882a593Smuzhiyun i_dev->disable(i_dev);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return 0;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
i2c_dw_pci_resume(struct device * dev)171*4882a593Smuzhiyun static int i2c_dw_pci_resume(struct device *dev)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
174*4882a593Smuzhiyun int ret;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun ret = i_dev->init(i_dev);
177*4882a593Smuzhiyun i_dev->suspended = false;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun return ret;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun #endif
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
184*4882a593Smuzhiyun i2c_dw_pci_resume, NULL);
185*4882a593Smuzhiyun
i2c_dw_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)186*4882a593Smuzhiyun static int i2c_dw_pci_probe(struct pci_dev *pdev,
187*4882a593Smuzhiyun const struct pci_device_id *id)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun struct dw_i2c_dev *dev;
190*4882a593Smuzhiyun struct i2c_adapter *adap;
191*4882a593Smuzhiyun int r;
192*4882a593Smuzhiyun struct dw_pci_controller *controller;
193*4882a593Smuzhiyun struct dw_scl_sda_cfg *cfg;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
196*4882a593Smuzhiyun dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
197*4882a593Smuzhiyun id->driver_data);
198*4882a593Smuzhiyun return -EINVAL;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun controller = &dw_pci_controllers[id->driver_data];
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun r = pcim_enable_device(pdev);
204*4882a593Smuzhiyun if (r) {
205*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
206*4882a593Smuzhiyun r);
207*4882a593Smuzhiyun return r;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun pci_set_master(pdev);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
213*4882a593Smuzhiyun if (r) {
214*4882a593Smuzhiyun dev_err(&pdev->dev, "I/O memory remapping failed\n");
215*4882a593Smuzhiyun return r;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
219*4882a593Smuzhiyun if (!dev)
220*4882a593Smuzhiyun return -ENOMEM;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun r = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
223*4882a593Smuzhiyun if (r < 0)
224*4882a593Smuzhiyun return r;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun dev->get_clk_rate_khz = controller->get_clk_rate_khz;
227*4882a593Smuzhiyun dev->timings.bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
228*4882a593Smuzhiyun dev->base = pcim_iomap_table(pdev)[0];
229*4882a593Smuzhiyun dev->dev = &pdev->dev;
230*4882a593Smuzhiyun dev->irq = pci_irq_vector(pdev, 0);
231*4882a593Smuzhiyun dev->flags |= controller->flags;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun pci_set_drvdata(pdev, dev);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun if (controller->setup) {
236*4882a593Smuzhiyun r = controller->setup(pdev, controller);
237*4882a593Smuzhiyun if (r) {
238*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
239*4882a593Smuzhiyun return r;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun i2c_dw_adjust_bus_speed(dev);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if (has_acpi_companion(&pdev->dev))
246*4882a593Smuzhiyun i2c_dw_acpi_configure(&pdev->dev);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun r = i2c_dw_validate_speed(dev);
249*4882a593Smuzhiyun if (r) {
250*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
251*4882a593Smuzhiyun return r;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun i2c_dw_configure(dev);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun if (controller->scl_sda_cfg) {
257*4882a593Smuzhiyun cfg = controller->scl_sda_cfg;
258*4882a593Smuzhiyun dev->ss_hcnt = cfg->ss_hcnt;
259*4882a593Smuzhiyun dev->fs_hcnt = cfg->fs_hcnt;
260*4882a593Smuzhiyun dev->ss_lcnt = cfg->ss_lcnt;
261*4882a593Smuzhiyun dev->fs_lcnt = cfg->fs_lcnt;
262*4882a593Smuzhiyun dev->sda_hold_time = cfg->sda_hold;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun adap = &dev->adapter;
266*4882a593Smuzhiyun adap->owner = THIS_MODULE;
267*4882a593Smuzhiyun adap->class = 0;
268*4882a593Smuzhiyun ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
269*4882a593Smuzhiyun adap->nr = controller->bus_num;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun r = i2c_dw_probe(dev);
272*4882a593Smuzhiyun if (r) {
273*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
274*4882a593Smuzhiyun return r;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
278*4882a593Smuzhiyun pm_runtime_use_autosuspend(&pdev->dev);
279*4882a593Smuzhiyun pm_runtime_put_autosuspend(&pdev->dev);
280*4882a593Smuzhiyun pm_runtime_allow(&pdev->dev);
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun return 0;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
i2c_dw_pci_remove(struct pci_dev * pdev)285*4882a593Smuzhiyun static void i2c_dw_pci_remove(struct pci_dev *pdev)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun dev->disable(dev);
290*4882a593Smuzhiyun pm_runtime_forbid(&pdev->dev);
291*4882a593Smuzhiyun pm_runtime_get_noresume(&pdev->dev);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun i2c_del_adapter(&dev->adapter);
294*4882a593Smuzhiyun devm_free_irq(&pdev->dev, dev->irq, dev);
295*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /* work with hotplug and coldplug */
299*4882a593Smuzhiyun MODULE_ALIAS("i2c_designware-pci");
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun static const struct pci_device_id i2_designware_pci_ids[] = {
302*4882a593Smuzhiyun /* Medfield */
303*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0817), medfield },
304*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0818), medfield },
305*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0819), medfield },
306*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x082C), medfield },
307*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x082D), medfield },
308*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x082E), medfield },
309*4882a593Smuzhiyun /* Merrifield */
310*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x1195), merrifield },
311*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x1196), merrifield },
312*4882a593Smuzhiyun /* Baytrail */
313*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0F41), baytrail },
314*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0F42), baytrail },
315*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0F43), baytrail },
316*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0F44), baytrail },
317*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0F45), baytrail },
318*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0F46), baytrail },
319*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x0F47), baytrail },
320*4882a593Smuzhiyun /* Haswell */
321*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x9c61), haswell },
322*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x9c62), haswell },
323*4882a593Smuzhiyun /* Braswell / Cherrytrail */
324*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
325*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
326*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
327*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
328*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
329*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
330*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
331*4882a593Smuzhiyun /* Elkhart Lake (PSE I2C) */
332*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x4bb9), elkhartlake },
333*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x4bba), elkhartlake },
334*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x4bbb), elkhartlake },
335*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x4bbc), elkhartlake },
336*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x4bbd), elkhartlake },
337*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x4bbe), elkhartlake },
338*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x4bbf), elkhartlake },
339*4882a593Smuzhiyun { PCI_VDEVICE(INTEL, 0x4bc0), elkhartlake },
340*4882a593Smuzhiyun { 0,}
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun static struct pci_driver dw_i2c_driver = {
345*4882a593Smuzhiyun .name = DRIVER_NAME,
346*4882a593Smuzhiyun .id_table = i2_designware_pci_ids,
347*4882a593Smuzhiyun .probe = i2c_dw_pci_probe,
348*4882a593Smuzhiyun .remove = i2c_dw_pci_remove,
349*4882a593Smuzhiyun .driver = {
350*4882a593Smuzhiyun .pm = &i2c_dw_pm_ops,
351*4882a593Smuzhiyun },
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun module_pci_driver(dw_i2c_driver);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
357*4882a593Smuzhiyun MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
358*4882a593Smuzhiyun MODULE_LICENSE("GPL");
359