1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* -------------------------------------------------------------------- */ 3*4882a593Smuzhiyun /* i2c-pcf8584.h: PCF 8584 global defines */ 4*4882a593Smuzhiyun /* -------------------------------------------------------------------- */ 5*4882a593Smuzhiyun /* Copyright (C) 1996 Simon G. Vogl 6*4882a593Smuzhiyun 1999 Hans Berglund 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun /* -------------------------------------------------------------------- */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* With some changes from Frodo Looijaard <frodol@dds.nl> */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef I2C_PCF8584_H 14*4882a593Smuzhiyun #define I2C_PCF8584_H 1 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* ----- Control register bits ---------------------------------------- */ 17*4882a593Smuzhiyun #define I2C_PCF_PIN 0x80 18*4882a593Smuzhiyun #define I2C_PCF_ESO 0x40 19*4882a593Smuzhiyun #define I2C_PCF_ES1 0x20 20*4882a593Smuzhiyun #define I2C_PCF_ES2 0x10 21*4882a593Smuzhiyun #define I2C_PCF_ENI 0x08 22*4882a593Smuzhiyun #define I2C_PCF_STA 0x04 23*4882a593Smuzhiyun #define I2C_PCF_STO 0x02 24*4882a593Smuzhiyun #define I2C_PCF_ACK 0x01 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define I2C_PCF_START (I2C_PCF_PIN | I2C_PCF_ESO | I2C_PCF_STA | I2C_PCF_ACK) 27*4882a593Smuzhiyun #define I2C_PCF_STOP (I2C_PCF_PIN | I2C_PCF_ESO | I2C_PCF_STO | I2C_PCF_ACK) 28*4882a593Smuzhiyun #define I2C_PCF_REPSTART ( I2C_PCF_ESO | I2C_PCF_STA | I2C_PCF_ACK) 29*4882a593Smuzhiyun #define I2C_PCF_IDLE (I2C_PCF_PIN | I2C_PCF_ESO | I2C_PCF_ACK) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* ----- Status register bits ----------------------------------------- */ 32*4882a593Smuzhiyun /*#define I2C_PCF_PIN 0x80 as above*/ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define I2C_PCF_INI 0x40 /* 1 if not initialized */ 35*4882a593Smuzhiyun #define I2C_PCF_STS 0x20 36*4882a593Smuzhiyun #define I2C_PCF_BER 0x10 37*4882a593Smuzhiyun #define I2C_PCF_AD0 0x08 38*4882a593Smuzhiyun #define I2C_PCF_LRB 0x08 39*4882a593Smuzhiyun #define I2C_PCF_AAS 0x04 40*4882a593Smuzhiyun #define I2C_PCF_LAB 0x02 41*4882a593Smuzhiyun #define I2C_PCF_BB 0x01 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* ----- Chip clock frequencies --------------------------------------- */ 44*4882a593Smuzhiyun #define I2C_PCF_CLK3 0x00 45*4882a593Smuzhiyun #define I2C_PCF_CLK443 0x10 46*4882a593Smuzhiyun #define I2C_PCF_CLK6 0x14 47*4882a593Smuzhiyun #define I2C_PCF_CLK 0x18 48*4882a593Smuzhiyun #define I2C_PCF_CLK12 0x1c 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* ----- transmission frequencies ------------------------------------- */ 51*4882a593Smuzhiyun #define I2C_PCF_TRNS90 0x00 /* 90 kHz */ 52*4882a593Smuzhiyun #define I2C_PCF_TRNS45 0x01 /* 45 kHz */ 53*4882a593Smuzhiyun #define I2C_PCF_TRNS11 0x02 /* 11 kHz */ 54*4882a593Smuzhiyun #define I2C_PCF_TRNS15 0x03 /* 1.5 kHz */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* ----- Access to internal registers according to ES1,ES2 ------------ */ 58*4882a593Smuzhiyun /* they are mapped to the data port ( a0 = 0 ) */ 59*4882a593Smuzhiyun /* available when ESO == 0 : */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define I2C_PCF_OWNADR 0 62*4882a593Smuzhiyun #define I2C_PCF_INTREG I2C_PCF_ES2 63*4882a593Smuzhiyun #define I2C_PCF_CLKREG I2C_PCF_ES1 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* I2C_PCF8584_H */ 66