1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Intel(R) Trace Hub Software Trace Hub (STH) data structures 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014-2015 Intel Corporation. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __INTEL_TH_STH_H__ 9*4882a593Smuzhiyun #define __INTEL_TH_STH_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun enum { 12*4882a593Smuzhiyun REG_STH_STHCAP0 = 0x0000, /* capabilities pt1 */ 13*4882a593Smuzhiyun REG_STH_STHCAP1 = 0x0004, /* capabilities pt2 */ 14*4882a593Smuzhiyun REG_STH_TRIG = 0x0008, /* TRIG packet payload */ 15*4882a593Smuzhiyun REG_STH_TRIG_TS = 0x000c, /* TRIG_TS packet payload */ 16*4882a593Smuzhiyun REG_STH_XSYNC = 0x0010, /* XSYNC packet payload */ 17*4882a593Smuzhiyun REG_STH_XSYNC_TS = 0x0014, /* XSYNC_TS packet payload */ 18*4882a593Smuzhiyun REG_STH_GERR = 0x0018, /* GERR packet payload */ 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct intel_th_channel { 22*4882a593Smuzhiyun u64 Dn; 23*4882a593Smuzhiyun u64 DnM; 24*4882a593Smuzhiyun u64 DnTS; 25*4882a593Smuzhiyun u64 DnMTS; 26*4882a593Smuzhiyun u64 USER; 27*4882a593Smuzhiyun u64 USER_TS; 28*4882a593Smuzhiyun u32 FLAG; 29*4882a593Smuzhiyun u32 FLAG_TS; 30*4882a593Smuzhiyun u32 MERR; 31*4882a593Smuzhiyun u32 __unused; 32*4882a593Smuzhiyun } __packed; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* __INTEL_TH_STH_H__ */ 35