1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Intel(R) Trace Hub Global Trace Hub (GTH) data structures 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014-2015 Intel Corporation. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __INTEL_TH_GTH_H__ 9*4882a593Smuzhiyun #define __INTEL_TH_GTH_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Map output port parameter bits to symbolic names */ 12*4882a593Smuzhiyun #define TH_OUTPUT_PARM(name) \ 13*4882a593Smuzhiyun TH_OUTPUT_ ## name 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun enum intel_th_output_parm { 16*4882a593Smuzhiyun /* output port type */ 17*4882a593Smuzhiyun TH_OUTPUT_PARM(port), 18*4882a593Smuzhiyun /* generate NULL packet */ 19*4882a593Smuzhiyun TH_OUTPUT_PARM(null), 20*4882a593Smuzhiyun /* packet drop */ 21*4882a593Smuzhiyun TH_OUTPUT_PARM(drop), 22*4882a593Smuzhiyun /* port in reset state */ 23*4882a593Smuzhiyun TH_OUTPUT_PARM(reset), 24*4882a593Smuzhiyun /* flush out data */ 25*4882a593Smuzhiyun TH_OUTPUT_PARM(flush), 26*4882a593Smuzhiyun /* mainenance packet frequency */ 27*4882a593Smuzhiyun TH_OUTPUT_PARM(smcfreq), 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * Register offsets 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun enum { 34*4882a593Smuzhiyun REG_GTH_GTHOPT0 = 0x00, /* Output ports 0..3 config */ 35*4882a593Smuzhiyun REG_GTH_GTHOPT1 = 0x04, /* Output ports 4..7 config */ 36*4882a593Smuzhiyun REG_GTH_SWDEST0 = 0x08, /* Switching destination masters 0..7 */ 37*4882a593Smuzhiyun REG_GTH_GSWTDEST = 0x88, /* Global sw trace destination */ 38*4882a593Smuzhiyun REG_GTH_SMCR0 = 0x9c, /* STP mainenance for ports 0/1 */ 39*4882a593Smuzhiyun REG_GTH_SMCR1 = 0xa0, /* STP mainenance for ports 2/3 */ 40*4882a593Smuzhiyun REG_GTH_SMCR2 = 0xa4, /* STP mainenance for ports 4/5 */ 41*4882a593Smuzhiyun REG_GTH_SMCR3 = 0xa8, /* STP mainenance for ports 6/7 */ 42*4882a593Smuzhiyun REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */ 43*4882a593Smuzhiyun REG_GTH_STAT = 0xd4, /* GTH status */ 44*4882a593Smuzhiyun REG_GTH_SCR2 = 0xd8, /* Source control (force storeEn off) */ 45*4882a593Smuzhiyun REG_GTH_DESTOVR = 0xdc, /* Destination override */ 46*4882a593Smuzhiyun REG_GTH_SCRPD0 = 0xe0, /* ScratchPad[0] */ 47*4882a593Smuzhiyun REG_GTH_SCRPD1 = 0xe4, /* ScratchPad[1] */ 48*4882a593Smuzhiyun REG_GTH_SCRPD2 = 0xe8, /* ScratchPad[2] */ 49*4882a593Smuzhiyun REG_GTH_SCRPD3 = 0xec, /* ScratchPad[3] */ 50*4882a593Smuzhiyun REG_TSCU_TSUCTRL = 0x2000, /* TSCU control register */ 51*4882a593Smuzhiyun REG_TSCU_TSCUSTAT = 0x2004, /* TSCU status register */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Common Capture Sequencer (CTS) registers */ 54*4882a593Smuzhiyun REG_CTS_C0S0_EN = 0x30c0, /* clause_event_enable_c0s0 */ 55*4882a593Smuzhiyun REG_CTS_C0S0_ACT = 0x3180, /* clause_action_control_c0s0 */ 56*4882a593Smuzhiyun REG_CTS_STAT = 0x32a0, /* cts_status */ 57*4882a593Smuzhiyun REG_CTS_CTL = 0x32a4, /* cts_control */ 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* waiting for Pipeline Empty bit(s) to assert for GTH */ 61*4882a593Smuzhiyun #define GTH_PLE_WAITLOOP_DEPTH 10000 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define TSUCTRL_CTCRESYNC BIT(0) 64*4882a593Smuzhiyun #define TSCUSTAT_CTCSYNCING BIT(1) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* waiting for Trigger status to assert for CTS */ 67*4882a593Smuzhiyun #define CTS_TRIG_WAITLOOP_DEPTH 10000 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define CTS_EVENT_ENABLE_IF_ANYTHING BIT(31) 70*4882a593Smuzhiyun #define CTS_ACTION_CONTROL_STATE_OFF 27 71*4882a593Smuzhiyun #define CTS_ACTION_CONTROL_SET_STATE(x) \ 72*4882a593Smuzhiyun (((x) & 0x1f) << CTS_ACTION_CONTROL_STATE_OFF) 73*4882a593Smuzhiyun #define CTS_ACTION_CONTROL_TRIGGER BIT(4) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define CTS_STATE_IDLE 0x10u 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define CTS_CTL_SEQUENCER_ENABLE BIT(0) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* __INTEL_TH_GTH_H__ */ 80