1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * SIRF hardware spinlock driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2015 Cambridge Silicon Radio Limited, a CSR plc group company.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/spinlock.h>
14*4882a593Smuzhiyun #include <linux/hwspinlock.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_address.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "hwspinlock_internal.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct sirf_hwspinlock {
22*4882a593Smuzhiyun void __iomem *io_base;
23*4882a593Smuzhiyun struct hwspinlock_device bank;
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Number of Hardware Spinlocks*/
27*4882a593Smuzhiyun #define HW_SPINLOCK_NUMBER 30
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* Hardware spinlock register offsets */
30*4882a593Smuzhiyun #define HW_SPINLOCK_BASE 0x404
31*4882a593Smuzhiyun #define HW_SPINLOCK_OFFSET(x) (HW_SPINLOCK_BASE + 0x4 * (x))
32*4882a593Smuzhiyun
sirf_hwspinlock_trylock(struct hwspinlock * lock)33*4882a593Smuzhiyun static int sirf_hwspinlock_trylock(struct hwspinlock *lock)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun void __iomem *lock_addr = lock->priv;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* attempt to acquire the lock by reading value == 1 from it */
38*4882a593Smuzhiyun return !!readl(lock_addr);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
sirf_hwspinlock_unlock(struct hwspinlock * lock)41*4882a593Smuzhiyun static void sirf_hwspinlock_unlock(struct hwspinlock *lock)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun void __iomem *lock_addr = lock->priv;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* release the lock by writing 0 to it */
46*4882a593Smuzhiyun writel(0, lock_addr);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static const struct hwspinlock_ops sirf_hwspinlock_ops = {
50*4882a593Smuzhiyun .trylock = sirf_hwspinlock_trylock,
51*4882a593Smuzhiyun .unlock = sirf_hwspinlock_unlock,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
sirf_hwspinlock_probe(struct platform_device * pdev)54*4882a593Smuzhiyun static int sirf_hwspinlock_probe(struct platform_device *pdev)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct sirf_hwspinlock *hwspin;
57*4882a593Smuzhiyun struct hwspinlock *hwlock;
58*4882a593Smuzhiyun int idx;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (!pdev->dev.of_node)
61*4882a593Smuzhiyun return -ENODEV;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun hwspin = devm_kzalloc(&pdev->dev,
64*4882a593Smuzhiyun struct_size(hwspin, bank.lock,
65*4882a593Smuzhiyun HW_SPINLOCK_NUMBER),
66*4882a593Smuzhiyun GFP_KERNEL);
67*4882a593Smuzhiyun if (!hwspin)
68*4882a593Smuzhiyun return -ENOMEM;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* retrieve io base */
71*4882a593Smuzhiyun hwspin->io_base = devm_platform_ioremap_resource(pdev, 0);
72*4882a593Smuzhiyun if (IS_ERR(hwspin->io_base))
73*4882a593Smuzhiyun return PTR_ERR(hwspin->io_base);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun for (idx = 0; idx < HW_SPINLOCK_NUMBER; idx++) {
76*4882a593Smuzhiyun hwlock = &hwspin->bank.lock[idx];
77*4882a593Smuzhiyun hwlock->priv = hwspin->io_base + HW_SPINLOCK_OFFSET(idx);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun platform_set_drvdata(pdev, hwspin);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return devm_hwspin_lock_register(&pdev->dev, &hwspin->bank,
83*4882a593Smuzhiyun &sirf_hwspinlock_ops, 0,
84*4882a593Smuzhiyun HW_SPINLOCK_NUMBER);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static const struct of_device_id sirf_hwpinlock_ids[] = {
88*4882a593Smuzhiyun { .compatible = "sirf,hwspinlock", },
89*4882a593Smuzhiyun {},
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sirf_hwpinlock_ids);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun static struct platform_driver sirf_hwspinlock_driver = {
94*4882a593Smuzhiyun .probe = sirf_hwspinlock_probe,
95*4882a593Smuzhiyun .driver = {
96*4882a593Smuzhiyun .name = "atlas7_hwspinlock",
97*4882a593Smuzhiyun .of_match_table = of_match_ptr(sirf_hwpinlock_ids),
98*4882a593Smuzhiyun },
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun module_platform_driver(sirf_hwspinlock_driver);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
104*4882a593Smuzhiyun MODULE_DESCRIPTION("SIRF Hardware spinlock driver");
105*4882a593Smuzhiyun MODULE_AUTHOR("Wei Chen <wei.chen@csr.com>");
106