1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/kernel.h>
5*4882a593Smuzhiyun #include <linux/module.h>
6*4882a593Smuzhiyun #include <linux/device.h>
7*4882a593Smuzhiyun #include <linux/io.h>
8*4882a593Smuzhiyun #include <linux/slab.h>
9*4882a593Smuzhiyun #include <linux/hwspinlock.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "hwspinlock_internal.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun struct rockchip_hwspinlock {
16*4882a593Smuzhiyun void __iomem *io_base;
17*4882a593Smuzhiyun struct hwspinlock_device bank;
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Number of Hardware Spinlocks*/
21*4882a593Smuzhiyun #define HWSPINLOCK_NUMBER 64
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* Hardware spinlock register offsets */
24*4882a593Smuzhiyun #define HWSPINLOCK_OFFSET(x) (0x4 * (x))
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define HWSPINLOCK_OWNER_ID 0x01
27*4882a593Smuzhiyun
rockchip_hwspinlock_trylock(struct hwspinlock * lock)28*4882a593Smuzhiyun static int rockchip_hwspinlock_trylock(struct hwspinlock *lock)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun void __iomem *lock_addr = lock->priv;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun writel(HWSPINLOCK_OWNER_ID, lock_addr);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /*
35*4882a593Smuzhiyun * Get only first 4 bits and compare to HWSPINLOCK_OWNER_ID,
36*4882a593Smuzhiyun * if equal, we attempt to acquire the lock, otherwise,
37*4882a593Smuzhiyun * someone else has it.
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun return (HWSPINLOCK_OWNER_ID == (0x0F & readl(lock_addr)));
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
rockchip_hwspinlock_unlock(struct hwspinlock * lock)42*4882a593Smuzhiyun static void rockchip_hwspinlock_unlock(struct hwspinlock *lock)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun void __iomem *lock_addr = lock->priv;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Release the lock by writing 0 to it */
47*4882a593Smuzhiyun writel(0, lock_addr);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const struct hwspinlock_ops rockchip_hwspinlock_ops = {
51*4882a593Smuzhiyun .trylock = rockchip_hwspinlock_trylock,
52*4882a593Smuzhiyun .unlock = rockchip_hwspinlock_unlock,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
rockchip_hwspinlock_probe(struct platform_device * pdev)55*4882a593Smuzhiyun static int rockchip_hwspinlock_probe(struct platform_device *pdev)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct rockchip_hwspinlock *hwspin;
58*4882a593Smuzhiyun struct hwspinlock *hwlock;
59*4882a593Smuzhiyun int idx;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun hwspin = devm_kzalloc(&pdev->dev,
62*4882a593Smuzhiyun struct_size(hwspin, bank.lock, HWSPINLOCK_NUMBER),
63*4882a593Smuzhiyun GFP_KERNEL);
64*4882a593Smuzhiyun if (!hwspin)
65*4882a593Smuzhiyun return -ENOMEM;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun hwspin->io_base = devm_platform_ioremap_resource(pdev, 0);
68*4882a593Smuzhiyun if (IS_ERR(hwspin->io_base))
69*4882a593Smuzhiyun return PTR_ERR(hwspin->io_base);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun for (idx = 0; idx < HWSPINLOCK_NUMBER; idx++) {
72*4882a593Smuzhiyun hwlock = &hwspin->bank.lock[idx];
73*4882a593Smuzhiyun hwlock->priv = hwspin->io_base + HWSPINLOCK_OFFSET(idx);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun platform_set_drvdata(pdev, hwspin);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return devm_hwspin_lock_register(&pdev->dev, &hwspin->bank,
79*4882a593Smuzhiyun &rockchip_hwspinlock_ops, 0,
80*4882a593Smuzhiyun HWSPINLOCK_NUMBER);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static const struct of_device_id rockchip_hwpinlock_ids[] = {
84*4882a593Smuzhiyun { .compatible = "rockchip,hwspinlock", },
85*4882a593Smuzhiyun {},
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rockchip_hwpinlock_ids);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static struct platform_driver rockchip_hwspinlock_driver = {
90*4882a593Smuzhiyun .probe = rockchip_hwspinlock_probe,
91*4882a593Smuzhiyun .driver = {
92*4882a593Smuzhiyun .name = "rockchip_hwspinlock",
93*4882a593Smuzhiyun .of_match_table = of_match_ptr(rockchip_hwpinlock_ids),
94*4882a593Smuzhiyun },
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
rockchip_hwspinlock_init(void)97*4882a593Smuzhiyun static int __init rockchip_hwspinlock_init(void)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun return platform_driver_register(&rockchip_hwspinlock_driver);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun postcore_initcall(rockchip_hwspinlock_init);
102*4882a593Smuzhiyun
rockchip_hwspinlock_exit(void)103*4882a593Smuzhiyun static void __exit rockchip_hwspinlock_exit(void)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun platform_driver_unregister(&rockchip_hwspinlock_driver);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun module_exit(rockchip_hwspinlock_exit);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
110*4882a593Smuzhiyun MODULE_DESCRIPTION("Rockchip Hardware spinlock driver");
111*4882a593Smuzhiyun MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
112