xref: /OK3568_Linux_fs/kernel/drivers/hwspinlock/qcom_hwspinlock.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  * Copyright (c) 2015, Sony Mobile Communications AB
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/hwspinlock.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_device.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/regmap.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include "hwspinlock_internal.h"
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define QCOM_MUTEX_APPS_PROC_ID	1
20*4882a593Smuzhiyun #define QCOM_MUTEX_NUM_LOCKS	32
21*4882a593Smuzhiyun 
qcom_hwspinlock_trylock(struct hwspinlock * lock)22*4882a593Smuzhiyun static int qcom_hwspinlock_trylock(struct hwspinlock *lock)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun 	struct regmap_field *field = lock->priv;
25*4882a593Smuzhiyun 	u32 lock_owner;
26*4882a593Smuzhiyun 	int ret;
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun 	ret = regmap_field_write(field, QCOM_MUTEX_APPS_PROC_ID);
29*4882a593Smuzhiyun 	if (ret)
30*4882a593Smuzhiyun 		return ret;
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun 	ret = regmap_field_read(field, &lock_owner);
33*4882a593Smuzhiyun 	if (ret)
34*4882a593Smuzhiyun 		return ret;
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	return lock_owner == QCOM_MUTEX_APPS_PROC_ID;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun 
qcom_hwspinlock_unlock(struct hwspinlock * lock)39*4882a593Smuzhiyun static void qcom_hwspinlock_unlock(struct hwspinlock *lock)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun 	struct regmap_field *field = lock->priv;
42*4882a593Smuzhiyun 	u32 lock_owner;
43*4882a593Smuzhiyun 	int ret;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	ret = regmap_field_read(field, &lock_owner);
46*4882a593Smuzhiyun 	if (ret) {
47*4882a593Smuzhiyun 		pr_err("%s: unable to query spinlock owner\n", __func__);
48*4882a593Smuzhiyun 		return;
49*4882a593Smuzhiyun 	}
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	if (lock_owner != QCOM_MUTEX_APPS_PROC_ID) {
52*4882a593Smuzhiyun 		pr_err("%s: spinlock not owned by us (actual owner is %d)\n",
53*4882a593Smuzhiyun 				__func__, lock_owner);
54*4882a593Smuzhiyun 	}
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	ret = regmap_field_write(field, 0);
57*4882a593Smuzhiyun 	if (ret)
58*4882a593Smuzhiyun 		pr_err("%s: failed to unlock spinlock\n", __func__);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun static const struct hwspinlock_ops qcom_hwspinlock_ops = {
62*4882a593Smuzhiyun 	.trylock	= qcom_hwspinlock_trylock,
63*4882a593Smuzhiyun 	.unlock		= qcom_hwspinlock_unlock,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun static const struct of_device_id qcom_hwspinlock_of_match[] = {
67*4882a593Smuzhiyun 	{ .compatible = "qcom,sfpb-mutex" },
68*4882a593Smuzhiyun 	{ .compatible = "qcom,tcsr-mutex" },
69*4882a593Smuzhiyun 	{ }
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match);
72*4882a593Smuzhiyun 
qcom_hwspinlock_probe_syscon(struct platform_device * pdev,u32 * base,u32 * stride)73*4882a593Smuzhiyun static struct regmap *qcom_hwspinlock_probe_syscon(struct platform_device *pdev,
74*4882a593Smuzhiyun 						   u32 *base, u32 *stride)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	struct device_node *syscon;
77*4882a593Smuzhiyun 	struct regmap *regmap;
78*4882a593Smuzhiyun 	int ret;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0);
81*4882a593Smuzhiyun 	if (!syscon)
82*4882a593Smuzhiyun 		return ERR_PTR(-ENODEV);
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	regmap = syscon_node_to_regmap(syscon);
85*4882a593Smuzhiyun 	of_node_put(syscon);
86*4882a593Smuzhiyun 	if (IS_ERR(regmap))
87*4882a593Smuzhiyun 		return regmap;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, base);
90*4882a593Smuzhiyun 	if (ret < 0) {
91*4882a593Smuzhiyun 		dev_err(&pdev->dev, "no offset in syscon\n");
92*4882a593Smuzhiyun 		return ERR_PTR(-EINVAL);
93*4882a593Smuzhiyun 	}
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, stride);
96*4882a593Smuzhiyun 	if (ret < 0) {
97*4882a593Smuzhiyun 		dev_err(&pdev->dev, "no stride syscon\n");
98*4882a593Smuzhiyun 		return ERR_PTR(-EINVAL);
99*4882a593Smuzhiyun 	}
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	return regmap;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun static const struct regmap_config tcsr_mutex_config = {
105*4882a593Smuzhiyun 	.reg_bits		= 32,
106*4882a593Smuzhiyun 	.reg_stride		= 4,
107*4882a593Smuzhiyun 	.val_bits		= 32,
108*4882a593Smuzhiyun 	.max_register		= 0x20000,
109*4882a593Smuzhiyun 	.fast_io		= true,
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun 
qcom_hwspinlock_probe_mmio(struct platform_device * pdev,u32 * offset,u32 * stride)112*4882a593Smuzhiyun static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev,
113*4882a593Smuzhiyun 						 u32 *offset, u32 *stride)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
116*4882a593Smuzhiyun 	void __iomem *base;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/* All modern platform has offset 0 and stride of 4k */
119*4882a593Smuzhiyun 	*offset = 0;
120*4882a593Smuzhiyun 	*stride = 0x1000;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	base = devm_platform_ioremap_resource(pdev, 0);
123*4882a593Smuzhiyun 	if (IS_ERR(base))
124*4882a593Smuzhiyun 		return ERR_CAST(base);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	return devm_regmap_init_mmio(dev, base, &tcsr_mutex_config);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
qcom_hwspinlock_probe(struct platform_device * pdev)129*4882a593Smuzhiyun static int qcom_hwspinlock_probe(struct platform_device *pdev)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun 	struct hwspinlock_device *bank;
132*4882a593Smuzhiyun 	struct reg_field field;
133*4882a593Smuzhiyun 	struct regmap *regmap;
134*4882a593Smuzhiyun 	size_t array_size;
135*4882a593Smuzhiyun 	u32 stride;
136*4882a593Smuzhiyun 	u32 base;
137*4882a593Smuzhiyun 	int i;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	regmap = qcom_hwspinlock_probe_syscon(pdev, &base, &stride);
140*4882a593Smuzhiyun 	if (IS_ERR(regmap) && PTR_ERR(regmap) == -ENODEV)
141*4882a593Smuzhiyun 		regmap = qcom_hwspinlock_probe_mmio(pdev, &base, &stride);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	if (IS_ERR(regmap))
144*4882a593Smuzhiyun 		return PTR_ERR(regmap);
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	array_size = QCOM_MUTEX_NUM_LOCKS * sizeof(struct hwspinlock);
147*4882a593Smuzhiyun 	bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL);
148*4882a593Smuzhiyun 	if (!bank)
149*4882a593Smuzhiyun 		return -ENOMEM;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	platform_set_drvdata(pdev, bank);
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	for (i = 0; i < QCOM_MUTEX_NUM_LOCKS; i++) {
154*4882a593Smuzhiyun 		field.reg = base + i * stride;
155*4882a593Smuzhiyun 		field.lsb = 0;
156*4882a593Smuzhiyun 		field.msb = 31;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 		bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev,
159*4882a593Smuzhiyun 							     regmap, field);
160*4882a593Smuzhiyun 	}
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	return devm_hwspin_lock_register(&pdev->dev, bank, &qcom_hwspinlock_ops,
163*4882a593Smuzhiyun 					 0, QCOM_MUTEX_NUM_LOCKS);
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun static struct platform_driver qcom_hwspinlock_driver = {
167*4882a593Smuzhiyun 	.probe		= qcom_hwspinlock_probe,
168*4882a593Smuzhiyun 	.driver		= {
169*4882a593Smuzhiyun 		.name	= "qcom_hwspinlock",
170*4882a593Smuzhiyun 		.of_match_table = qcom_hwspinlock_of_match,
171*4882a593Smuzhiyun 	},
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
qcom_hwspinlock_init(void)174*4882a593Smuzhiyun static int __init qcom_hwspinlock_init(void)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	return platform_driver_register(&qcom_hwspinlock_driver);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun /* board init code might need to reserve hwspinlocks for predefined purposes */
179*4882a593Smuzhiyun postcore_initcall(qcom_hwspinlock_init);
180*4882a593Smuzhiyun 
qcom_hwspinlock_exit(void)181*4882a593Smuzhiyun static void __exit qcom_hwspinlock_exit(void)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	platform_driver_unregister(&qcom_hwspinlock_driver);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun module_exit(qcom_hwspinlock_exit);
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
188*4882a593Smuzhiyun MODULE_DESCRIPTION("Hardware spinlock driver for Qualcomm SoCs");
189