xref: /OK3568_Linux_fs/kernel/drivers/hwmon/w83791d.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * w83791d.c - Part of lm_sensors, Linux kernel modules for hardware
4*4882a593Smuzhiyun  *	       monitoring
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2006-2007 Charles Spirakis <bezaur@gmail.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun  * Supports following chips:
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * Chip		#vin	#fanin	#pwm	#temp	wchipid	vendid	i2c	ISA
13*4882a593Smuzhiyun  * w83791d	10	5	5	3	0x71	0x5ca3	yes	no
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * The w83791d chip appears to be part way between the 83781d and the
16*4882a593Smuzhiyun  * 83792d. Thus, this file is derived from both the w83792d.c and
17*4882a593Smuzhiyun  * w83781d.c files.
18*4882a593Smuzhiyun  *
19*4882a593Smuzhiyun  * The w83791g chip is the same as the w83791d but lead-free.
20*4882a593Smuzhiyun  */
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include <linux/module.h>
23*4882a593Smuzhiyun #include <linux/init.h>
24*4882a593Smuzhiyun #include <linux/slab.h>
25*4882a593Smuzhiyun #include <linux/i2c.h>
26*4882a593Smuzhiyun #include <linux/hwmon.h>
27*4882a593Smuzhiyun #include <linux/hwmon-vid.h>
28*4882a593Smuzhiyun #include <linux/hwmon-sysfs.h>
29*4882a593Smuzhiyun #include <linux/err.h>
30*4882a593Smuzhiyun #include <linux/mutex.h>
31*4882a593Smuzhiyun #include <linux/jiffies.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define NUMBER_OF_VIN		10
34*4882a593Smuzhiyun #define NUMBER_OF_FANIN		5
35*4882a593Smuzhiyun #define NUMBER_OF_TEMPIN	3
36*4882a593Smuzhiyun #define NUMBER_OF_PWM		5
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* Addresses to scan */
39*4882a593Smuzhiyun static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, 0x2f,
40*4882a593Smuzhiyun 						I2C_CLIENT_END };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* Insmod parameters */
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun static unsigned short force_subclients[4];
45*4882a593Smuzhiyun module_param_array(force_subclients, short, NULL, 0);
46*4882a593Smuzhiyun MODULE_PARM_DESC(force_subclients,
47*4882a593Smuzhiyun 		 "List of subclient addresses: {bus, clientaddr, subclientaddr1, subclientaddr2}");
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun static bool reset;
50*4882a593Smuzhiyun module_param(reset, bool, 0);
51*4882a593Smuzhiyun MODULE_PARM_DESC(reset, "Set to one to force a hardware chip reset");
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun static bool init;
54*4882a593Smuzhiyun module_param(init, bool, 0);
55*4882a593Smuzhiyun MODULE_PARM_DESC(init, "Set to one to force extra software initialization");
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun /* The W83791D registers */
58*4882a593Smuzhiyun static const u8 W83791D_REG_IN[NUMBER_OF_VIN] = {
59*4882a593Smuzhiyun 	0x20,			/* VCOREA in DataSheet */
60*4882a593Smuzhiyun 	0x21,			/* VINR0 in DataSheet */
61*4882a593Smuzhiyun 	0x22,			/* +3.3VIN in DataSheet */
62*4882a593Smuzhiyun 	0x23,			/* VDD5V in DataSheet */
63*4882a593Smuzhiyun 	0x24,			/* +12VIN in DataSheet */
64*4882a593Smuzhiyun 	0x25,			/* -12VIN in DataSheet */
65*4882a593Smuzhiyun 	0x26,			/* -5VIN in DataSheet */
66*4882a593Smuzhiyun 	0xB0,			/* 5VSB in DataSheet */
67*4882a593Smuzhiyun 	0xB1,			/* VBAT in DataSheet */
68*4882a593Smuzhiyun 	0xB2			/* VINR1 in DataSheet */
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun static const u8 W83791D_REG_IN_MAX[NUMBER_OF_VIN] = {
72*4882a593Smuzhiyun 	0x2B,			/* VCOREA High Limit in DataSheet */
73*4882a593Smuzhiyun 	0x2D,			/* VINR0 High Limit in DataSheet */
74*4882a593Smuzhiyun 	0x2F,			/* +3.3VIN High Limit in DataSheet */
75*4882a593Smuzhiyun 	0x31,			/* VDD5V High Limit in DataSheet */
76*4882a593Smuzhiyun 	0x33,			/* +12VIN High Limit in DataSheet */
77*4882a593Smuzhiyun 	0x35,			/* -12VIN High Limit in DataSheet */
78*4882a593Smuzhiyun 	0x37,			/* -5VIN High Limit in DataSheet */
79*4882a593Smuzhiyun 	0xB4,			/* 5VSB High Limit in DataSheet */
80*4882a593Smuzhiyun 	0xB6,			/* VBAT High Limit in DataSheet */
81*4882a593Smuzhiyun 	0xB8			/* VINR1 High Limit in DataSheet */
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun static const u8 W83791D_REG_IN_MIN[NUMBER_OF_VIN] = {
84*4882a593Smuzhiyun 	0x2C,			/* VCOREA Low Limit in DataSheet */
85*4882a593Smuzhiyun 	0x2E,			/* VINR0 Low Limit in DataSheet */
86*4882a593Smuzhiyun 	0x30,			/* +3.3VIN Low Limit in DataSheet */
87*4882a593Smuzhiyun 	0x32,			/* VDD5V Low Limit in DataSheet */
88*4882a593Smuzhiyun 	0x34,			/* +12VIN Low Limit in DataSheet */
89*4882a593Smuzhiyun 	0x36,			/* -12VIN Low Limit in DataSheet */
90*4882a593Smuzhiyun 	0x38,			/* -5VIN Low Limit in DataSheet */
91*4882a593Smuzhiyun 	0xB5,			/* 5VSB Low Limit in DataSheet */
92*4882a593Smuzhiyun 	0xB7,			/* VBAT Low Limit in DataSheet */
93*4882a593Smuzhiyun 	0xB9			/* VINR1 Low Limit in DataSheet */
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun static const u8 W83791D_REG_FAN[NUMBER_OF_FANIN] = {
96*4882a593Smuzhiyun 	0x28,			/* FAN 1 Count in DataSheet */
97*4882a593Smuzhiyun 	0x29,			/* FAN 2 Count in DataSheet */
98*4882a593Smuzhiyun 	0x2A,			/* FAN 3 Count in DataSheet */
99*4882a593Smuzhiyun 	0xBA,			/* FAN 4 Count in DataSheet */
100*4882a593Smuzhiyun 	0xBB,			/* FAN 5 Count in DataSheet */
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun static const u8 W83791D_REG_FAN_MIN[NUMBER_OF_FANIN] = {
103*4882a593Smuzhiyun 	0x3B,			/* FAN 1 Count Low Limit in DataSheet */
104*4882a593Smuzhiyun 	0x3C,			/* FAN 2 Count Low Limit in DataSheet */
105*4882a593Smuzhiyun 	0x3D,			/* FAN 3 Count Low Limit in DataSheet */
106*4882a593Smuzhiyun 	0xBC,			/* FAN 4 Count Low Limit in DataSheet */
107*4882a593Smuzhiyun 	0xBD,			/* FAN 5 Count Low Limit in DataSheet */
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun static const u8 W83791D_REG_PWM[NUMBER_OF_PWM] = {
111*4882a593Smuzhiyun 	0x81,			/* PWM 1 duty cycle register in DataSheet */
112*4882a593Smuzhiyun 	0x83,			/* PWM 2 duty cycle register in DataSheet */
113*4882a593Smuzhiyun 	0x94,			/* PWM 3 duty cycle register in DataSheet */
114*4882a593Smuzhiyun 	0xA0,			/* PWM 4 duty cycle register in DataSheet */
115*4882a593Smuzhiyun 	0xA1,			/* PWM 5 duty cycle register in DataSheet */
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun static const u8 W83791D_REG_TEMP_TARGET[3] = {
119*4882a593Smuzhiyun 	0x85,			/* PWM 1 target temperature for temp 1 */
120*4882a593Smuzhiyun 	0x86,			/* PWM 2 target temperature for temp 2 */
121*4882a593Smuzhiyun 	0x96,			/* PWM 3 target temperature for temp 3 */
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun static const u8 W83791D_REG_TEMP_TOL[2] = {
125*4882a593Smuzhiyun 	0x87,			/* PWM 1/2 temperature tolerance */
126*4882a593Smuzhiyun 	0x97,			/* PWM 3 temperature tolerance */
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun static const u8 W83791D_REG_FAN_CFG[2] = {
130*4882a593Smuzhiyun 	0x84,			/* FAN 1/2 configuration */
131*4882a593Smuzhiyun 	0x95,			/* FAN 3 configuration */
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun static const u8 W83791D_REG_FAN_DIV[3] = {
135*4882a593Smuzhiyun 	0x47,			/* contains FAN1 and FAN2 Divisor */
136*4882a593Smuzhiyun 	0x4b,			/* contains FAN3 Divisor */
137*4882a593Smuzhiyun 	0x5C,			/* contains FAN4 and FAN5 Divisor */
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun #define W83791D_REG_BANK		0x4E
141*4882a593Smuzhiyun #define W83791D_REG_TEMP2_CONFIG	0xC2
142*4882a593Smuzhiyun #define W83791D_REG_TEMP3_CONFIG	0xCA
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun static const u8 W83791D_REG_TEMP1[3] = {
145*4882a593Smuzhiyun 	0x27,			/* TEMP 1 in DataSheet */
146*4882a593Smuzhiyun 	0x39,			/* TEMP 1 Over in DataSheet */
147*4882a593Smuzhiyun 	0x3A,			/* TEMP 1 Hyst in DataSheet */
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun static const u8 W83791D_REG_TEMP_ADD[2][6] = {
151*4882a593Smuzhiyun 	{0xC0,			/* TEMP 2 in DataSheet */
152*4882a593Smuzhiyun 	 0xC1,			/* TEMP 2(0.5 deg) in DataSheet */
153*4882a593Smuzhiyun 	 0xC5,			/* TEMP 2 Over High part in DataSheet */
154*4882a593Smuzhiyun 	 0xC6,			/* TEMP 2 Over Low part in DataSheet */
155*4882a593Smuzhiyun 	 0xC3,			/* TEMP 2 Thyst High part in DataSheet */
156*4882a593Smuzhiyun 	 0xC4},			/* TEMP 2 Thyst Low part in DataSheet */
157*4882a593Smuzhiyun 	{0xC8,			/* TEMP 3 in DataSheet */
158*4882a593Smuzhiyun 	 0xC9,			/* TEMP 3(0.5 deg) in DataSheet */
159*4882a593Smuzhiyun 	 0xCD,			/* TEMP 3 Over High part in DataSheet */
160*4882a593Smuzhiyun 	 0xCE,			/* TEMP 3 Over Low part in DataSheet */
161*4882a593Smuzhiyun 	 0xCB,			/* TEMP 3 Thyst High part in DataSheet */
162*4882a593Smuzhiyun 	 0xCC}			/* TEMP 3 Thyst Low part in DataSheet */
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun #define W83791D_REG_BEEP_CONFIG		0x4D
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun static const u8 W83791D_REG_BEEP_CTRL[3] = {
168*4882a593Smuzhiyun 	0x56,			/* BEEP Control Register 1 */
169*4882a593Smuzhiyun 	0x57,			/* BEEP Control Register 2 */
170*4882a593Smuzhiyun 	0xA3,			/* BEEP Control Register 3 */
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun #define W83791D_REG_GPIO		0x15
174*4882a593Smuzhiyun #define W83791D_REG_CONFIG		0x40
175*4882a593Smuzhiyun #define W83791D_REG_VID_FANDIV		0x47
176*4882a593Smuzhiyun #define W83791D_REG_DID_VID4		0x49
177*4882a593Smuzhiyun #define W83791D_REG_WCHIPID		0x58
178*4882a593Smuzhiyun #define W83791D_REG_CHIPMAN		0x4F
179*4882a593Smuzhiyun #define W83791D_REG_PIN			0x4B
180*4882a593Smuzhiyun #define W83791D_REG_I2C_SUBADDR		0x4A
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun #define W83791D_REG_ALARM1 0xA9	/* realtime status register1 */
183*4882a593Smuzhiyun #define W83791D_REG_ALARM2 0xAA	/* realtime status register2 */
184*4882a593Smuzhiyun #define W83791D_REG_ALARM3 0xAB	/* realtime status register3 */
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun #define W83791D_REG_VBAT		0x5D
187*4882a593Smuzhiyun #define W83791D_REG_I2C_ADDR		0x48
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun /*
190*4882a593Smuzhiyun  * The SMBus locks itself. The Winbond W83791D has a bank select register
191*4882a593Smuzhiyun  * (index 0x4e), but the driver only accesses registers in bank 0. Since
192*4882a593Smuzhiyun  * we don't switch banks, we don't need any special code to handle
193*4882a593Smuzhiyun  * locking access between bank switches
194*4882a593Smuzhiyun  */
w83791d_read(struct i2c_client * client,u8 reg)195*4882a593Smuzhiyun static inline int w83791d_read(struct i2c_client *client, u8 reg)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun 	return i2c_smbus_read_byte_data(client, reg);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun 
w83791d_write(struct i2c_client * client,u8 reg,u8 value)200*4882a593Smuzhiyun static inline int w83791d_write(struct i2c_client *client, u8 reg, u8 value)
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun 	return i2c_smbus_write_byte_data(client, reg, value);
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun /*
206*4882a593Smuzhiyun  * The analog voltage inputs have 16mV LSB. Since the sysfs output is
207*4882a593Smuzhiyun  * in mV as would be measured on the chip input pin, need to just
208*4882a593Smuzhiyun  * multiply/divide by 16 to translate from/to register values.
209*4882a593Smuzhiyun  */
210*4882a593Smuzhiyun #define IN_TO_REG(val)		(clamp_val((((val) + 8) / 16), 0, 255))
211*4882a593Smuzhiyun #define IN_FROM_REG(val)	((val) * 16)
212*4882a593Smuzhiyun 
fan_to_reg(long rpm,int div)213*4882a593Smuzhiyun static u8 fan_to_reg(long rpm, int div)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	if (rpm == 0)
216*4882a593Smuzhiyun 		return 255;
217*4882a593Smuzhiyun 	rpm = clamp_val(rpm, 1, 1000000);
218*4882a593Smuzhiyun 	return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun #define FAN_FROM_REG(val, div)	((val) == 0 ? -1 : \
222*4882a593Smuzhiyun 				((val) == 255 ? 0 : \
223*4882a593Smuzhiyun 					1350000 / ((val) * (div))))
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun /* for temp1 which is 8-bit resolution, LSB = 1 degree Celsius */
226*4882a593Smuzhiyun #define TEMP1_FROM_REG(val)	((val) * 1000)
227*4882a593Smuzhiyun #define TEMP1_TO_REG(val)	((val) <= -128000 ? -128 : \
228*4882a593Smuzhiyun 				 (val) >= 127000 ? 127 : \
229*4882a593Smuzhiyun 				 (val) < 0 ? ((val) - 500) / 1000 : \
230*4882a593Smuzhiyun 				 ((val) + 500) / 1000)
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun /*
233*4882a593Smuzhiyun  * for temp2 and temp3 which are 9-bit resolution, LSB = 0.5 degree Celsius
234*4882a593Smuzhiyun  * Assumes the top 8 bits are the integral amount and the bottom 8 bits
235*4882a593Smuzhiyun  * are the fractional amount. Since we only have 0.5 degree resolution,
236*4882a593Smuzhiyun  * the bottom 7 bits will always be zero
237*4882a593Smuzhiyun  */
238*4882a593Smuzhiyun #define TEMP23_FROM_REG(val)	((val) / 128 * 500)
239*4882a593Smuzhiyun #define TEMP23_TO_REG(val)	(DIV_ROUND_CLOSEST(clamp_val((val), -128000, \
240*4882a593Smuzhiyun 						   127500), 500) * 128)
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun /* for thermal cruise target temp, 7-bits, LSB = 1 degree Celsius */
243*4882a593Smuzhiyun #define TARGET_TEMP_TO_REG(val)	DIV_ROUND_CLOSEST(clamp_val((val), 0, 127000), \
244*4882a593Smuzhiyun 						  1000)
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun /* for thermal cruise temp tolerance, 4-bits, LSB = 1 degree Celsius */
247*4882a593Smuzhiyun #define TOL_TEMP_TO_REG(val)	DIV_ROUND_CLOSEST(clamp_val((val), 0, 15000), \
248*4882a593Smuzhiyun 						  1000)
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun #define BEEP_MASK_TO_REG(val)		((val) & 0xffffff)
251*4882a593Smuzhiyun #define BEEP_MASK_FROM_REG(val)		((val) & 0xffffff)
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun #define DIV_FROM_REG(val)		(1 << (val))
254*4882a593Smuzhiyun 
div_to_reg(int nr,long val)255*4882a593Smuzhiyun static u8 div_to_reg(int nr, long val)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun 	int i;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	/* fan divisors max out at 128 */
260*4882a593Smuzhiyun 	val = clamp_val(val, 1, 128) >> 1;
261*4882a593Smuzhiyun 	for (i = 0; i < 7; i++) {
262*4882a593Smuzhiyun 		if (val == 0)
263*4882a593Smuzhiyun 			break;
264*4882a593Smuzhiyun 		val >>= 1;
265*4882a593Smuzhiyun 	}
266*4882a593Smuzhiyun 	return (u8) i;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun struct w83791d_data {
270*4882a593Smuzhiyun 	struct device *hwmon_dev;
271*4882a593Smuzhiyun 	struct mutex update_lock;
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	char valid;			/* !=0 if following fields are valid */
274*4882a593Smuzhiyun 	unsigned long last_updated;	/* In jiffies */
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	/* volts */
277*4882a593Smuzhiyun 	u8 in[NUMBER_OF_VIN];		/* Register value */
278*4882a593Smuzhiyun 	u8 in_max[NUMBER_OF_VIN];	/* Register value */
279*4882a593Smuzhiyun 	u8 in_min[NUMBER_OF_VIN];	/* Register value */
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	/* fans */
282*4882a593Smuzhiyun 	u8 fan[NUMBER_OF_FANIN];	/* Register value */
283*4882a593Smuzhiyun 	u8 fan_min[NUMBER_OF_FANIN];	/* Register value */
284*4882a593Smuzhiyun 	u8 fan_div[NUMBER_OF_FANIN];	/* Register encoding, shifted right */
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	/* Temperature sensors */
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	s8 temp1[3];		/* current, over, thyst */
289*4882a593Smuzhiyun 	s16 temp_add[2][3];	/* fixed point value. Top 8 bits are the
290*4882a593Smuzhiyun 				 * integral part, bottom 8 bits are the
291*4882a593Smuzhiyun 				 * fractional part. We only use the top
292*4882a593Smuzhiyun 				 * 9 bits as the resolution is only
293*4882a593Smuzhiyun 				 * to the 0.5 degree C...
294*4882a593Smuzhiyun 				 * two sensors with three values
295*4882a593Smuzhiyun 				 * (cur, over, hyst)
296*4882a593Smuzhiyun 				 */
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	/* PWMs */
299*4882a593Smuzhiyun 	u8 pwm[5];		/* pwm duty cycle */
300*4882a593Smuzhiyun 	u8 pwm_enable[3];	/* pwm enable status for fan 1-3
301*4882a593Smuzhiyun 				 * (fan 4-5 only support manual mode)
302*4882a593Smuzhiyun 				 */
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	u8 temp_target[3];	/* pwm 1-3 target temperature */
305*4882a593Smuzhiyun 	u8 temp_tolerance[3];	/* pwm 1-3 temperature tolerance */
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	/* Misc */
308*4882a593Smuzhiyun 	u32 alarms;		/* realtime status register encoding,combined */
309*4882a593Smuzhiyun 	u8 beep_enable;		/* Global beep enable */
310*4882a593Smuzhiyun 	u32 beep_mask;		/* Mask off specific beeps */
311*4882a593Smuzhiyun 	u8 vid;			/* Register encoding, combined */
312*4882a593Smuzhiyun 	u8 vrm;			/* hwmon-vid */
313*4882a593Smuzhiyun };
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun static int w83791d_probe(struct i2c_client *client);
316*4882a593Smuzhiyun static int w83791d_detect(struct i2c_client *client,
317*4882a593Smuzhiyun 			  struct i2c_board_info *info);
318*4882a593Smuzhiyun static int w83791d_remove(struct i2c_client *client);
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun static int w83791d_read(struct i2c_client *client, u8 reg);
321*4882a593Smuzhiyun static int w83791d_write(struct i2c_client *client, u8 reg, u8 value);
322*4882a593Smuzhiyun static struct w83791d_data *w83791d_update_device(struct device *dev);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun #ifdef DEBUG
325*4882a593Smuzhiyun static void w83791d_print_debug(struct w83791d_data *data, struct device *dev);
326*4882a593Smuzhiyun #endif
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun static void w83791d_init_client(struct i2c_client *client);
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun static const struct i2c_device_id w83791d_id[] = {
331*4882a593Smuzhiyun 	{ "w83791d", 0 },
332*4882a593Smuzhiyun 	{ }
333*4882a593Smuzhiyun };
334*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, w83791d_id);
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun static struct i2c_driver w83791d_driver = {
337*4882a593Smuzhiyun 	.class		= I2C_CLASS_HWMON,
338*4882a593Smuzhiyun 	.driver = {
339*4882a593Smuzhiyun 		.name = "w83791d",
340*4882a593Smuzhiyun 	},
341*4882a593Smuzhiyun 	.probe_new	= w83791d_probe,
342*4882a593Smuzhiyun 	.remove		= w83791d_remove,
343*4882a593Smuzhiyun 	.id_table	= w83791d_id,
344*4882a593Smuzhiyun 	.detect		= w83791d_detect,
345*4882a593Smuzhiyun 	.address_list	= normal_i2c,
346*4882a593Smuzhiyun };
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun /* following are the sysfs callback functions */
349*4882a593Smuzhiyun #define show_in_reg(reg) \
350*4882a593Smuzhiyun static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
351*4882a593Smuzhiyun 			char *buf) \
352*4882a593Smuzhiyun { \
353*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = \
354*4882a593Smuzhiyun 						to_sensor_dev_attr(attr); \
355*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev); \
356*4882a593Smuzhiyun 	int nr = sensor_attr->index; \
357*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", IN_FROM_REG(data->reg[nr])); \
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun show_in_reg(in);
361*4882a593Smuzhiyun show_in_reg(in_min);
362*4882a593Smuzhiyun show_in_reg(in_max);
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun #define store_in_reg(REG, reg) \
365*4882a593Smuzhiyun static ssize_t store_in_##reg(struct device *dev, \
366*4882a593Smuzhiyun 				struct device_attribute *attr, \
367*4882a593Smuzhiyun 				const char *buf, size_t count) \
368*4882a593Smuzhiyun { \
369*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = \
370*4882a593Smuzhiyun 						to_sensor_dev_attr(attr); \
371*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev); \
372*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client); \
373*4882a593Smuzhiyun 	int nr = sensor_attr->index; \
374*4882a593Smuzhiyun 	unsigned long val; \
375*4882a593Smuzhiyun 	int err = kstrtoul(buf, 10, &val); \
376*4882a593Smuzhiyun 	if (err) \
377*4882a593Smuzhiyun 		return err; \
378*4882a593Smuzhiyun 	mutex_lock(&data->update_lock); \
379*4882a593Smuzhiyun 	data->in_##reg[nr] = IN_TO_REG(val); \
380*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_IN_##REG[nr], data->in_##reg[nr]); \
381*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock); \
382*4882a593Smuzhiyun 	 \
383*4882a593Smuzhiyun 	return count; \
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun store_in_reg(MIN, min);
386*4882a593Smuzhiyun store_in_reg(MAX, max);
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun static struct sensor_device_attribute sda_in_input[] = {
389*4882a593Smuzhiyun 	SENSOR_ATTR(in0_input, S_IRUGO, show_in, NULL, 0),
390*4882a593Smuzhiyun 	SENSOR_ATTR(in1_input, S_IRUGO, show_in, NULL, 1),
391*4882a593Smuzhiyun 	SENSOR_ATTR(in2_input, S_IRUGO, show_in, NULL, 2),
392*4882a593Smuzhiyun 	SENSOR_ATTR(in3_input, S_IRUGO, show_in, NULL, 3),
393*4882a593Smuzhiyun 	SENSOR_ATTR(in4_input, S_IRUGO, show_in, NULL, 4),
394*4882a593Smuzhiyun 	SENSOR_ATTR(in5_input, S_IRUGO, show_in, NULL, 5),
395*4882a593Smuzhiyun 	SENSOR_ATTR(in6_input, S_IRUGO, show_in, NULL, 6),
396*4882a593Smuzhiyun 	SENSOR_ATTR(in7_input, S_IRUGO, show_in, NULL, 7),
397*4882a593Smuzhiyun 	SENSOR_ATTR(in8_input, S_IRUGO, show_in, NULL, 8),
398*4882a593Smuzhiyun 	SENSOR_ATTR(in9_input, S_IRUGO, show_in, NULL, 9),
399*4882a593Smuzhiyun };
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun static struct sensor_device_attribute sda_in_min[] = {
402*4882a593Smuzhiyun 	SENSOR_ATTR(in0_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 0),
403*4882a593Smuzhiyun 	SENSOR_ATTR(in1_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 1),
404*4882a593Smuzhiyun 	SENSOR_ATTR(in2_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 2),
405*4882a593Smuzhiyun 	SENSOR_ATTR(in3_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 3),
406*4882a593Smuzhiyun 	SENSOR_ATTR(in4_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 4),
407*4882a593Smuzhiyun 	SENSOR_ATTR(in5_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 5),
408*4882a593Smuzhiyun 	SENSOR_ATTR(in6_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 6),
409*4882a593Smuzhiyun 	SENSOR_ATTR(in7_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 7),
410*4882a593Smuzhiyun 	SENSOR_ATTR(in8_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 8),
411*4882a593Smuzhiyun 	SENSOR_ATTR(in9_min, S_IWUSR | S_IRUGO, show_in_min, store_in_min, 9),
412*4882a593Smuzhiyun };
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun static struct sensor_device_attribute sda_in_max[] = {
415*4882a593Smuzhiyun 	SENSOR_ATTR(in0_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 0),
416*4882a593Smuzhiyun 	SENSOR_ATTR(in1_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 1),
417*4882a593Smuzhiyun 	SENSOR_ATTR(in2_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 2),
418*4882a593Smuzhiyun 	SENSOR_ATTR(in3_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 3),
419*4882a593Smuzhiyun 	SENSOR_ATTR(in4_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 4),
420*4882a593Smuzhiyun 	SENSOR_ATTR(in5_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 5),
421*4882a593Smuzhiyun 	SENSOR_ATTR(in6_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 6),
422*4882a593Smuzhiyun 	SENSOR_ATTR(in7_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 7),
423*4882a593Smuzhiyun 	SENSOR_ATTR(in8_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 8),
424*4882a593Smuzhiyun 	SENSOR_ATTR(in9_max, S_IWUSR | S_IRUGO, show_in_max, store_in_max, 9),
425*4882a593Smuzhiyun };
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 
show_beep(struct device * dev,struct device_attribute * attr,char * buf)428*4882a593Smuzhiyun static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
429*4882a593Smuzhiyun 			char *buf)
430*4882a593Smuzhiyun {
431*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr =
432*4882a593Smuzhiyun 						to_sensor_dev_attr(attr);
433*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
434*4882a593Smuzhiyun 	int bitnr = sensor_attr->index;
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", (data->beep_mask >> bitnr) & 1);
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun 
store_beep(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)439*4882a593Smuzhiyun static ssize_t store_beep(struct device *dev, struct device_attribute *attr,
440*4882a593Smuzhiyun 			const char *buf, size_t count)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr =
443*4882a593Smuzhiyun 						to_sensor_dev_attr(attr);
444*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
445*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
446*4882a593Smuzhiyun 	int bitnr = sensor_attr->index;
447*4882a593Smuzhiyun 	int bytenr = bitnr / 8;
448*4882a593Smuzhiyun 	unsigned long val;
449*4882a593Smuzhiyun 	int err;
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	err = kstrtoul(buf, 10, &val);
452*4882a593Smuzhiyun 	if (err)
453*4882a593Smuzhiyun 		return err;
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	val = val ? 1 : 0;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	data->beep_mask &= ~(0xff << (bytenr * 8));
460*4882a593Smuzhiyun 	data->beep_mask |= w83791d_read(client, W83791D_REG_BEEP_CTRL[bytenr])
461*4882a593Smuzhiyun 		<< (bytenr * 8);
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	data->beep_mask &= ~(1 << bitnr);
464*4882a593Smuzhiyun 	data->beep_mask |= val << bitnr;
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_BEEP_CTRL[bytenr],
467*4882a593Smuzhiyun 		(data->beep_mask >> (bytenr * 8)) & 0xff);
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	return count;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun 
show_alarm(struct device * dev,struct device_attribute * attr,char * buf)474*4882a593Smuzhiyun static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
475*4882a593Smuzhiyun 			char *buf)
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr =
478*4882a593Smuzhiyun 						to_sensor_dev_attr(attr);
479*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
480*4882a593Smuzhiyun 	int bitnr = sensor_attr->index;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", (data->alarms >> bitnr) & 1);
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun /*
486*4882a593Smuzhiyun  * Note: The bitmask for the beep enable/disable is different than
487*4882a593Smuzhiyun  * the bitmask for the alarm.
488*4882a593Smuzhiyun  */
489*4882a593Smuzhiyun static struct sensor_device_attribute sda_in_beep[] = {
490*4882a593Smuzhiyun 	SENSOR_ATTR(in0_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 0),
491*4882a593Smuzhiyun 	SENSOR_ATTR(in1_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 13),
492*4882a593Smuzhiyun 	SENSOR_ATTR(in2_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 2),
493*4882a593Smuzhiyun 	SENSOR_ATTR(in3_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 3),
494*4882a593Smuzhiyun 	SENSOR_ATTR(in4_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 8),
495*4882a593Smuzhiyun 	SENSOR_ATTR(in5_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 9),
496*4882a593Smuzhiyun 	SENSOR_ATTR(in6_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 10),
497*4882a593Smuzhiyun 	SENSOR_ATTR(in7_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 16),
498*4882a593Smuzhiyun 	SENSOR_ATTR(in8_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 17),
499*4882a593Smuzhiyun 	SENSOR_ATTR(in9_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 14),
500*4882a593Smuzhiyun };
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun static struct sensor_device_attribute sda_in_alarm[] = {
503*4882a593Smuzhiyun 	SENSOR_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 0),
504*4882a593Smuzhiyun 	SENSOR_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 1),
505*4882a593Smuzhiyun 	SENSOR_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 2),
506*4882a593Smuzhiyun 	SENSOR_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 3),
507*4882a593Smuzhiyun 	SENSOR_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 8),
508*4882a593Smuzhiyun 	SENSOR_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 9),
509*4882a593Smuzhiyun 	SENSOR_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 10),
510*4882a593Smuzhiyun 	SENSOR_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 19),
511*4882a593Smuzhiyun 	SENSOR_ATTR(in8_alarm, S_IRUGO, show_alarm, NULL, 20),
512*4882a593Smuzhiyun 	SENSOR_ATTR(in9_alarm, S_IRUGO, show_alarm, NULL, 14),
513*4882a593Smuzhiyun };
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun #define show_fan_reg(reg) \
516*4882a593Smuzhiyun static ssize_t show_##reg(struct device *dev, struct device_attribute *attr, \
517*4882a593Smuzhiyun 				char *buf) \
518*4882a593Smuzhiyun { \
519*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = \
520*4882a593Smuzhiyun 						to_sensor_dev_attr(attr); \
521*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev); \
522*4882a593Smuzhiyun 	int nr = sensor_attr->index; \
523*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", \
524*4882a593Smuzhiyun 		FAN_FROM_REG(data->reg[nr], DIV_FROM_REG(data->fan_div[nr]))); \
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun show_fan_reg(fan);
528*4882a593Smuzhiyun show_fan_reg(fan_min);
529*4882a593Smuzhiyun 
store_fan_min(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)530*4882a593Smuzhiyun static ssize_t store_fan_min(struct device *dev, struct device_attribute *attr,
531*4882a593Smuzhiyun 				const char *buf, size_t count)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
534*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
535*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
536*4882a593Smuzhiyun 	int nr = sensor_attr->index;
537*4882a593Smuzhiyun 	unsigned long val;
538*4882a593Smuzhiyun 	int err;
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	err = kstrtoul(buf, 10, &val);
541*4882a593Smuzhiyun 	if (err)
542*4882a593Smuzhiyun 		return err;
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
545*4882a593Smuzhiyun 	data->fan_min[nr] = fan_to_reg(val, DIV_FROM_REG(data->fan_div[nr]));
546*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_FAN_MIN[nr], data->fan_min[nr]);
547*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	return count;
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun 
show_fan_div(struct device * dev,struct device_attribute * attr,char * buf)552*4882a593Smuzhiyun static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
553*4882a593Smuzhiyun 				char *buf)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
556*4882a593Smuzhiyun 	int nr = sensor_attr->index;
557*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
558*4882a593Smuzhiyun 	return sprintf(buf, "%u\n", DIV_FROM_REG(data->fan_div[nr]));
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun /*
562*4882a593Smuzhiyun  * Note: we save and restore the fan minimum here, because its value is
563*4882a593Smuzhiyun  * determined in part by the fan divisor.  This follows the principle of
564*4882a593Smuzhiyun  * least surprise; the user doesn't expect the fan minimum to change just
565*4882a593Smuzhiyun  * because the divisor changed.
566*4882a593Smuzhiyun  */
store_fan_div(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)567*4882a593Smuzhiyun static ssize_t store_fan_div(struct device *dev, struct device_attribute *attr,
568*4882a593Smuzhiyun 				const char *buf, size_t count)
569*4882a593Smuzhiyun {
570*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
571*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
572*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
573*4882a593Smuzhiyun 	int nr = sensor_attr->index;
574*4882a593Smuzhiyun 	unsigned long min;
575*4882a593Smuzhiyun 	u8 tmp_fan_div;
576*4882a593Smuzhiyun 	u8 fan_div_reg;
577*4882a593Smuzhiyun 	u8 vbat_reg;
578*4882a593Smuzhiyun 	int indx = 0;
579*4882a593Smuzhiyun 	u8 keep_mask = 0;
580*4882a593Smuzhiyun 	u8 new_shift = 0;
581*4882a593Smuzhiyun 	unsigned long val;
582*4882a593Smuzhiyun 	int err;
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	err = kstrtoul(buf, 10, &val);
585*4882a593Smuzhiyun 	if (err)
586*4882a593Smuzhiyun 		return err;
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	/* Save fan_min */
589*4882a593Smuzhiyun 	min = FAN_FROM_REG(data->fan_min[nr], DIV_FROM_REG(data->fan_div[nr]));
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
592*4882a593Smuzhiyun 	data->fan_div[nr] = div_to_reg(nr, val);
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	switch (nr) {
595*4882a593Smuzhiyun 	case 0:
596*4882a593Smuzhiyun 		indx = 0;
597*4882a593Smuzhiyun 		keep_mask = 0xcf;
598*4882a593Smuzhiyun 		new_shift = 4;
599*4882a593Smuzhiyun 		break;
600*4882a593Smuzhiyun 	case 1:
601*4882a593Smuzhiyun 		indx = 0;
602*4882a593Smuzhiyun 		keep_mask = 0x3f;
603*4882a593Smuzhiyun 		new_shift = 6;
604*4882a593Smuzhiyun 		break;
605*4882a593Smuzhiyun 	case 2:
606*4882a593Smuzhiyun 		indx = 1;
607*4882a593Smuzhiyun 		keep_mask = 0x3f;
608*4882a593Smuzhiyun 		new_shift = 6;
609*4882a593Smuzhiyun 		break;
610*4882a593Smuzhiyun 	case 3:
611*4882a593Smuzhiyun 		indx = 2;
612*4882a593Smuzhiyun 		keep_mask = 0xf8;
613*4882a593Smuzhiyun 		new_shift = 0;
614*4882a593Smuzhiyun 		break;
615*4882a593Smuzhiyun 	case 4:
616*4882a593Smuzhiyun 		indx = 2;
617*4882a593Smuzhiyun 		keep_mask = 0x8f;
618*4882a593Smuzhiyun 		new_shift = 4;
619*4882a593Smuzhiyun 		break;
620*4882a593Smuzhiyun #ifdef DEBUG
621*4882a593Smuzhiyun 	default:
622*4882a593Smuzhiyun 		dev_warn(dev, "store_fan_div: Unexpected nr seen: %d\n", nr);
623*4882a593Smuzhiyun 		count = -EINVAL;
624*4882a593Smuzhiyun 		goto err_exit;
625*4882a593Smuzhiyun #endif
626*4882a593Smuzhiyun 	}
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 	fan_div_reg = w83791d_read(client, W83791D_REG_FAN_DIV[indx])
629*4882a593Smuzhiyun 			& keep_mask;
630*4882a593Smuzhiyun 	tmp_fan_div = (data->fan_div[nr] << new_shift) & ~keep_mask;
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_FAN_DIV[indx],
633*4882a593Smuzhiyun 				fan_div_reg | tmp_fan_div);
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 	/* Bit 2 of fans 0-2 is stored in the vbat register (bits 5-7) */
636*4882a593Smuzhiyun 	if (nr < 3) {
637*4882a593Smuzhiyun 		keep_mask = ~(1 << (nr + 5));
638*4882a593Smuzhiyun 		vbat_reg = w83791d_read(client, W83791D_REG_VBAT)
639*4882a593Smuzhiyun 				& keep_mask;
640*4882a593Smuzhiyun 		tmp_fan_div = (data->fan_div[nr] << (3 + nr)) & ~keep_mask;
641*4882a593Smuzhiyun 		w83791d_write(client, W83791D_REG_VBAT,
642*4882a593Smuzhiyun 				vbat_reg | tmp_fan_div);
643*4882a593Smuzhiyun 	}
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	/* Restore fan_min */
646*4882a593Smuzhiyun 	data->fan_min[nr] = fan_to_reg(min, DIV_FROM_REG(data->fan_div[nr]));
647*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_FAN_MIN[nr], data->fan_min[nr]);
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun #ifdef DEBUG
650*4882a593Smuzhiyun err_exit:
651*4882a593Smuzhiyun #endif
652*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	return count;
655*4882a593Smuzhiyun }
656*4882a593Smuzhiyun 
657*4882a593Smuzhiyun static struct sensor_device_attribute sda_fan_input[] = {
658*4882a593Smuzhiyun 	SENSOR_ATTR(fan1_input, S_IRUGO, show_fan, NULL, 0),
659*4882a593Smuzhiyun 	SENSOR_ATTR(fan2_input, S_IRUGO, show_fan, NULL, 1),
660*4882a593Smuzhiyun 	SENSOR_ATTR(fan3_input, S_IRUGO, show_fan, NULL, 2),
661*4882a593Smuzhiyun 	SENSOR_ATTR(fan4_input, S_IRUGO, show_fan, NULL, 3),
662*4882a593Smuzhiyun 	SENSOR_ATTR(fan5_input, S_IRUGO, show_fan, NULL, 4),
663*4882a593Smuzhiyun };
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun static struct sensor_device_attribute sda_fan_min[] = {
666*4882a593Smuzhiyun 	SENSOR_ATTR(fan1_min, S_IWUSR | S_IRUGO,
667*4882a593Smuzhiyun 			show_fan_min, store_fan_min, 0),
668*4882a593Smuzhiyun 	SENSOR_ATTR(fan2_min, S_IWUSR | S_IRUGO,
669*4882a593Smuzhiyun 			show_fan_min, store_fan_min, 1),
670*4882a593Smuzhiyun 	SENSOR_ATTR(fan3_min, S_IWUSR | S_IRUGO,
671*4882a593Smuzhiyun 			show_fan_min, store_fan_min, 2),
672*4882a593Smuzhiyun 	SENSOR_ATTR(fan4_min, S_IWUSR | S_IRUGO,
673*4882a593Smuzhiyun 			show_fan_min, store_fan_min, 3),
674*4882a593Smuzhiyun 	SENSOR_ATTR(fan5_min, S_IWUSR | S_IRUGO,
675*4882a593Smuzhiyun 			show_fan_min, store_fan_min, 4),
676*4882a593Smuzhiyun };
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun static struct sensor_device_attribute sda_fan_div[] = {
679*4882a593Smuzhiyun 	SENSOR_ATTR(fan1_div, S_IWUSR | S_IRUGO,
680*4882a593Smuzhiyun 			show_fan_div, store_fan_div, 0),
681*4882a593Smuzhiyun 	SENSOR_ATTR(fan2_div, S_IWUSR | S_IRUGO,
682*4882a593Smuzhiyun 			show_fan_div, store_fan_div, 1),
683*4882a593Smuzhiyun 	SENSOR_ATTR(fan3_div, S_IWUSR | S_IRUGO,
684*4882a593Smuzhiyun 			show_fan_div, store_fan_div, 2),
685*4882a593Smuzhiyun 	SENSOR_ATTR(fan4_div, S_IWUSR | S_IRUGO,
686*4882a593Smuzhiyun 			show_fan_div, store_fan_div, 3),
687*4882a593Smuzhiyun 	SENSOR_ATTR(fan5_div, S_IWUSR | S_IRUGO,
688*4882a593Smuzhiyun 			show_fan_div, store_fan_div, 4),
689*4882a593Smuzhiyun };
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun static struct sensor_device_attribute sda_fan_beep[] = {
692*4882a593Smuzhiyun 	SENSOR_ATTR(fan1_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 6),
693*4882a593Smuzhiyun 	SENSOR_ATTR(fan2_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 7),
694*4882a593Smuzhiyun 	SENSOR_ATTR(fan3_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 11),
695*4882a593Smuzhiyun 	SENSOR_ATTR(fan4_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 21),
696*4882a593Smuzhiyun 	SENSOR_ATTR(fan5_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 22),
697*4882a593Smuzhiyun };
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun static struct sensor_device_attribute sda_fan_alarm[] = {
700*4882a593Smuzhiyun 	SENSOR_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 6),
701*4882a593Smuzhiyun 	SENSOR_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 7),
702*4882a593Smuzhiyun 	SENSOR_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 11),
703*4882a593Smuzhiyun 	SENSOR_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 21),
704*4882a593Smuzhiyun 	SENSOR_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 22),
705*4882a593Smuzhiyun };
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun /* read/write PWMs */
show_pwm(struct device * dev,struct device_attribute * attr,char * buf)708*4882a593Smuzhiyun static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
709*4882a593Smuzhiyun 				char *buf)
710*4882a593Smuzhiyun {
711*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
712*4882a593Smuzhiyun 	int nr = sensor_attr->index;
713*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
714*4882a593Smuzhiyun 	return sprintf(buf, "%u\n", data->pwm[nr]);
715*4882a593Smuzhiyun }
716*4882a593Smuzhiyun 
store_pwm(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)717*4882a593Smuzhiyun static ssize_t store_pwm(struct device *dev, struct device_attribute *attr,
718*4882a593Smuzhiyun 		const char *buf, size_t count)
719*4882a593Smuzhiyun {
720*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
721*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
722*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
723*4882a593Smuzhiyun 	int nr = sensor_attr->index;
724*4882a593Smuzhiyun 	unsigned long val;
725*4882a593Smuzhiyun 
726*4882a593Smuzhiyun 	if (kstrtoul(buf, 10, &val))
727*4882a593Smuzhiyun 		return -EINVAL;
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
730*4882a593Smuzhiyun 	data->pwm[nr] = clamp_val(val, 0, 255);
731*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_PWM[nr], data->pwm[nr]);
732*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
733*4882a593Smuzhiyun 	return count;
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun static struct sensor_device_attribute sda_pwm[] = {
737*4882a593Smuzhiyun 	SENSOR_ATTR(pwm1, S_IWUSR | S_IRUGO,
738*4882a593Smuzhiyun 			show_pwm, store_pwm, 0),
739*4882a593Smuzhiyun 	SENSOR_ATTR(pwm2, S_IWUSR | S_IRUGO,
740*4882a593Smuzhiyun 			show_pwm, store_pwm, 1),
741*4882a593Smuzhiyun 	SENSOR_ATTR(pwm3, S_IWUSR | S_IRUGO,
742*4882a593Smuzhiyun 			show_pwm, store_pwm, 2),
743*4882a593Smuzhiyun 	SENSOR_ATTR(pwm4, S_IWUSR | S_IRUGO,
744*4882a593Smuzhiyun 			show_pwm, store_pwm, 3),
745*4882a593Smuzhiyun 	SENSOR_ATTR(pwm5, S_IWUSR | S_IRUGO,
746*4882a593Smuzhiyun 			show_pwm, store_pwm, 4),
747*4882a593Smuzhiyun };
748*4882a593Smuzhiyun 
show_pwmenable(struct device * dev,struct device_attribute * attr,char * buf)749*4882a593Smuzhiyun static ssize_t show_pwmenable(struct device *dev, struct device_attribute *attr,
750*4882a593Smuzhiyun 				char *buf)
751*4882a593Smuzhiyun {
752*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
753*4882a593Smuzhiyun 	int nr = sensor_attr->index;
754*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
755*4882a593Smuzhiyun 	return sprintf(buf, "%u\n", data->pwm_enable[nr] + 1);
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun 
store_pwmenable(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)758*4882a593Smuzhiyun static ssize_t store_pwmenable(struct device *dev,
759*4882a593Smuzhiyun 		struct device_attribute *attr, const char *buf, size_t count)
760*4882a593Smuzhiyun {
761*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
762*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
763*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
764*4882a593Smuzhiyun 	int nr = sensor_attr->index;
765*4882a593Smuzhiyun 	unsigned long val;
766*4882a593Smuzhiyun 	u8 reg_cfg_tmp;
767*4882a593Smuzhiyun 	u8 reg_idx = 0;
768*4882a593Smuzhiyun 	u8 val_shift = 0;
769*4882a593Smuzhiyun 	u8 keep_mask = 0;
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun 	int ret = kstrtoul(buf, 10, &val);
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	if (ret || val < 1 || val > 3)
774*4882a593Smuzhiyun 		return -EINVAL;
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
777*4882a593Smuzhiyun 	data->pwm_enable[nr] = val - 1;
778*4882a593Smuzhiyun 	switch (nr) {
779*4882a593Smuzhiyun 	case 0:
780*4882a593Smuzhiyun 		reg_idx = 0;
781*4882a593Smuzhiyun 		val_shift = 2;
782*4882a593Smuzhiyun 		keep_mask = 0xf3;
783*4882a593Smuzhiyun 		break;
784*4882a593Smuzhiyun 	case 1:
785*4882a593Smuzhiyun 		reg_idx = 0;
786*4882a593Smuzhiyun 		val_shift = 4;
787*4882a593Smuzhiyun 		keep_mask = 0xcf;
788*4882a593Smuzhiyun 		break;
789*4882a593Smuzhiyun 	case 2:
790*4882a593Smuzhiyun 		reg_idx = 1;
791*4882a593Smuzhiyun 		val_shift = 2;
792*4882a593Smuzhiyun 		keep_mask = 0xf3;
793*4882a593Smuzhiyun 		break;
794*4882a593Smuzhiyun 	}
795*4882a593Smuzhiyun 
796*4882a593Smuzhiyun 	reg_cfg_tmp = w83791d_read(client, W83791D_REG_FAN_CFG[reg_idx]);
797*4882a593Smuzhiyun 	reg_cfg_tmp = (reg_cfg_tmp & keep_mask) |
798*4882a593Smuzhiyun 					data->pwm_enable[nr] << val_shift;
799*4882a593Smuzhiyun 
800*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_FAN_CFG[reg_idx], reg_cfg_tmp);
801*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun 	return count;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun static struct sensor_device_attribute sda_pwmenable[] = {
806*4882a593Smuzhiyun 	SENSOR_ATTR(pwm1_enable, S_IWUSR | S_IRUGO,
807*4882a593Smuzhiyun 			show_pwmenable, store_pwmenable, 0),
808*4882a593Smuzhiyun 	SENSOR_ATTR(pwm2_enable, S_IWUSR | S_IRUGO,
809*4882a593Smuzhiyun 			show_pwmenable, store_pwmenable, 1),
810*4882a593Smuzhiyun 	SENSOR_ATTR(pwm3_enable, S_IWUSR | S_IRUGO,
811*4882a593Smuzhiyun 			show_pwmenable, store_pwmenable, 2),
812*4882a593Smuzhiyun };
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun /* For Smart Fan I / Thermal Cruise */
show_temp_target(struct device * dev,struct device_attribute * attr,char * buf)815*4882a593Smuzhiyun static ssize_t show_temp_target(struct device *dev,
816*4882a593Smuzhiyun 			struct device_attribute *attr, char *buf)
817*4882a593Smuzhiyun {
818*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
819*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
820*4882a593Smuzhiyun 	int nr = sensor_attr->index;
821*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", TEMP1_FROM_REG(data->temp_target[nr]));
822*4882a593Smuzhiyun }
823*4882a593Smuzhiyun 
store_temp_target(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)824*4882a593Smuzhiyun static ssize_t store_temp_target(struct device *dev,
825*4882a593Smuzhiyun 		struct device_attribute *attr, const char *buf, size_t count)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
828*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
829*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
830*4882a593Smuzhiyun 	int nr = sensor_attr->index;
831*4882a593Smuzhiyun 	long val;
832*4882a593Smuzhiyun 	u8 target_mask;
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun 	if (kstrtol(buf, 10, &val))
835*4882a593Smuzhiyun 		return -EINVAL;
836*4882a593Smuzhiyun 
837*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
838*4882a593Smuzhiyun 	data->temp_target[nr] = TARGET_TEMP_TO_REG(val);
839*4882a593Smuzhiyun 	target_mask = w83791d_read(client,
840*4882a593Smuzhiyun 				W83791D_REG_TEMP_TARGET[nr]) & 0x80;
841*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_TEMP_TARGET[nr],
842*4882a593Smuzhiyun 				data->temp_target[nr] | target_mask);
843*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
844*4882a593Smuzhiyun 	return count;
845*4882a593Smuzhiyun }
846*4882a593Smuzhiyun 
847*4882a593Smuzhiyun static struct sensor_device_attribute sda_temp_target[] = {
848*4882a593Smuzhiyun 	SENSOR_ATTR(temp1_target, S_IWUSR | S_IRUGO,
849*4882a593Smuzhiyun 			show_temp_target, store_temp_target, 0),
850*4882a593Smuzhiyun 	SENSOR_ATTR(temp2_target, S_IWUSR | S_IRUGO,
851*4882a593Smuzhiyun 			show_temp_target, store_temp_target, 1),
852*4882a593Smuzhiyun 	SENSOR_ATTR(temp3_target, S_IWUSR | S_IRUGO,
853*4882a593Smuzhiyun 			show_temp_target, store_temp_target, 2),
854*4882a593Smuzhiyun };
855*4882a593Smuzhiyun 
show_temp_tolerance(struct device * dev,struct device_attribute * attr,char * buf)856*4882a593Smuzhiyun static ssize_t show_temp_tolerance(struct device *dev,
857*4882a593Smuzhiyun 			struct device_attribute *attr, char *buf)
858*4882a593Smuzhiyun {
859*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
860*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
861*4882a593Smuzhiyun 	int nr = sensor_attr->index;
862*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", TEMP1_FROM_REG(data->temp_tolerance[nr]));
863*4882a593Smuzhiyun }
864*4882a593Smuzhiyun 
store_temp_tolerance(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)865*4882a593Smuzhiyun static ssize_t store_temp_tolerance(struct device *dev,
866*4882a593Smuzhiyun 		struct device_attribute *attr, const char *buf, size_t count)
867*4882a593Smuzhiyun {
868*4882a593Smuzhiyun 	struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
869*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
870*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
871*4882a593Smuzhiyun 	int nr = sensor_attr->index;
872*4882a593Smuzhiyun 	unsigned long val;
873*4882a593Smuzhiyun 	u8 target_mask;
874*4882a593Smuzhiyun 	u8 reg_idx = 0;
875*4882a593Smuzhiyun 	u8 val_shift = 0;
876*4882a593Smuzhiyun 	u8 keep_mask = 0;
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun 	if (kstrtoul(buf, 10, &val))
879*4882a593Smuzhiyun 		return -EINVAL;
880*4882a593Smuzhiyun 
881*4882a593Smuzhiyun 	switch (nr) {
882*4882a593Smuzhiyun 	case 0:
883*4882a593Smuzhiyun 		reg_idx = 0;
884*4882a593Smuzhiyun 		val_shift = 0;
885*4882a593Smuzhiyun 		keep_mask = 0xf0;
886*4882a593Smuzhiyun 		break;
887*4882a593Smuzhiyun 	case 1:
888*4882a593Smuzhiyun 		reg_idx = 0;
889*4882a593Smuzhiyun 		val_shift = 4;
890*4882a593Smuzhiyun 		keep_mask = 0x0f;
891*4882a593Smuzhiyun 		break;
892*4882a593Smuzhiyun 	case 2:
893*4882a593Smuzhiyun 		reg_idx = 1;
894*4882a593Smuzhiyun 		val_shift = 0;
895*4882a593Smuzhiyun 		keep_mask = 0xf0;
896*4882a593Smuzhiyun 		break;
897*4882a593Smuzhiyun 	}
898*4882a593Smuzhiyun 
899*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
900*4882a593Smuzhiyun 	data->temp_tolerance[nr] = TOL_TEMP_TO_REG(val);
901*4882a593Smuzhiyun 	target_mask = w83791d_read(client,
902*4882a593Smuzhiyun 			W83791D_REG_TEMP_TOL[reg_idx]) & keep_mask;
903*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_TEMP_TOL[reg_idx],
904*4882a593Smuzhiyun 			(data->temp_tolerance[nr] << val_shift) | target_mask);
905*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
906*4882a593Smuzhiyun 	return count;
907*4882a593Smuzhiyun }
908*4882a593Smuzhiyun 
909*4882a593Smuzhiyun static struct sensor_device_attribute sda_temp_tolerance[] = {
910*4882a593Smuzhiyun 	SENSOR_ATTR(temp1_tolerance, S_IWUSR | S_IRUGO,
911*4882a593Smuzhiyun 			show_temp_tolerance, store_temp_tolerance, 0),
912*4882a593Smuzhiyun 	SENSOR_ATTR(temp2_tolerance, S_IWUSR | S_IRUGO,
913*4882a593Smuzhiyun 			show_temp_tolerance, store_temp_tolerance, 1),
914*4882a593Smuzhiyun 	SENSOR_ATTR(temp3_tolerance, S_IWUSR | S_IRUGO,
915*4882a593Smuzhiyun 			show_temp_tolerance, store_temp_tolerance, 2),
916*4882a593Smuzhiyun };
917*4882a593Smuzhiyun 
918*4882a593Smuzhiyun /* read/write the temperature1, includes measured value and limits */
show_temp1(struct device * dev,struct device_attribute * devattr,char * buf)919*4882a593Smuzhiyun static ssize_t show_temp1(struct device *dev, struct device_attribute *devattr,
920*4882a593Smuzhiyun 				char *buf)
921*4882a593Smuzhiyun {
922*4882a593Smuzhiyun 	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
923*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
924*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", TEMP1_FROM_REG(data->temp1[attr->index]));
925*4882a593Smuzhiyun }
926*4882a593Smuzhiyun 
store_temp1(struct device * dev,struct device_attribute * devattr,const char * buf,size_t count)927*4882a593Smuzhiyun static ssize_t store_temp1(struct device *dev, struct device_attribute *devattr,
928*4882a593Smuzhiyun 				const char *buf, size_t count)
929*4882a593Smuzhiyun {
930*4882a593Smuzhiyun 	struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
931*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
932*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
933*4882a593Smuzhiyun 	int nr = attr->index;
934*4882a593Smuzhiyun 	long val;
935*4882a593Smuzhiyun 	int err;
936*4882a593Smuzhiyun 
937*4882a593Smuzhiyun 	err = kstrtol(buf, 10, &val);
938*4882a593Smuzhiyun 	if (err)
939*4882a593Smuzhiyun 		return err;
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
942*4882a593Smuzhiyun 	data->temp1[nr] = TEMP1_TO_REG(val);
943*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_TEMP1[nr], data->temp1[nr]);
944*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
945*4882a593Smuzhiyun 	return count;
946*4882a593Smuzhiyun }
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun /* read/write temperature2-3, includes measured value and limits */
show_temp23(struct device * dev,struct device_attribute * devattr,char * buf)949*4882a593Smuzhiyun static ssize_t show_temp23(struct device *dev, struct device_attribute *devattr,
950*4882a593Smuzhiyun 				char *buf)
951*4882a593Smuzhiyun {
952*4882a593Smuzhiyun 	struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
953*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
954*4882a593Smuzhiyun 	int nr = attr->nr;
955*4882a593Smuzhiyun 	int index = attr->index;
956*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", TEMP23_FROM_REG(data->temp_add[nr][index]));
957*4882a593Smuzhiyun }
958*4882a593Smuzhiyun 
store_temp23(struct device * dev,struct device_attribute * devattr,const char * buf,size_t count)959*4882a593Smuzhiyun static ssize_t store_temp23(struct device *dev,
960*4882a593Smuzhiyun 				struct device_attribute *devattr,
961*4882a593Smuzhiyun 				const char *buf, size_t count)
962*4882a593Smuzhiyun {
963*4882a593Smuzhiyun 	struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
964*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
965*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
966*4882a593Smuzhiyun 	long val;
967*4882a593Smuzhiyun 	int err;
968*4882a593Smuzhiyun 	int nr = attr->nr;
969*4882a593Smuzhiyun 	int index = attr->index;
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun 	err = kstrtol(buf, 10, &val);
972*4882a593Smuzhiyun 	if (err)
973*4882a593Smuzhiyun 		return err;
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
976*4882a593Smuzhiyun 	data->temp_add[nr][index] = TEMP23_TO_REG(val);
977*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_TEMP_ADD[nr][index * 2],
978*4882a593Smuzhiyun 				data->temp_add[nr][index] >> 8);
979*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_TEMP_ADD[nr][index * 2 + 1],
980*4882a593Smuzhiyun 				data->temp_add[nr][index] & 0x80);
981*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
982*4882a593Smuzhiyun 
983*4882a593Smuzhiyun 	return count;
984*4882a593Smuzhiyun }
985*4882a593Smuzhiyun 
986*4882a593Smuzhiyun static struct sensor_device_attribute_2 sda_temp_input[] = {
987*4882a593Smuzhiyun 	SENSOR_ATTR_2(temp1_input, S_IRUGO, show_temp1, NULL, 0, 0),
988*4882a593Smuzhiyun 	SENSOR_ATTR_2(temp2_input, S_IRUGO, show_temp23, NULL, 0, 0),
989*4882a593Smuzhiyun 	SENSOR_ATTR_2(temp3_input, S_IRUGO, show_temp23, NULL, 1, 0),
990*4882a593Smuzhiyun };
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun static struct sensor_device_attribute_2 sda_temp_max[] = {
993*4882a593Smuzhiyun 	SENSOR_ATTR_2(temp1_max, S_IRUGO | S_IWUSR,
994*4882a593Smuzhiyun 			show_temp1, store_temp1, 0, 1),
995*4882a593Smuzhiyun 	SENSOR_ATTR_2(temp2_max, S_IRUGO | S_IWUSR,
996*4882a593Smuzhiyun 			show_temp23, store_temp23, 0, 1),
997*4882a593Smuzhiyun 	SENSOR_ATTR_2(temp3_max, S_IRUGO | S_IWUSR,
998*4882a593Smuzhiyun 			show_temp23, store_temp23, 1, 1),
999*4882a593Smuzhiyun };
1000*4882a593Smuzhiyun 
1001*4882a593Smuzhiyun static struct sensor_device_attribute_2 sda_temp_max_hyst[] = {
1002*4882a593Smuzhiyun 	SENSOR_ATTR_2(temp1_max_hyst, S_IRUGO | S_IWUSR,
1003*4882a593Smuzhiyun 			show_temp1, store_temp1, 0, 2),
1004*4882a593Smuzhiyun 	SENSOR_ATTR_2(temp2_max_hyst, S_IRUGO | S_IWUSR,
1005*4882a593Smuzhiyun 			show_temp23, store_temp23, 0, 2),
1006*4882a593Smuzhiyun 	SENSOR_ATTR_2(temp3_max_hyst, S_IRUGO | S_IWUSR,
1007*4882a593Smuzhiyun 			show_temp23, store_temp23, 1, 2),
1008*4882a593Smuzhiyun };
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun /*
1011*4882a593Smuzhiyun  * Note: The bitmask for the beep enable/disable is different than
1012*4882a593Smuzhiyun  * the bitmask for the alarm.
1013*4882a593Smuzhiyun  */
1014*4882a593Smuzhiyun static struct sensor_device_attribute sda_temp_beep[] = {
1015*4882a593Smuzhiyun 	SENSOR_ATTR(temp1_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 4),
1016*4882a593Smuzhiyun 	SENSOR_ATTR(temp2_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 5),
1017*4882a593Smuzhiyun 	SENSOR_ATTR(temp3_beep, S_IWUSR | S_IRUGO, show_beep, store_beep, 1),
1018*4882a593Smuzhiyun };
1019*4882a593Smuzhiyun 
1020*4882a593Smuzhiyun static struct sensor_device_attribute sda_temp_alarm[] = {
1021*4882a593Smuzhiyun 	SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
1022*4882a593Smuzhiyun 	SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
1023*4882a593Smuzhiyun 	SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
1024*4882a593Smuzhiyun };
1025*4882a593Smuzhiyun 
1026*4882a593Smuzhiyun /* get realtime status of all sensors items: voltage, temp, fan */
alarms_show(struct device * dev,struct device_attribute * attr,char * buf)1027*4882a593Smuzhiyun static ssize_t alarms_show(struct device *dev, struct device_attribute *attr,
1028*4882a593Smuzhiyun 			   char *buf)
1029*4882a593Smuzhiyun {
1030*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
1031*4882a593Smuzhiyun 	return sprintf(buf, "%u\n", data->alarms);
1032*4882a593Smuzhiyun }
1033*4882a593Smuzhiyun 
1034*4882a593Smuzhiyun static DEVICE_ATTR_RO(alarms);
1035*4882a593Smuzhiyun 
1036*4882a593Smuzhiyun /* Beep control */
1037*4882a593Smuzhiyun 
1038*4882a593Smuzhiyun #define GLOBAL_BEEP_ENABLE_SHIFT	15
1039*4882a593Smuzhiyun #define GLOBAL_BEEP_ENABLE_MASK		(1 << GLOBAL_BEEP_ENABLE_SHIFT)
1040*4882a593Smuzhiyun 
show_beep_enable(struct device * dev,struct device_attribute * attr,char * buf)1041*4882a593Smuzhiyun static ssize_t show_beep_enable(struct device *dev,
1042*4882a593Smuzhiyun 				struct device_attribute *attr, char *buf)
1043*4882a593Smuzhiyun {
1044*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
1045*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", data->beep_enable);
1046*4882a593Smuzhiyun }
1047*4882a593Smuzhiyun 
show_beep_mask(struct device * dev,struct device_attribute * attr,char * buf)1048*4882a593Smuzhiyun static ssize_t show_beep_mask(struct device *dev,
1049*4882a593Smuzhiyun 				struct device_attribute *attr, char *buf)
1050*4882a593Smuzhiyun {
1051*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
1052*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", BEEP_MASK_FROM_REG(data->beep_mask));
1053*4882a593Smuzhiyun }
1054*4882a593Smuzhiyun 
1055*4882a593Smuzhiyun 
store_beep_mask(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1056*4882a593Smuzhiyun static ssize_t store_beep_mask(struct device *dev,
1057*4882a593Smuzhiyun 				struct device_attribute *attr,
1058*4882a593Smuzhiyun 				const char *buf, size_t count)
1059*4882a593Smuzhiyun {
1060*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1061*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
1062*4882a593Smuzhiyun 	int i;
1063*4882a593Smuzhiyun 	long val;
1064*4882a593Smuzhiyun 	int err;
1065*4882a593Smuzhiyun 
1066*4882a593Smuzhiyun 	err = kstrtol(buf, 10, &val);
1067*4882a593Smuzhiyun 	if (err)
1068*4882a593Smuzhiyun 		return err;
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 	/*
1073*4882a593Smuzhiyun 	 * The beep_enable state overrides any enabling request from
1074*4882a593Smuzhiyun 	 * the masks
1075*4882a593Smuzhiyun 	 */
1076*4882a593Smuzhiyun 	data->beep_mask = BEEP_MASK_TO_REG(val) & ~GLOBAL_BEEP_ENABLE_MASK;
1077*4882a593Smuzhiyun 	data->beep_mask |= (data->beep_enable << GLOBAL_BEEP_ENABLE_SHIFT);
1078*4882a593Smuzhiyun 
1079*4882a593Smuzhiyun 	val = data->beep_mask;
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	for (i = 0; i < 3; i++) {
1082*4882a593Smuzhiyun 		w83791d_write(client, W83791D_REG_BEEP_CTRL[i], (val & 0xff));
1083*4882a593Smuzhiyun 		val >>= 8;
1084*4882a593Smuzhiyun 	}
1085*4882a593Smuzhiyun 
1086*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
1087*4882a593Smuzhiyun 
1088*4882a593Smuzhiyun 	return count;
1089*4882a593Smuzhiyun }
1090*4882a593Smuzhiyun 
store_beep_enable(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1091*4882a593Smuzhiyun static ssize_t store_beep_enable(struct device *dev,
1092*4882a593Smuzhiyun 				struct device_attribute *attr,
1093*4882a593Smuzhiyun 				const char *buf, size_t count)
1094*4882a593Smuzhiyun {
1095*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1096*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
1097*4882a593Smuzhiyun 	long val;
1098*4882a593Smuzhiyun 	int err;
1099*4882a593Smuzhiyun 
1100*4882a593Smuzhiyun 	err = kstrtol(buf, 10, &val);
1101*4882a593Smuzhiyun 	if (err)
1102*4882a593Smuzhiyun 		return err;
1103*4882a593Smuzhiyun 
1104*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	data->beep_enable = val ? 1 : 0;
1107*4882a593Smuzhiyun 
1108*4882a593Smuzhiyun 	/* Keep the full mask value in sync with the current enable */
1109*4882a593Smuzhiyun 	data->beep_mask &= ~GLOBAL_BEEP_ENABLE_MASK;
1110*4882a593Smuzhiyun 	data->beep_mask |= (data->beep_enable << GLOBAL_BEEP_ENABLE_SHIFT);
1111*4882a593Smuzhiyun 
1112*4882a593Smuzhiyun 	/*
1113*4882a593Smuzhiyun 	 * The global control is in the second beep control register
1114*4882a593Smuzhiyun 	 * so only need to update that register
1115*4882a593Smuzhiyun 	 */
1116*4882a593Smuzhiyun 	val = (data->beep_mask >> 8) & 0xff;
1117*4882a593Smuzhiyun 
1118*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_BEEP_CTRL[1], val);
1119*4882a593Smuzhiyun 
1120*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
1121*4882a593Smuzhiyun 
1122*4882a593Smuzhiyun 	return count;
1123*4882a593Smuzhiyun }
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun static struct sensor_device_attribute sda_beep_ctrl[] = {
1126*4882a593Smuzhiyun 	SENSOR_ATTR(beep_enable, S_IRUGO | S_IWUSR,
1127*4882a593Smuzhiyun 			show_beep_enable, store_beep_enable, 0),
1128*4882a593Smuzhiyun 	SENSOR_ATTR(beep_mask, S_IRUGO | S_IWUSR,
1129*4882a593Smuzhiyun 			show_beep_mask, store_beep_mask, 1)
1130*4882a593Smuzhiyun };
1131*4882a593Smuzhiyun 
1132*4882a593Smuzhiyun /* cpu voltage regulation information */
cpu0_vid_show(struct device * dev,struct device_attribute * attr,char * buf)1133*4882a593Smuzhiyun static ssize_t cpu0_vid_show(struct device *dev,
1134*4882a593Smuzhiyun 			     struct device_attribute *attr, char *buf)
1135*4882a593Smuzhiyun {
1136*4882a593Smuzhiyun 	struct w83791d_data *data = w83791d_update_device(dev);
1137*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
1138*4882a593Smuzhiyun }
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun static DEVICE_ATTR_RO(cpu0_vid);
1141*4882a593Smuzhiyun 
vrm_show(struct device * dev,struct device_attribute * attr,char * buf)1142*4882a593Smuzhiyun static ssize_t vrm_show(struct device *dev, struct device_attribute *attr,
1143*4882a593Smuzhiyun 			char *buf)
1144*4882a593Smuzhiyun {
1145*4882a593Smuzhiyun 	struct w83791d_data *data = dev_get_drvdata(dev);
1146*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", data->vrm);
1147*4882a593Smuzhiyun }
1148*4882a593Smuzhiyun 
vrm_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1149*4882a593Smuzhiyun static ssize_t vrm_store(struct device *dev, struct device_attribute *attr,
1150*4882a593Smuzhiyun 			 const char *buf, size_t count)
1151*4882a593Smuzhiyun {
1152*4882a593Smuzhiyun 	struct w83791d_data *data = dev_get_drvdata(dev);
1153*4882a593Smuzhiyun 	unsigned long val;
1154*4882a593Smuzhiyun 	int err;
1155*4882a593Smuzhiyun 
1156*4882a593Smuzhiyun 	/*
1157*4882a593Smuzhiyun 	 * No lock needed as vrm is internal to the driver
1158*4882a593Smuzhiyun 	 * (not read from a chip register) and so is not
1159*4882a593Smuzhiyun 	 * updated in w83791d_update_device()
1160*4882a593Smuzhiyun 	 */
1161*4882a593Smuzhiyun 
1162*4882a593Smuzhiyun 	err = kstrtoul(buf, 10, &val);
1163*4882a593Smuzhiyun 	if (err)
1164*4882a593Smuzhiyun 		return err;
1165*4882a593Smuzhiyun 
1166*4882a593Smuzhiyun 	if (val > 255)
1167*4882a593Smuzhiyun 		return -EINVAL;
1168*4882a593Smuzhiyun 
1169*4882a593Smuzhiyun 	data->vrm = val;
1170*4882a593Smuzhiyun 	return count;
1171*4882a593Smuzhiyun }
1172*4882a593Smuzhiyun 
1173*4882a593Smuzhiyun static DEVICE_ATTR_RW(vrm);
1174*4882a593Smuzhiyun 
1175*4882a593Smuzhiyun #define IN_UNIT_ATTRS(X) \
1176*4882a593Smuzhiyun 	&sda_in_input[X].dev_attr.attr,	\
1177*4882a593Smuzhiyun 	&sda_in_min[X].dev_attr.attr,	\
1178*4882a593Smuzhiyun 	&sda_in_max[X].dev_attr.attr,	\
1179*4882a593Smuzhiyun 	&sda_in_beep[X].dev_attr.attr,	\
1180*4882a593Smuzhiyun 	&sda_in_alarm[X].dev_attr.attr
1181*4882a593Smuzhiyun 
1182*4882a593Smuzhiyun #define FAN_UNIT_ATTRS(X) \
1183*4882a593Smuzhiyun 	&sda_fan_input[X].dev_attr.attr,	\
1184*4882a593Smuzhiyun 	&sda_fan_min[X].dev_attr.attr,		\
1185*4882a593Smuzhiyun 	&sda_fan_div[X].dev_attr.attr,		\
1186*4882a593Smuzhiyun 	&sda_fan_beep[X].dev_attr.attr,		\
1187*4882a593Smuzhiyun 	&sda_fan_alarm[X].dev_attr.attr
1188*4882a593Smuzhiyun 
1189*4882a593Smuzhiyun #define TEMP_UNIT_ATTRS(X) \
1190*4882a593Smuzhiyun 	&sda_temp_input[X].dev_attr.attr,	\
1191*4882a593Smuzhiyun 	&sda_temp_max[X].dev_attr.attr,		\
1192*4882a593Smuzhiyun 	&sda_temp_max_hyst[X].dev_attr.attr,	\
1193*4882a593Smuzhiyun 	&sda_temp_beep[X].dev_attr.attr,	\
1194*4882a593Smuzhiyun 	&sda_temp_alarm[X].dev_attr.attr
1195*4882a593Smuzhiyun 
1196*4882a593Smuzhiyun static struct attribute *w83791d_attributes[] = {
1197*4882a593Smuzhiyun 	IN_UNIT_ATTRS(0),
1198*4882a593Smuzhiyun 	IN_UNIT_ATTRS(1),
1199*4882a593Smuzhiyun 	IN_UNIT_ATTRS(2),
1200*4882a593Smuzhiyun 	IN_UNIT_ATTRS(3),
1201*4882a593Smuzhiyun 	IN_UNIT_ATTRS(4),
1202*4882a593Smuzhiyun 	IN_UNIT_ATTRS(5),
1203*4882a593Smuzhiyun 	IN_UNIT_ATTRS(6),
1204*4882a593Smuzhiyun 	IN_UNIT_ATTRS(7),
1205*4882a593Smuzhiyun 	IN_UNIT_ATTRS(8),
1206*4882a593Smuzhiyun 	IN_UNIT_ATTRS(9),
1207*4882a593Smuzhiyun 	FAN_UNIT_ATTRS(0),
1208*4882a593Smuzhiyun 	FAN_UNIT_ATTRS(1),
1209*4882a593Smuzhiyun 	FAN_UNIT_ATTRS(2),
1210*4882a593Smuzhiyun 	TEMP_UNIT_ATTRS(0),
1211*4882a593Smuzhiyun 	TEMP_UNIT_ATTRS(1),
1212*4882a593Smuzhiyun 	TEMP_UNIT_ATTRS(2),
1213*4882a593Smuzhiyun 	&dev_attr_alarms.attr,
1214*4882a593Smuzhiyun 	&sda_beep_ctrl[0].dev_attr.attr,
1215*4882a593Smuzhiyun 	&sda_beep_ctrl[1].dev_attr.attr,
1216*4882a593Smuzhiyun 	&dev_attr_cpu0_vid.attr,
1217*4882a593Smuzhiyun 	&dev_attr_vrm.attr,
1218*4882a593Smuzhiyun 	&sda_pwm[0].dev_attr.attr,
1219*4882a593Smuzhiyun 	&sda_pwm[1].dev_attr.attr,
1220*4882a593Smuzhiyun 	&sda_pwm[2].dev_attr.attr,
1221*4882a593Smuzhiyun 	&sda_pwmenable[0].dev_attr.attr,
1222*4882a593Smuzhiyun 	&sda_pwmenable[1].dev_attr.attr,
1223*4882a593Smuzhiyun 	&sda_pwmenable[2].dev_attr.attr,
1224*4882a593Smuzhiyun 	&sda_temp_target[0].dev_attr.attr,
1225*4882a593Smuzhiyun 	&sda_temp_target[1].dev_attr.attr,
1226*4882a593Smuzhiyun 	&sda_temp_target[2].dev_attr.attr,
1227*4882a593Smuzhiyun 	&sda_temp_tolerance[0].dev_attr.attr,
1228*4882a593Smuzhiyun 	&sda_temp_tolerance[1].dev_attr.attr,
1229*4882a593Smuzhiyun 	&sda_temp_tolerance[2].dev_attr.attr,
1230*4882a593Smuzhiyun 	NULL
1231*4882a593Smuzhiyun };
1232*4882a593Smuzhiyun 
1233*4882a593Smuzhiyun static const struct attribute_group w83791d_group = {
1234*4882a593Smuzhiyun 	.attrs = w83791d_attributes,
1235*4882a593Smuzhiyun };
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun /*
1238*4882a593Smuzhiyun  * Separate group of attributes for fan/pwm 4-5. Their pins can also be
1239*4882a593Smuzhiyun  * in use for GPIO in which case their sysfs-interface should not be made
1240*4882a593Smuzhiyun  * available
1241*4882a593Smuzhiyun  */
1242*4882a593Smuzhiyun static struct attribute *w83791d_attributes_fanpwm45[] = {
1243*4882a593Smuzhiyun 	FAN_UNIT_ATTRS(3),
1244*4882a593Smuzhiyun 	FAN_UNIT_ATTRS(4),
1245*4882a593Smuzhiyun 	&sda_pwm[3].dev_attr.attr,
1246*4882a593Smuzhiyun 	&sda_pwm[4].dev_attr.attr,
1247*4882a593Smuzhiyun 	NULL
1248*4882a593Smuzhiyun };
1249*4882a593Smuzhiyun 
1250*4882a593Smuzhiyun static const struct attribute_group w83791d_group_fanpwm45 = {
1251*4882a593Smuzhiyun 	.attrs = w83791d_attributes_fanpwm45,
1252*4882a593Smuzhiyun };
1253*4882a593Smuzhiyun 
w83791d_detect_subclients(struct i2c_client * client)1254*4882a593Smuzhiyun static int w83791d_detect_subclients(struct i2c_client *client)
1255*4882a593Smuzhiyun {
1256*4882a593Smuzhiyun 	struct i2c_adapter *adapter = client->adapter;
1257*4882a593Smuzhiyun 	int address = client->addr;
1258*4882a593Smuzhiyun 	int i, id;
1259*4882a593Smuzhiyun 	u8 val;
1260*4882a593Smuzhiyun 
1261*4882a593Smuzhiyun 	id = i2c_adapter_id(adapter);
1262*4882a593Smuzhiyun 	if (force_subclients[0] == id && force_subclients[1] == address) {
1263*4882a593Smuzhiyun 		for (i = 2; i <= 3; i++) {
1264*4882a593Smuzhiyun 			if (force_subclients[i] < 0x48 ||
1265*4882a593Smuzhiyun 			    force_subclients[i] > 0x4f) {
1266*4882a593Smuzhiyun 				dev_err(&client->dev,
1267*4882a593Smuzhiyun 					"invalid subclient "
1268*4882a593Smuzhiyun 					"address %d; must be 0x48-0x4f\n",
1269*4882a593Smuzhiyun 					force_subclients[i]);
1270*4882a593Smuzhiyun 				return -ENODEV;
1271*4882a593Smuzhiyun 			}
1272*4882a593Smuzhiyun 		}
1273*4882a593Smuzhiyun 		w83791d_write(client, W83791D_REG_I2C_SUBADDR,
1274*4882a593Smuzhiyun 					(force_subclients[2] & 0x07) |
1275*4882a593Smuzhiyun 					((force_subclients[3] & 0x07) << 4));
1276*4882a593Smuzhiyun 	}
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 	val = w83791d_read(client, W83791D_REG_I2C_SUBADDR);
1279*4882a593Smuzhiyun 
1280*4882a593Smuzhiyun 	if (!(val & 0x88) && (val & 0x7) == ((val >> 4) & 0x7)) {
1281*4882a593Smuzhiyun 		dev_err(&client->dev,
1282*4882a593Smuzhiyun 			"duplicate addresses 0x%x, use force_subclient\n", 0x48 + (val & 0x7));
1283*4882a593Smuzhiyun 		return -ENODEV;
1284*4882a593Smuzhiyun 	}
1285*4882a593Smuzhiyun 
1286*4882a593Smuzhiyun 	if (!(val & 0x08))
1287*4882a593Smuzhiyun 		devm_i2c_new_dummy_device(&client->dev, adapter, 0x48 + (val & 0x7));
1288*4882a593Smuzhiyun 
1289*4882a593Smuzhiyun 	if (!(val & 0x80))
1290*4882a593Smuzhiyun 		devm_i2c_new_dummy_device(&client->dev, adapter, 0x48 + ((val >> 4) & 0x7));
1291*4882a593Smuzhiyun 
1292*4882a593Smuzhiyun 	return 0;
1293*4882a593Smuzhiyun }
1294*4882a593Smuzhiyun 
1295*4882a593Smuzhiyun 
1296*4882a593Smuzhiyun /* Return 0 if detection is successful, -ENODEV otherwise */
w83791d_detect(struct i2c_client * client,struct i2c_board_info * info)1297*4882a593Smuzhiyun static int w83791d_detect(struct i2c_client *client,
1298*4882a593Smuzhiyun 			  struct i2c_board_info *info)
1299*4882a593Smuzhiyun {
1300*4882a593Smuzhiyun 	struct i2c_adapter *adapter = client->adapter;
1301*4882a593Smuzhiyun 	int val1, val2;
1302*4882a593Smuzhiyun 	unsigned short address = client->addr;
1303*4882a593Smuzhiyun 
1304*4882a593Smuzhiyun 	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1305*4882a593Smuzhiyun 		return -ENODEV;
1306*4882a593Smuzhiyun 
1307*4882a593Smuzhiyun 	if (w83791d_read(client, W83791D_REG_CONFIG) & 0x80)
1308*4882a593Smuzhiyun 		return -ENODEV;
1309*4882a593Smuzhiyun 
1310*4882a593Smuzhiyun 	val1 = w83791d_read(client, W83791D_REG_BANK);
1311*4882a593Smuzhiyun 	val2 = w83791d_read(client, W83791D_REG_CHIPMAN);
1312*4882a593Smuzhiyun 	/* Check for Winbond ID if in bank 0 */
1313*4882a593Smuzhiyun 	if (!(val1 & 0x07)) {
1314*4882a593Smuzhiyun 		if ((!(val1 & 0x80) && val2 != 0xa3) ||
1315*4882a593Smuzhiyun 		    ((val1 & 0x80) && val2 != 0x5c)) {
1316*4882a593Smuzhiyun 			return -ENODEV;
1317*4882a593Smuzhiyun 		}
1318*4882a593Smuzhiyun 	}
1319*4882a593Smuzhiyun 	/*
1320*4882a593Smuzhiyun 	 * If Winbond chip, address of chip and W83791D_REG_I2C_ADDR
1321*4882a593Smuzhiyun 	 * should match
1322*4882a593Smuzhiyun 	 */
1323*4882a593Smuzhiyun 	if (w83791d_read(client, W83791D_REG_I2C_ADDR) != address)
1324*4882a593Smuzhiyun 		return -ENODEV;
1325*4882a593Smuzhiyun 
1326*4882a593Smuzhiyun 	/* We want bank 0 and Vendor ID high byte */
1327*4882a593Smuzhiyun 	val1 = w83791d_read(client, W83791D_REG_BANK) & 0x78;
1328*4882a593Smuzhiyun 	w83791d_write(client, W83791D_REG_BANK, val1 | 0x80);
1329*4882a593Smuzhiyun 
1330*4882a593Smuzhiyun 	/* Verify it is a Winbond w83791d */
1331*4882a593Smuzhiyun 	val1 = w83791d_read(client, W83791D_REG_WCHIPID);
1332*4882a593Smuzhiyun 	val2 = w83791d_read(client, W83791D_REG_CHIPMAN);
1333*4882a593Smuzhiyun 	if (val1 != 0x71 || val2 != 0x5c)
1334*4882a593Smuzhiyun 		return -ENODEV;
1335*4882a593Smuzhiyun 
1336*4882a593Smuzhiyun 	strlcpy(info->type, "w83791d", I2C_NAME_SIZE);
1337*4882a593Smuzhiyun 
1338*4882a593Smuzhiyun 	return 0;
1339*4882a593Smuzhiyun }
1340*4882a593Smuzhiyun 
w83791d_probe(struct i2c_client * client)1341*4882a593Smuzhiyun static int w83791d_probe(struct i2c_client *client)
1342*4882a593Smuzhiyun {
1343*4882a593Smuzhiyun 	struct w83791d_data *data;
1344*4882a593Smuzhiyun 	struct device *dev = &client->dev;
1345*4882a593Smuzhiyun 	int i, err;
1346*4882a593Smuzhiyun 	u8 has_fanpwm45;
1347*4882a593Smuzhiyun 
1348*4882a593Smuzhiyun #ifdef DEBUG
1349*4882a593Smuzhiyun 	int val1;
1350*4882a593Smuzhiyun 	val1 = w83791d_read(client, W83791D_REG_DID_VID4);
1351*4882a593Smuzhiyun 	dev_dbg(dev, "Device ID version: %d.%d (0x%02x)\n",
1352*4882a593Smuzhiyun 			(val1 >> 5) & 0x07, (val1 >> 1) & 0x0f, val1);
1353*4882a593Smuzhiyun #endif
1354*4882a593Smuzhiyun 
1355*4882a593Smuzhiyun 	data = devm_kzalloc(&client->dev, sizeof(struct w83791d_data),
1356*4882a593Smuzhiyun 			    GFP_KERNEL);
1357*4882a593Smuzhiyun 	if (!data)
1358*4882a593Smuzhiyun 		return -ENOMEM;
1359*4882a593Smuzhiyun 
1360*4882a593Smuzhiyun 	i2c_set_clientdata(client, data);
1361*4882a593Smuzhiyun 	mutex_init(&data->update_lock);
1362*4882a593Smuzhiyun 
1363*4882a593Smuzhiyun 	err = w83791d_detect_subclients(client);
1364*4882a593Smuzhiyun 	if (err)
1365*4882a593Smuzhiyun 		return err;
1366*4882a593Smuzhiyun 
1367*4882a593Smuzhiyun 	/* Initialize the chip */
1368*4882a593Smuzhiyun 	w83791d_init_client(client);
1369*4882a593Smuzhiyun 
1370*4882a593Smuzhiyun 	/*
1371*4882a593Smuzhiyun 	 * If the fan_div is changed, make sure there is a rational
1372*4882a593Smuzhiyun 	 * fan_min in place
1373*4882a593Smuzhiyun 	 */
1374*4882a593Smuzhiyun 	for (i = 0; i < NUMBER_OF_FANIN; i++)
1375*4882a593Smuzhiyun 		data->fan_min[i] = w83791d_read(client, W83791D_REG_FAN_MIN[i]);
1376*4882a593Smuzhiyun 
1377*4882a593Smuzhiyun 	/* Register sysfs hooks */
1378*4882a593Smuzhiyun 	err = sysfs_create_group(&client->dev.kobj, &w83791d_group);
1379*4882a593Smuzhiyun 	if (err)
1380*4882a593Smuzhiyun 		return err;
1381*4882a593Smuzhiyun 
1382*4882a593Smuzhiyun 	/* Check if pins of fan/pwm 4-5 are in use as GPIO */
1383*4882a593Smuzhiyun 	has_fanpwm45 = w83791d_read(client, W83791D_REG_GPIO) & 0x10;
1384*4882a593Smuzhiyun 	if (has_fanpwm45) {
1385*4882a593Smuzhiyun 		err = sysfs_create_group(&client->dev.kobj,
1386*4882a593Smuzhiyun 					 &w83791d_group_fanpwm45);
1387*4882a593Smuzhiyun 		if (err)
1388*4882a593Smuzhiyun 			goto error4;
1389*4882a593Smuzhiyun 	}
1390*4882a593Smuzhiyun 
1391*4882a593Smuzhiyun 	/* Everything is ready, now register the working device */
1392*4882a593Smuzhiyun 	data->hwmon_dev = hwmon_device_register(dev);
1393*4882a593Smuzhiyun 	if (IS_ERR(data->hwmon_dev)) {
1394*4882a593Smuzhiyun 		err = PTR_ERR(data->hwmon_dev);
1395*4882a593Smuzhiyun 		goto error5;
1396*4882a593Smuzhiyun 	}
1397*4882a593Smuzhiyun 
1398*4882a593Smuzhiyun 	return 0;
1399*4882a593Smuzhiyun 
1400*4882a593Smuzhiyun error5:
1401*4882a593Smuzhiyun 	if (has_fanpwm45)
1402*4882a593Smuzhiyun 		sysfs_remove_group(&client->dev.kobj, &w83791d_group_fanpwm45);
1403*4882a593Smuzhiyun error4:
1404*4882a593Smuzhiyun 	sysfs_remove_group(&client->dev.kobj, &w83791d_group);
1405*4882a593Smuzhiyun 	return err;
1406*4882a593Smuzhiyun }
1407*4882a593Smuzhiyun 
w83791d_remove(struct i2c_client * client)1408*4882a593Smuzhiyun static int w83791d_remove(struct i2c_client *client)
1409*4882a593Smuzhiyun {
1410*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
1411*4882a593Smuzhiyun 
1412*4882a593Smuzhiyun 	hwmon_device_unregister(data->hwmon_dev);
1413*4882a593Smuzhiyun 	sysfs_remove_group(&client->dev.kobj, &w83791d_group);
1414*4882a593Smuzhiyun 
1415*4882a593Smuzhiyun 	return 0;
1416*4882a593Smuzhiyun }
1417*4882a593Smuzhiyun 
w83791d_init_client(struct i2c_client * client)1418*4882a593Smuzhiyun static void w83791d_init_client(struct i2c_client *client)
1419*4882a593Smuzhiyun {
1420*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
1421*4882a593Smuzhiyun 	u8 tmp;
1422*4882a593Smuzhiyun 	u8 old_beep;
1423*4882a593Smuzhiyun 
1424*4882a593Smuzhiyun 	/*
1425*4882a593Smuzhiyun 	 * The difference between reset and init is that reset
1426*4882a593Smuzhiyun 	 * does a hard reset of the chip via index 0x40, bit 7,
1427*4882a593Smuzhiyun 	 * but init simply forces certain registers to have "sane"
1428*4882a593Smuzhiyun 	 * values. The hope is that the BIOS has done the right
1429*4882a593Smuzhiyun 	 * thing (which is why the default is reset=0, init=0),
1430*4882a593Smuzhiyun 	 * but if not, reset is the hard hammer and init
1431*4882a593Smuzhiyun 	 * is the soft mallet both of which are trying to whack
1432*4882a593Smuzhiyun 	 * things into place...
1433*4882a593Smuzhiyun 	 * NOTE: The data sheet makes a distinction between
1434*4882a593Smuzhiyun 	 * "power on defaults" and "reset by MR". As far as I can tell,
1435*4882a593Smuzhiyun 	 * the hard reset puts everything into a power-on state so I'm
1436*4882a593Smuzhiyun 	 * not sure what "reset by MR" means or how it can happen.
1437*4882a593Smuzhiyun 	 */
1438*4882a593Smuzhiyun 	if (reset || init) {
1439*4882a593Smuzhiyun 		/* keep some BIOS settings when we... */
1440*4882a593Smuzhiyun 		old_beep = w83791d_read(client, W83791D_REG_BEEP_CONFIG);
1441*4882a593Smuzhiyun 
1442*4882a593Smuzhiyun 		if (reset) {
1443*4882a593Smuzhiyun 			/* ... reset the chip and ... */
1444*4882a593Smuzhiyun 			w83791d_write(client, W83791D_REG_CONFIG, 0x80);
1445*4882a593Smuzhiyun 		}
1446*4882a593Smuzhiyun 
1447*4882a593Smuzhiyun 		/* ... disable power-on abnormal beep */
1448*4882a593Smuzhiyun 		w83791d_write(client, W83791D_REG_BEEP_CONFIG, old_beep | 0x80);
1449*4882a593Smuzhiyun 
1450*4882a593Smuzhiyun 		/* disable the global beep (not done by hard reset) */
1451*4882a593Smuzhiyun 		tmp = w83791d_read(client, W83791D_REG_BEEP_CTRL[1]);
1452*4882a593Smuzhiyun 		w83791d_write(client, W83791D_REG_BEEP_CTRL[1], tmp & 0xef);
1453*4882a593Smuzhiyun 
1454*4882a593Smuzhiyun 		if (init) {
1455*4882a593Smuzhiyun 			/* Make sure monitoring is turned on for add-ons */
1456*4882a593Smuzhiyun 			tmp = w83791d_read(client, W83791D_REG_TEMP2_CONFIG);
1457*4882a593Smuzhiyun 			if (tmp & 1) {
1458*4882a593Smuzhiyun 				w83791d_write(client, W83791D_REG_TEMP2_CONFIG,
1459*4882a593Smuzhiyun 					tmp & 0xfe);
1460*4882a593Smuzhiyun 			}
1461*4882a593Smuzhiyun 
1462*4882a593Smuzhiyun 			tmp = w83791d_read(client, W83791D_REG_TEMP3_CONFIG);
1463*4882a593Smuzhiyun 			if (tmp & 1) {
1464*4882a593Smuzhiyun 				w83791d_write(client, W83791D_REG_TEMP3_CONFIG,
1465*4882a593Smuzhiyun 					tmp & 0xfe);
1466*4882a593Smuzhiyun 			}
1467*4882a593Smuzhiyun 
1468*4882a593Smuzhiyun 			/* Start monitoring */
1469*4882a593Smuzhiyun 			tmp = w83791d_read(client, W83791D_REG_CONFIG) & 0xf7;
1470*4882a593Smuzhiyun 			w83791d_write(client, W83791D_REG_CONFIG, tmp | 0x01);
1471*4882a593Smuzhiyun 		}
1472*4882a593Smuzhiyun 	}
1473*4882a593Smuzhiyun 
1474*4882a593Smuzhiyun 	data->vrm = vid_which_vrm();
1475*4882a593Smuzhiyun }
1476*4882a593Smuzhiyun 
w83791d_update_device(struct device * dev)1477*4882a593Smuzhiyun static struct w83791d_data *w83791d_update_device(struct device *dev)
1478*4882a593Smuzhiyun {
1479*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
1480*4882a593Smuzhiyun 	struct w83791d_data *data = i2c_get_clientdata(client);
1481*4882a593Smuzhiyun 	int i, j;
1482*4882a593Smuzhiyun 	u8 reg_array_tmp[3];
1483*4882a593Smuzhiyun 	u8 vbat_reg;
1484*4882a593Smuzhiyun 
1485*4882a593Smuzhiyun 	mutex_lock(&data->update_lock);
1486*4882a593Smuzhiyun 
1487*4882a593Smuzhiyun 	if (time_after(jiffies, data->last_updated + (HZ * 3))
1488*4882a593Smuzhiyun 			|| !data->valid) {
1489*4882a593Smuzhiyun 		dev_dbg(dev, "Starting w83791d device update\n");
1490*4882a593Smuzhiyun 
1491*4882a593Smuzhiyun 		/* Update the voltages measured value and limits */
1492*4882a593Smuzhiyun 		for (i = 0; i < NUMBER_OF_VIN; i++) {
1493*4882a593Smuzhiyun 			data->in[i] = w83791d_read(client,
1494*4882a593Smuzhiyun 						W83791D_REG_IN[i]);
1495*4882a593Smuzhiyun 			data->in_max[i] = w83791d_read(client,
1496*4882a593Smuzhiyun 						W83791D_REG_IN_MAX[i]);
1497*4882a593Smuzhiyun 			data->in_min[i] = w83791d_read(client,
1498*4882a593Smuzhiyun 						W83791D_REG_IN_MIN[i]);
1499*4882a593Smuzhiyun 		}
1500*4882a593Smuzhiyun 
1501*4882a593Smuzhiyun 		/* Update the fan counts and limits */
1502*4882a593Smuzhiyun 		for (i = 0; i < NUMBER_OF_FANIN; i++) {
1503*4882a593Smuzhiyun 			/* Update the Fan measured value and limits */
1504*4882a593Smuzhiyun 			data->fan[i] = w83791d_read(client,
1505*4882a593Smuzhiyun 						W83791D_REG_FAN[i]);
1506*4882a593Smuzhiyun 			data->fan_min[i] = w83791d_read(client,
1507*4882a593Smuzhiyun 						W83791D_REG_FAN_MIN[i]);
1508*4882a593Smuzhiyun 		}
1509*4882a593Smuzhiyun 
1510*4882a593Smuzhiyun 		/* Update the fan divisor */
1511*4882a593Smuzhiyun 		for (i = 0; i < 3; i++) {
1512*4882a593Smuzhiyun 			reg_array_tmp[i] = w83791d_read(client,
1513*4882a593Smuzhiyun 						W83791D_REG_FAN_DIV[i]);
1514*4882a593Smuzhiyun 		}
1515*4882a593Smuzhiyun 		data->fan_div[0] = (reg_array_tmp[0] >> 4) & 0x03;
1516*4882a593Smuzhiyun 		data->fan_div[1] = (reg_array_tmp[0] >> 6) & 0x03;
1517*4882a593Smuzhiyun 		data->fan_div[2] = (reg_array_tmp[1] >> 6) & 0x03;
1518*4882a593Smuzhiyun 		data->fan_div[3] = reg_array_tmp[2] & 0x07;
1519*4882a593Smuzhiyun 		data->fan_div[4] = (reg_array_tmp[2] >> 4) & 0x07;
1520*4882a593Smuzhiyun 
1521*4882a593Smuzhiyun 		/*
1522*4882a593Smuzhiyun 		 * The fan divisor for fans 0-2 get bit 2 from
1523*4882a593Smuzhiyun 		 * bits 5-7 respectively of vbat register
1524*4882a593Smuzhiyun 		 */
1525*4882a593Smuzhiyun 		vbat_reg = w83791d_read(client, W83791D_REG_VBAT);
1526*4882a593Smuzhiyun 		for (i = 0; i < 3; i++)
1527*4882a593Smuzhiyun 			data->fan_div[i] |= (vbat_reg >> (3 + i)) & 0x04;
1528*4882a593Smuzhiyun 
1529*4882a593Smuzhiyun 		/* Update PWM duty cycle */
1530*4882a593Smuzhiyun 		for (i = 0; i < NUMBER_OF_PWM; i++) {
1531*4882a593Smuzhiyun 			data->pwm[i] =  w83791d_read(client,
1532*4882a593Smuzhiyun 						W83791D_REG_PWM[i]);
1533*4882a593Smuzhiyun 		}
1534*4882a593Smuzhiyun 
1535*4882a593Smuzhiyun 		/* Update PWM enable status */
1536*4882a593Smuzhiyun 		for (i = 0; i < 2; i++) {
1537*4882a593Smuzhiyun 			reg_array_tmp[i] = w83791d_read(client,
1538*4882a593Smuzhiyun 						W83791D_REG_FAN_CFG[i]);
1539*4882a593Smuzhiyun 		}
1540*4882a593Smuzhiyun 		data->pwm_enable[0] = (reg_array_tmp[0] >> 2) & 0x03;
1541*4882a593Smuzhiyun 		data->pwm_enable[1] = (reg_array_tmp[0] >> 4) & 0x03;
1542*4882a593Smuzhiyun 		data->pwm_enable[2] = (reg_array_tmp[1] >> 2) & 0x03;
1543*4882a593Smuzhiyun 
1544*4882a593Smuzhiyun 		/* Update PWM target temperature */
1545*4882a593Smuzhiyun 		for (i = 0; i < 3; i++) {
1546*4882a593Smuzhiyun 			data->temp_target[i] = w83791d_read(client,
1547*4882a593Smuzhiyun 				W83791D_REG_TEMP_TARGET[i]) & 0x7f;
1548*4882a593Smuzhiyun 		}
1549*4882a593Smuzhiyun 
1550*4882a593Smuzhiyun 		/* Update PWM temperature tolerance */
1551*4882a593Smuzhiyun 		for (i = 0; i < 2; i++) {
1552*4882a593Smuzhiyun 			reg_array_tmp[i] = w83791d_read(client,
1553*4882a593Smuzhiyun 					W83791D_REG_TEMP_TOL[i]);
1554*4882a593Smuzhiyun 		}
1555*4882a593Smuzhiyun 		data->temp_tolerance[0] = reg_array_tmp[0] & 0x0f;
1556*4882a593Smuzhiyun 		data->temp_tolerance[1] = (reg_array_tmp[0] >> 4) & 0x0f;
1557*4882a593Smuzhiyun 		data->temp_tolerance[2] = reg_array_tmp[1] & 0x0f;
1558*4882a593Smuzhiyun 
1559*4882a593Smuzhiyun 		/* Update the first temperature sensor */
1560*4882a593Smuzhiyun 		for (i = 0; i < 3; i++) {
1561*4882a593Smuzhiyun 			data->temp1[i] = w83791d_read(client,
1562*4882a593Smuzhiyun 						W83791D_REG_TEMP1[i]);
1563*4882a593Smuzhiyun 		}
1564*4882a593Smuzhiyun 
1565*4882a593Smuzhiyun 		/* Update the rest of the temperature sensors */
1566*4882a593Smuzhiyun 		for (i = 0; i < 2; i++) {
1567*4882a593Smuzhiyun 			for (j = 0; j < 3; j++) {
1568*4882a593Smuzhiyun 				data->temp_add[i][j] =
1569*4882a593Smuzhiyun 					(w83791d_read(client,
1570*4882a593Smuzhiyun 					W83791D_REG_TEMP_ADD[i][j * 2]) << 8) |
1571*4882a593Smuzhiyun 					w83791d_read(client,
1572*4882a593Smuzhiyun 					W83791D_REG_TEMP_ADD[i][j * 2 + 1]);
1573*4882a593Smuzhiyun 			}
1574*4882a593Smuzhiyun 		}
1575*4882a593Smuzhiyun 
1576*4882a593Smuzhiyun 		/* Update the realtime status */
1577*4882a593Smuzhiyun 		data->alarms =
1578*4882a593Smuzhiyun 			w83791d_read(client, W83791D_REG_ALARM1) +
1579*4882a593Smuzhiyun 			(w83791d_read(client, W83791D_REG_ALARM2) << 8) +
1580*4882a593Smuzhiyun 			(w83791d_read(client, W83791D_REG_ALARM3) << 16);
1581*4882a593Smuzhiyun 
1582*4882a593Smuzhiyun 		/* Update the beep configuration information */
1583*4882a593Smuzhiyun 		data->beep_mask =
1584*4882a593Smuzhiyun 			w83791d_read(client, W83791D_REG_BEEP_CTRL[0]) +
1585*4882a593Smuzhiyun 			(w83791d_read(client, W83791D_REG_BEEP_CTRL[1]) << 8) +
1586*4882a593Smuzhiyun 			(w83791d_read(client, W83791D_REG_BEEP_CTRL[2]) << 16);
1587*4882a593Smuzhiyun 
1588*4882a593Smuzhiyun 		/* Extract global beep enable flag */
1589*4882a593Smuzhiyun 		data->beep_enable =
1590*4882a593Smuzhiyun 			(data->beep_mask >> GLOBAL_BEEP_ENABLE_SHIFT) & 0x01;
1591*4882a593Smuzhiyun 
1592*4882a593Smuzhiyun 		/* Update the cpu voltage information */
1593*4882a593Smuzhiyun 		i = w83791d_read(client, W83791D_REG_VID_FANDIV);
1594*4882a593Smuzhiyun 		data->vid = i & 0x0f;
1595*4882a593Smuzhiyun 		data->vid |= (w83791d_read(client, W83791D_REG_DID_VID4) & 0x01)
1596*4882a593Smuzhiyun 				<< 4;
1597*4882a593Smuzhiyun 
1598*4882a593Smuzhiyun 		data->last_updated = jiffies;
1599*4882a593Smuzhiyun 		data->valid = 1;
1600*4882a593Smuzhiyun 	}
1601*4882a593Smuzhiyun 
1602*4882a593Smuzhiyun 	mutex_unlock(&data->update_lock);
1603*4882a593Smuzhiyun 
1604*4882a593Smuzhiyun #ifdef DEBUG
1605*4882a593Smuzhiyun 	w83791d_print_debug(data, dev);
1606*4882a593Smuzhiyun #endif
1607*4882a593Smuzhiyun 
1608*4882a593Smuzhiyun 	return data;
1609*4882a593Smuzhiyun }
1610*4882a593Smuzhiyun 
1611*4882a593Smuzhiyun #ifdef DEBUG
w83791d_print_debug(struct w83791d_data * data,struct device * dev)1612*4882a593Smuzhiyun static void w83791d_print_debug(struct w83791d_data *data, struct device *dev)
1613*4882a593Smuzhiyun {
1614*4882a593Smuzhiyun 	int i = 0, j = 0;
1615*4882a593Smuzhiyun 
1616*4882a593Smuzhiyun 	dev_dbg(dev, "======Start of w83791d debug values======\n");
1617*4882a593Smuzhiyun 	dev_dbg(dev, "%d set of Voltages: ===>\n", NUMBER_OF_VIN);
1618*4882a593Smuzhiyun 	for (i = 0; i < NUMBER_OF_VIN; i++) {
1619*4882a593Smuzhiyun 		dev_dbg(dev, "vin[%d] is:     0x%02x\n", i, data->in[i]);
1620*4882a593Smuzhiyun 		dev_dbg(dev, "vin[%d] min is: 0x%02x\n", i, data->in_min[i]);
1621*4882a593Smuzhiyun 		dev_dbg(dev, "vin[%d] max is: 0x%02x\n", i, data->in_max[i]);
1622*4882a593Smuzhiyun 	}
1623*4882a593Smuzhiyun 	dev_dbg(dev, "%d set of Fan Counts/Divisors: ===>\n", NUMBER_OF_FANIN);
1624*4882a593Smuzhiyun 	for (i = 0; i < NUMBER_OF_FANIN; i++) {
1625*4882a593Smuzhiyun 		dev_dbg(dev, "fan[%d] is:     0x%02x\n", i, data->fan[i]);
1626*4882a593Smuzhiyun 		dev_dbg(dev, "fan[%d] min is: 0x%02x\n", i, data->fan_min[i]);
1627*4882a593Smuzhiyun 		dev_dbg(dev, "fan_div[%d] is: 0x%02x\n", i, data->fan_div[i]);
1628*4882a593Smuzhiyun 	}
1629*4882a593Smuzhiyun 
1630*4882a593Smuzhiyun 	/*
1631*4882a593Smuzhiyun 	 * temperature math is signed, but only print out the
1632*4882a593Smuzhiyun 	 * bits that matter
1633*4882a593Smuzhiyun 	 */
1634*4882a593Smuzhiyun 	dev_dbg(dev, "%d set of Temperatures: ===>\n", NUMBER_OF_TEMPIN);
1635*4882a593Smuzhiyun 	for (i = 0; i < 3; i++)
1636*4882a593Smuzhiyun 		dev_dbg(dev, "temp1[%d] is: 0x%02x\n", i, (u8) data->temp1[i]);
1637*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
1638*4882a593Smuzhiyun 		for (j = 0; j < 3; j++) {
1639*4882a593Smuzhiyun 			dev_dbg(dev, "temp_add[%d][%d] is: 0x%04x\n", i, j,
1640*4882a593Smuzhiyun 				(u16) data->temp_add[i][j]);
1641*4882a593Smuzhiyun 		}
1642*4882a593Smuzhiyun 	}
1643*4882a593Smuzhiyun 
1644*4882a593Smuzhiyun 	dev_dbg(dev, "Misc Information: ===>\n");
1645*4882a593Smuzhiyun 	dev_dbg(dev, "alarm is:     0x%08x\n", data->alarms);
1646*4882a593Smuzhiyun 	dev_dbg(dev, "beep_mask is: 0x%08x\n", data->beep_mask);
1647*4882a593Smuzhiyun 	dev_dbg(dev, "beep_enable is: %d\n", data->beep_enable);
1648*4882a593Smuzhiyun 	dev_dbg(dev, "vid is: 0x%02x\n", data->vid);
1649*4882a593Smuzhiyun 	dev_dbg(dev, "vrm is: 0x%02x\n", data->vrm);
1650*4882a593Smuzhiyun 	dev_dbg(dev, "=======End of w83791d debug values========\n");
1651*4882a593Smuzhiyun 	dev_dbg(dev, "\n");
1652*4882a593Smuzhiyun }
1653*4882a593Smuzhiyun #endif
1654*4882a593Smuzhiyun 
1655*4882a593Smuzhiyun module_i2c_driver(w83791d_driver);
1656*4882a593Smuzhiyun 
1657*4882a593Smuzhiyun MODULE_AUTHOR("Charles Spirakis <bezaur@gmail.com>");
1658*4882a593Smuzhiyun MODULE_DESCRIPTION("W83791D driver");
1659*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1660