xref: /OK3568_Linux_fs/kernel/drivers/hwmon/w83773g.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2017 IBM Corp.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Driver for the Nuvoton W83773G SMBus temperature sensor IC.
6*4882a593Smuzhiyun  * Supported models: W83773G
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/hwmon.h>
13*4882a593Smuzhiyun #include <linux/hwmon-sysfs.h>
14*4882a593Smuzhiyun #include <linux/err.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* W83773 has 3 channels */
19*4882a593Smuzhiyun #define W83773_CHANNELS				3
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* The W83773 registers */
22*4882a593Smuzhiyun #define W83773_CONVERSION_RATE_REG_READ		0x04
23*4882a593Smuzhiyun #define W83773_CONVERSION_RATE_REG_WRITE	0x0A
24*4882a593Smuzhiyun #define W83773_MANUFACTURER_ID_REG		0xFE
25*4882a593Smuzhiyun #define W83773_LOCAL_TEMP			0x00
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun static const u8 W83773_STATUS[2] = { 0x02, 0x17 };
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun static const u8 W83773_TEMP_LSB[2] = { 0x10, 0x25 };
30*4882a593Smuzhiyun static const u8 W83773_TEMP_MSB[2] = { 0x01, 0x24 };
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun static const u8 W83773_OFFSET_LSB[2] = { 0x12, 0x16 };
33*4882a593Smuzhiyun static const u8 W83773_OFFSET_MSB[2] = { 0x11, 0x15 };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /* this is the number of sensors in the device */
36*4882a593Smuzhiyun static const struct i2c_device_id w83773_id[] = {
37*4882a593Smuzhiyun 	{ "w83773g" },
38*4882a593Smuzhiyun 	{ }
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, w83773_id);
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun static const struct of_device_id __maybe_unused w83773_of_match[] = {
44*4882a593Smuzhiyun 	{
45*4882a593Smuzhiyun 		.compatible = "nuvoton,w83773g"
46*4882a593Smuzhiyun 	},
47*4882a593Smuzhiyun 	{ },
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, w83773_of_match);
50*4882a593Smuzhiyun 
temp_of_local(s8 reg)51*4882a593Smuzhiyun static inline long temp_of_local(s8 reg)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun 	return reg * 1000;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun 
temp_of_remote(s8 hb,u8 lb)56*4882a593Smuzhiyun static inline long temp_of_remote(s8 hb, u8 lb)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun 	return (hb << 3 | lb >> 5) * 125;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
get_local_temp(struct regmap * regmap,long * val)61*4882a593Smuzhiyun static int get_local_temp(struct regmap *regmap, long *val)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	unsigned int regval;
64*4882a593Smuzhiyun 	int ret;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	ret = regmap_read(regmap, W83773_LOCAL_TEMP, &regval);
67*4882a593Smuzhiyun 	if (ret < 0)
68*4882a593Smuzhiyun 		return ret;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	*val = temp_of_local(regval);
71*4882a593Smuzhiyun 	return 0;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
get_remote_temp(struct regmap * regmap,int index,long * val)74*4882a593Smuzhiyun static int get_remote_temp(struct regmap *regmap, int index, long *val)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	unsigned int regval_high;
77*4882a593Smuzhiyun 	unsigned int regval_low;
78*4882a593Smuzhiyun 	int ret;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	ret = regmap_read(regmap, W83773_TEMP_MSB[index], &regval_high);
81*4882a593Smuzhiyun 	if (ret < 0)
82*4882a593Smuzhiyun 		return ret;
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	ret = regmap_read(regmap, W83773_TEMP_LSB[index], &regval_low);
85*4882a593Smuzhiyun 	if (ret < 0)
86*4882a593Smuzhiyun 		return ret;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	*val = temp_of_remote(regval_high, regval_low);
89*4882a593Smuzhiyun 	return 0;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun 
get_fault(struct regmap * regmap,int index,long * val)92*4882a593Smuzhiyun static int get_fault(struct regmap *regmap, int index, long *val)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	unsigned int regval;
95*4882a593Smuzhiyun 	int ret;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	ret = regmap_read(regmap, W83773_STATUS[index], &regval);
98*4882a593Smuzhiyun 	if (ret < 0)
99*4882a593Smuzhiyun 		return ret;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	*val = (regval & 0x04) >> 2;
102*4882a593Smuzhiyun 	return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun 
get_offset(struct regmap * regmap,int index,long * val)105*4882a593Smuzhiyun static int get_offset(struct regmap *regmap, int index, long *val)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	unsigned int regval_high;
108*4882a593Smuzhiyun 	unsigned int regval_low;
109*4882a593Smuzhiyun 	int ret;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	ret = regmap_read(regmap, W83773_OFFSET_MSB[index], &regval_high);
112*4882a593Smuzhiyun 	if (ret < 0)
113*4882a593Smuzhiyun 		return ret;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	ret = regmap_read(regmap, W83773_OFFSET_LSB[index], &regval_low);
116*4882a593Smuzhiyun 	if (ret < 0)
117*4882a593Smuzhiyun 		return ret;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	*val = temp_of_remote(regval_high, regval_low);
120*4882a593Smuzhiyun 	return 0;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun 
set_offset(struct regmap * regmap,int index,long val)123*4882a593Smuzhiyun static int set_offset(struct regmap *regmap, int index, long val)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	int ret;
126*4882a593Smuzhiyun 	u8 high_byte;
127*4882a593Smuzhiyun 	u8 low_byte;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	val = clamp_val(val, -127825, 127825);
130*4882a593Smuzhiyun 	/* offset value equals to (high_byte << 3 | low_byte >> 5) * 125 */
131*4882a593Smuzhiyun 	val /= 125;
132*4882a593Smuzhiyun 	high_byte = val >> 3;
133*4882a593Smuzhiyun 	low_byte = (val & 0x07) << 5;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	ret = regmap_write(regmap, W83773_OFFSET_MSB[index], high_byte);
136*4882a593Smuzhiyun 	if (ret < 0)
137*4882a593Smuzhiyun 		return ret;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	return regmap_write(regmap, W83773_OFFSET_LSB[index], low_byte);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
get_update_interval(struct regmap * regmap,long * val)142*4882a593Smuzhiyun static int get_update_interval(struct regmap *regmap, long *val)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	unsigned int regval;
145*4882a593Smuzhiyun 	int ret;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	ret = regmap_read(regmap, W83773_CONVERSION_RATE_REG_READ, &regval);
148*4882a593Smuzhiyun 	if (ret < 0)
149*4882a593Smuzhiyun 		return ret;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	*val = 16000 >> regval;
152*4882a593Smuzhiyun 	return 0;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
set_update_interval(struct regmap * regmap,long val)155*4882a593Smuzhiyun static int set_update_interval(struct regmap *regmap, long val)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	int rate;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	/*
160*4882a593Smuzhiyun 	 * For valid rates, interval can be calculated as
161*4882a593Smuzhiyun 	 *	interval = (1 << (8 - rate)) * 62.5;
162*4882a593Smuzhiyun 	 * Rounded rate is therefore
163*4882a593Smuzhiyun 	 *	rate = 8 - __fls(interval * 8 / (62.5 * 7));
164*4882a593Smuzhiyun 	 * Use clamp_val() to avoid overflows, and to ensure valid input
165*4882a593Smuzhiyun 	 * for __fls.
166*4882a593Smuzhiyun 	 */
167*4882a593Smuzhiyun 	val = clamp_val(val, 62, 16000) * 10;
168*4882a593Smuzhiyun 	rate = 8 - __fls((val * 8 / (625 * 7)));
169*4882a593Smuzhiyun 	return regmap_write(regmap, W83773_CONVERSION_RATE_REG_WRITE, rate);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun 
w83773_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)172*4882a593Smuzhiyun static int w83773_read(struct device *dev, enum hwmon_sensor_types type,
173*4882a593Smuzhiyun 		       u32 attr, int channel, long *val)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun 	struct regmap *regmap = dev_get_drvdata(dev);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	if (type == hwmon_chip) {
178*4882a593Smuzhiyun 		if (attr == hwmon_chip_update_interval)
179*4882a593Smuzhiyun 			return get_update_interval(regmap, val);
180*4882a593Smuzhiyun 		return -EOPNOTSUPP;
181*4882a593Smuzhiyun 	}
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	switch (attr) {
184*4882a593Smuzhiyun 	case hwmon_temp_input:
185*4882a593Smuzhiyun 		if (channel == 0)
186*4882a593Smuzhiyun 			return get_local_temp(regmap, val);
187*4882a593Smuzhiyun 		return get_remote_temp(regmap, channel - 1, val);
188*4882a593Smuzhiyun 	case hwmon_temp_fault:
189*4882a593Smuzhiyun 		return get_fault(regmap, channel - 1, val);
190*4882a593Smuzhiyun 	case hwmon_temp_offset:
191*4882a593Smuzhiyun 		return get_offset(regmap, channel - 1, val);
192*4882a593Smuzhiyun 	default:
193*4882a593Smuzhiyun 		return -EOPNOTSUPP;
194*4882a593Smuzhiyun 	}
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun 
w83773_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)197*4882a593Smuzhiyun static int w83773_write(struct device *dev, enum hwmon_sensor_types type,
198*4882a593Smuzhiyun 			u32 attr, int channel, long val)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	struct regmap *regmap = dev_get_drvdata(dev);
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	if (type == hwmon_chip && attr == hwmon_chip_update_interval)
203*4882a593Smuzhiyun 		return set_update_interval(regmap, val);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	if (type == hwmon_temp && attr == hwmon_temp_offset)
206*4882a593Smuzhiyun 		return set_offset(regmap, channel - 1, val);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	return -EOPNOTSUPP;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun 
w83773_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)211*4882a593Smuzhiyun static umode_t w83773_is_visible(const void *data, enum hwmon_sensor_types type,
212*4882a593Smuzhiyun 				 u32 attr, int channel)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun 	switch (type) {
215*4882a593Smuzhiyun 	case hwmon_chip:
216*4882a593Smuzhiyun 		switch (attr) {
217*4882a593Smuzhiyun 		case hwmon_chip_update_interval:
218*4882a593Smuzhiyun 			return 0644;
219*4882a593Smuzhiyun 		}
220*4882a593Smuzhiyun 		break;
221*4882a593Smuzhiyun 	case hwmon_temp:
222*4882a593Smuzhiyun 		switch (attr) {
223*4882a593Smuzhiyun 		case hwmon_temp_input:
224*4882a593Smuzhiyun 		case hwmon_temp_fault:
225*4882a593Smuzhiyun 			return 0444;
226*4882a593Smuzhiyun 		case hwmon_temp_offset:
227*4882a593Smuzhiyun 			return 0644;
228*4882a593Smuzhiyun 		}
229*4882a593Smuzhiyun 		break;
230*4882a593Smuzhiyun 	default:
231*4882a593Smuzhiyun 		break;
232*4882a593Smuzhiyun 	}
233*4882a593Smuzhiyun 	return 0;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun static const struct hwmon_channel_info *w83773_info[] = {
237*4882a593Smuzhiyun 	HWMON_CHANNEL_INFO(chip,
238*4882a593Smuzhiyun 			   HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),
239*4882a593Smuzhiyun 	HWMON_CHANNEL_INFO(temp,
240*4882a593Smuzhiyun 			   HWMON_T_INPUT,
241*4882a593Smuzhiyun 			   HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_OFFSET,
242*4882a593Smuzhiyun 			   HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_OFFSET),
243*4882a593Smuzhiyun 	NULL
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun static const struct hwmon_ops w83773_ops = {
247*4882a593Smuzhiyun 	.is_visible = w83773_is_visible,
248*4882a593Smuzhiyun 	.read = w83773_read,
249*4882a593Smuzhiyun 	.write = w83773_write,
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun static const struct hwmon_chip_info w83773_chip_info = {
253*4882a593Smuzhiyun 	.ops = &w83773_ops,
254*4882a593Smuzhiyun 	.info = w83773_info,
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun static const struct regmap_config w83773_regmap_config = {
258*4882a593Smuzhiyun 	.reg_bits = 8,
259*4882a593Smuzhiyun 	.val_bits = 8,
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun 
w83773_probe(struct i2c_client * client)262*4882a593Smuzhiyun static int w83773_probe(struct i2c_client *client)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun 	struct device *dev = &client->dev;
265*4882a593Smuzhiyun 	struct device *hwmon_dev;
266*4882a593Smuzhiyun 	struct regmap *regmap;
267*4882a593Smuzhiyun 	int ret;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	regmap = devm_regmap_init_i2c(client, &w83773_regmap_config);
270*4882a593Smuzhiyun 	if (IS_ERR(regmap)) {
271*4882a593Smuzhiyun 		dev_err(dev, "failed to allocate register map\n");
272*4882a593Smuzhiyun 		return PTR_ERR(regmap);
273*4882a593Smuzhiyun 	}
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	/* Set the conversion rate to 2 Hz */
276*4882a593Smuzhiyun 	ret = regmap_write(regmap, W83773_CONVERSION_RATE_REG_WRITE, 0x05);
277*4882a593Smuzhiyun 	if (ret < 0) {
278*4882a593Smuzhiyun 		dev_err(&client->dev, "error writing config rate register\n");
279*4882a593Smuzhiyun 		return ret;
280*4882a593Smuzhiyun 	}
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	i2c_set_clientdata(client, regmap);
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	hwmon_dev = devm_hwmon_device_register_with_info(dev,
285*4882a593Smuzhiyun 							 client->name,
286*4882a593Smuzhiyun 							 regmap,
287*4882a593Smuzhiyun 							 &w83773_chip_info,
288*4882a593Smuzhiyun 							 NULL);
289*4882a593Smuzhiyun 	return PTR_ERR_OR_ZERO(hwmon_dev);
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun static struct i2c_driver w83773_driver = {
293*4882a593Smuzhiyun 	.class = I2C_CLASS_HWMON,
294*4882a593Smuzhiyun 	.driver = {
295*4882a593Smuzhiyun 		.name	= "w83773g",
296*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(w83773_of_match),
297*4882a593Smuzhiyun 	},
298*4882a593Smuzhiyun 	.probe_new = w83773_probe,
299*4882a593Smuzhiyun 	.id_table = w83773_id,
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun module_i2c_driver(w83773_driver);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun MODULE_AUTHOR("Lei YU <mine260309@gmail.com>");
305*4882a593Smuzhiyun MODULE_DESCRIPTION("W83773G temperature sensor driver");
306*4882a593Smuzhiyun MODULE_LICENSE("GPL");
307