1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /***************************************************************************
3*4882a593Smuzhiyun * Copyright (C) 2010-2012 Hans de Goede <hdegoede@redhat.com> *
4*4882a593Smuzhiyun * *
5*4882a593Smuzhiyun ***************************************************************************/
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/acpi.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/fs.h>
17*4882a593Smuzhiyun #include <linux/watchdog.h>
18*4882a593Smuzhiyun #include <linux/uaccess.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include "sch56xx-common.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* Insmod parameters */
23*4882a593Smuzhiyun static int nowayout = WATCHDOG_NOWAYOUT;
24*4882a593Smuzhiyun module_param(nowayout, int, 0);
25*4882a593Smuzhiyun MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
26*4882a593Smuzhiyun __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define SIO_SCH56XX_LD_EM 0x0C /* Embedded uController Logical Dev */
29*4882a593Smuzhiyun #define SIO_UNLOCK_KEY 0x55 /* Key to enable Super-I/O */
30*4882a593Smuzhiyun #define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define SIO_REG_LDSEL 0x07 /* Logical device select */
33*4882a593Smuzhiyun #define SIO_REG_DEVID 0x20 /* Device ID */
34*4882a593Smuzhiyun #define SIO_REG_ENABLE 0x30 /* Logical device enable */
35*4882a593Smuzhiyun #define SIO_REG_ADDR 0x66 /* Logical device address (2 bytes) */
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define SIO_SCH5627_ID 0xC6 /* Chipset ID */
38*4882a593Smuzhiyun #define SIO_SCH5636_ID 0xC7 /* Chipset ID */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define REGION_LENGTH 10
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define SCH56XX_CMD_READ 0x02
43*4882a593Smuzhiyun #define SCH56XX_CMD_WRITE 0x03
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Watchdog registers */
46*4882a593Smuzhiyun #define SCH56XX_REG_WDOG_PRESET 0x58B
47*4882a593Smuzhiyun #define SCH56XX_REG_WDOG_CONTROL 0x58C
48*4882a593Smuzhiyun #define SCH56XX_WDOG_TIME_BASE_SEC 0x01
49*4882a593Smuzhiyun #define SCH56XX_REG_WDOG_OUTPUT_ENABLE 0x58E
50*4882a593Smuzhiyun #define SCH56XX_WDOG_OUTPUT_ENABLE 0x02
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun struct sch56xx_watchdog_data {
53*4882a593Smuzhiyun u16 addr;
54*4882a593Smuzhiyun struct mutex *io_lock;
55*4882a593Smuzhiyun struct watchdog_info wdinfo;
56*4882a593Smuzhiyun struct watchdog_device wddev;
57*4882a593Smuzhiyun u8 watchdog_preset;
58*4882a593Smuzhiyun u8 watchdog_control;
59*4882a593Smuzhiyun u8 watchdog_output_enable;
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun static struct platform_device *sch56xx_pdev;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Super I/O functions */
superio_inb(int base,int reg)65*4882a593Smuzhiyun static inline int superio_inb(int base, int reg)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun outb(reg, base);
68*4882a593Smuzhiyun return inb(base + 1);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
superio_enter(int base)71*4882a593Smuzhiyun static inline int superio_enter(int base)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun /* Don't step on other drivers' I/O space by accident */
74*4882a593Smuzhiyun if (!request_muxed_region(base, 2, "sch56xx")) {
75*4882a593Smuzhiyun pr_err("I/O address 0x%04x already in use\n", base);
76*4882a593Smuzhiyun return -EBUSY;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun outb(SIO_UNLOCK_KEY, base);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
superio_select(int base,int ld)84*4882a593Smuzhiyun static inline void superio_select(int base, int ld)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun outb(SIO_REG_LDSEL, base);
87*4882a593Smuzhiyun outb(ld, base + 1);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
superio_exit(int base)90*4882a593Smuzhiyun static inline void superio_exit(int base)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun outb(SIO_LOCK_KEY, base);
93*4882a593Smuzhiyun release_region(base, 2);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
sch56xx_send_cmd(u16 addr,u8 cmd,u16 reg,u8 v)96*4882a593Smuzhiyun static int sch56xx_send_cmd(u16 addr, u8 cmd, u16 reg, u8 v)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun u8 val;
99*4882a593Smuzhiyun int i;
100*4882a593Smuzhiyun /*
101*4882a593Smuzhiyun * According to SMSC for the commands we use the maximum time for
102*4882a593Smuzhiyun * the EM to respond is 15 ms, but testing shows in practice it
103*4882a593Smuzhiyun * responds within 15-32 reads, so we first busy poll, and if
104*4882a593Smuzhiyun * that fails sleep a bit and try again until we are way past
105*4882a593Smuzhiyun * the 15 ms maximum response time.
106*4882a593Smuzhiyun */
107*4882a593Smuzhiyun const int max_busy_polls = 64;
108*4882a593Smuzhiyun const int max_lazy_polls = 32;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* (Optional) Write-Clear the EC to Host Mailbox Register */
111*4882a593Smuzhiyun val = inb(addr + 1);
112*4882a593Smuzhiyun outb(val, addr + 1);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* Set Mailbox Address Pointer to first location in Region 1 */
115*4882a593Smuzhiyun outb(0x00, addr + 2);
116*4882a593Smuzhiyun outb(0x80, addr + 3);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* Write Request Packet Header */
119*4882a593Smuzhiyun outb(cmd, addr + 4); /* VREG Access Type read:0x02 write:0x03 */
120*4882a593Smuzhiyun outb(0x01, addr + 5); /* # of Entries: 1 Byte (8-bit) */
121*4882a593Smuzhiyun outb(0x04, addr + 2); /* Mailbox AP to first data entry loc. */
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* Write Value field */
124*4882a593Smuzhiyun if (cmd == SCH56XX_CMD_WRITE)
125*4882a593Smuzhiyun outb(v, addr + 4);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* Write Address field */
128*4882a593Smuzhiyun outb(reg & 0xff, addr + 6);
129*4882a593Smuzhiyun outb(reg >> 8, addr + 7);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* Execute the Random Access Command */
132*4882a593Smuzhiyun outb(0x01, addr); /* Write 01h to the Host-to-EC register */
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* EM Interface Polling "Algorithm" */
135*4882a593Smuzhiyun for (i = 0; i < max_busy_polls + max_lazy_polls; i++) {
136*4882a593Smuzhiyun if (i >= max_busy_polls)
137*4882a593Smuzhiyun msleep(1);
138*4882a593Smuzhiyun /* Read Interrupt source Register */
139*4882a593Smuzhiyun val = inb(addr + 8);
140*4882a593Smuzhiyun /* Write Clear the interrupt source bits */
141*4882a593Smuzhiyun if (val)
142*4882a593Smuzhiyun outb(val, addr + 8);
143*4882a593Smuzhiyun /* Command Completed ? */
144*4882a593Smuzhiyun if (val & 0x01)
145*4882a593Smuzhiyun break;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun if (i == max_busy_polls + max_lazy_polls) {
148*4882a593Smuzhiyun pr_err("Max retries exceeded reading virtual register 0x%04hx (%d)\n",
149*4882a593Smuzhiyun reg, 1);
150*4882a593Smuzhiyun return -EIO;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /*
154*4882a593Smuzhiyun * According to SMSC we may need to retry this, but sofar I've always
155*4882a593Smuzhiyun * seen this succeed in 1 try.
156*4882a593Smuzhiyun */
157*4882a593Smuzhiyun for (i = 0; i < max_busy_polls; i++) {
158*4882a593Smuzhiyun /* Read EC-to-Host Register */
159*4882a593Smuzhiyun val = inb(addr + 1);
160*4882a593Smuzhiyun /* Command Completed ? */
161*4882a593Smuzhiyun if (val == 0x01)
162*4882a593Smuzhiyun break;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun if (i == 0)
165*4882a593Smuzhiyun pr_warn("EC reports: 0x%02x reading virtual register 0x%04hx\n",
166*4882a593Smuzhiyun (unsigned int)val, reg);
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun if (i == max_busy_polls) {
169*4882a593Smuzhiyun pr_err("Max retries exceeded reading virtual register 0x%04hx (%d)\n",
170*4882a593Smuzhiyun reg, 2);
171*4882a593Smuzhiyun return -EIO;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /*
175*4882a593Smuzhiyun * According to the SMSC app note we should now do:
176*4882a593Smuzhiyun *
177*4882a593Smuzhiyun * Set Mailbox Address Pointer to first location in Region 1 *
178*4882a593Smuzhiyun * outb(0x00, addr + 2);
179*4882a593Smuzhiyun * outb(0x80, addr + 3);
180*4882a593Smuzhiyun *
181*4882a593Smuzhiyun * But if we do that things don't work, so let's not.
182*4882a593Smuzhiyun */
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /* Read Value field */
185*4882a593Smuzhiyun if (cmd == SCH56XX_CMD_READ)
186*4882a593Smuzhiyun return inb(addr + 4);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun return 0;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
sch56xx_read_virtual_reg(u16 addr,u16 reg)191*4882a593Smuzhiyun int sch56xx_read_virtual_reg(u16 addr, u16 reg)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun return sch56xx_send_cmd(addr, SCH56XX_CMD_READ, reg, 0);
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun EXPORT_SYMBOL(sch56xx_read_virtual_reg);
196*4882a593Smuzhiyun
sch56xx_write_virtual_reg(u16 addr,u16 reg,u8 val)197*4882a593Smuzhiyun int sch56xx_write_virtual_reg(u16 addr, u16 reg, u8 val)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun return sch56xx_send_cmd(addr, SCH56XX_CMD_WRITE, reg, val);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun EXPORT_SYMBOL(sch56xx_write_virtual_reg);
202*4882a593Smuzhiyun
sch56xx_read_virtual_reg16(u16 addr,u16 reg)203*4882a593Smuzhiyun int sch56xx_read_virtual_reg16(u16 addr, u16 reg)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun int lsb, msb;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /* Read LSB first, this will cause the matching MSB to be latched */
208*4882a593Smuzhiyun lsb = sch56xx_read_virtual_reg(addr, reg);
209*4882a593Smuzhiyun if (lsb < 0)
210*4882a593Smuzhiyun return lsb;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun msb = sch56xx_read_virtual_reg(addr, reg + 1);
213*4882a593Smuzhiyun if (msb < 0)
214*4882a593Smuzhiyun return msb;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun return lsb | (msb << 8);
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun EXPORT_SYMBOL(sch56xx_read_virtual_reg16);
219*4882a593Smuzhiyun
sch56xx_read_virtual_reg12(u16 addr,u16 msb_reg,u16 lsn_reg,int high_nibble)220*4882a593Smuzhiyun int sch56xx_read_virtual_reg12(u16 addr, u16 msb_reg, u16 lsn_reg,
221*4882a593Smuzhiyun int high_nibble)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun int msb, lsn;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /* Read MSB first, this will cause the matching LSN to be latched */
226*4882a593Smuzhiyun msb = sch56xx_read_virtual_reg(addr, msb_reg);
227*4882a593Smuzhiyun if (msb < 0)
228*4882a593Smuzhiyun return msb;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun lsn = sch56xx_read_virtual_reg(addr, lsn_reg);
231*4882a593Smuzhiyun if (lsn < 0)
232*4882a593Smuzhiyun return lsn;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun if (high_nibble)
235*4882a593Smuzhiyun return (msb << 4) | (lsn >> 4);
236*4882a593Smuzhiyun else
237*4882a593Smuzhiyun return (msb << 4) | (lsn & 0x0f);
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun EXPORT_SYMBOL(sch56xx_read_virtual_reg12);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /*
242*4882a593Smuzhiyun * Watchdog routines
243*4882a593Smuzhiyun */
244*4882a593Smuzhiyun
watchdog_set_timeout(struct watchdog_device * wddev,unsigned int timeout)245*4882a593Smuzhiyun static int watchdog_set_timeout(struct watchdog_device *wddev,
246*4882a593Smuzhiyun unsigned int timeout)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev);
249*4882a593Smuzhiyun unsigned int resolution;
250*4882a593Smuzhiyun u8 control;
251*4882a593Smuzhiyun int ret;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /* 1 second or 60 second resolution? */
254*4882a593Smuzhiyun if (timeout <= 255)
255*4882a593Smuzhiyun resolution = 1;
256*4882a593Smuzhiyun else
257*4882a593Smuzhiyun resolution = 60;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun if (timeout < resolution || timeout > (resolution * 255))
260*4882a593Smuzhiyun return -EINVAL;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun if (resolution == 1)
263*4882a593Smuzhiyun control = data->watchdog_control | SCH56XX_WDOG_TIME_BASE_SEC;
264*4882a593Smuzhiyun else
265*4882a593Smuzhiyun control = data->watchdog_control & ~SCH56XX_WDOG_TIME_BASE_SEC;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun if (data->watchdog_control != control) {
268*4882a593Smuzhiyun mutex_lock(data->io_lock);
269*4882a593Smuzhiyun ret = sch56xx_write_virtual_reg(data->addr,
270*4882a593Smuzhiyun SCH56XX_REG_WDOG_CONTROL,
271*4882a593Smuzhiyun control);
272*4882a593Smuzhiyun mutex_unlock(data->io_lock);
273*4882a593Smuzhiyun if (ret)
274*4882a593Smuzhiyun return ret;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun data->watchdog_control = control;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun /*
280*4882a593Smuzhiyun * Remember new timeout value, but do not write as that (re)starts
281*4882a593Smuzhiyun * the watchdog countdown.
282*4882a593Smuzhiyun */
283*4882a593Smuzhiyun data->watchdog_preset = DIV_ROUND_UP(timeout, resolution);
284*4882a593Smuzhiyun wddev->timeout = data->watchdog_preset * resolution;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun return 0;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
watchdog_start(struct watchdog_device * wddev)289*4882a593Smuzhiyun static int watchdog_start(struct watchdog_device *wddev)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev);
292*4882a593Smuzhiyun int ret;
293*4882a593Smuzhiyun u8 val;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun /*
296*4882a593Smuzhiyun * The sch56xx's watchdog cannot really be started / stopped
297*4882a593Smuzhiyun * it is always running, but we can avoid the timer expiring
298*4882a593Smuzhiyun * from causing a system reset by clearing the output enable bit.
299*4882a593Smuzhiyun *
300*4882a593Smuzhiyun * The sch56xx's watchdog will set the watchdog event bit, bit 0
301*4882a593Smuzhiyun * of the second interrupt source register (at base-address + 9),
302*4882a593Smuzhiyun * when the timer expires.
303*4882a593Smuzhiyun *
304*4882a593Smuzhiyun * This will only cause a system reset if the 0-1 flank happens when
305*4882a593Smuzhiyun * output enable is true. Setting output enable after the flank will
306*4882a593Smuzhiyun * not cause a reset, nor will the timer expiring a second time.
307*4882a593Smuzhiyun * This means we must clear the watchdog event bit in case it is set.
308*4882a593Smuzhiyun *
309*4882a593Smuzhiyun * The timer may still be running (after a recent watchdog_stop) and
310*4882a593Smuzhiyun * mere milliseconds away from expiring, so the timer must be reset
311*4882a593Smuzhiyun * first!
312*4882a593Smuzhiyun */
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun mutex_lock(data->io_lock);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun /* 1. Reset the watchdog countdown counter */
317*4882a593Smuzhiyun ret = sch56xx_write_virtual_reg(data->addr, SCH56XX_REG_WDOG_PRESET,
318*4882a593Smuzhiyun data->watchdog_preset);
319*4882a593Smuzhiyun if (ret)
320*4882a593Smuzhiyun goto leave;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /* 2. Enable output */
323*4882a593Smuzhiyun val = data->watchdog_output_enable | SCH56XX_WDOG_OUTPUT_ENABLE;
324*4882a593Smuzhiyun ret = sch56xx_write_virtual_reg(data->addr,
325*4882a593Smuzhiyun SCH56XX_REG_WDOG_OUTPUT_ENABLE, val);
326*4882a593Smuzhiyun if (ret)
327*4882a593Smuzhiyun goto leave;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun data->watchdog_output_enable = val;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun /* 3. Clear the watchdog event bit if set */
332*4882a593Smuzhiyun val = inb(data->addr + 9);
333*4882a593Smuzhiyun if (val & 0x01)
334*4882a593Smuzhiyun outb(0x01, data->addr + 9);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun leave:
337*4882a593Smuzhiyun mutex_unlock(data->io_lock);
338*4882a593Smuzhiyun return ret;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
watchdog_trigger(struct watchdog_device * wddev)341*4882a593Smuzhiyun static int watchdog_trigger(struct watchdog_device *wddev)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev);
344*4882a593Smuzhiyun int ret;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun /* Reset the watchdog countdown counter */
347*4882a593Smuzhiyun mutex_lock(data->io_lock);
348*4882a593Smuzhiyun ret = sch56xx_write_virtual_reg(data->addr, SCH56XX_REG_WDOG_PRESET,
349*4882a593Smuzhiyun data->watchdog_preset);
350*4882a593Smuzhiyun mutex_unlock(data->io_lock);
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun return ret;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
watchdog_stop(struct watchdog_device * wddev)355*4882a593Smuzhiyun static int watchdog_stop(struct watchdog_device *wddev)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun struct sch56xx_watchdog_data *data = watchdog_get_drvdata(wddev);
358*4882a593Smuzhiyun int ret = 0;
359*4882a593Smuzhiyun u8 val;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun val = data->watchdog_output_enable & ~SCH56XX_WDOG_OUTPUT_ENABLE;
362*4882a593Smuzhiyun mutex_lock(data->io_lock);
363*4882a593Smuzhiyun ret = sch56xx_write_virtual_reg(data->addr,
364*4882a593Smuzhiyun SCH56XX_REG_WDOG_OUTPUT_ENABLE, val);
365*4882a593Smuzhiyun mutex_unlock(data->io_lock);
366*4882a593Smuzhiyun if (ret)
367*4882a593Smuzhiyun return ret;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun data->watchdog_output_enable = val;
370*4882a593Smuzhiyun return 0;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun static const struct watchdog_ops watchdog_ops = {
374*4882a593Smuzhiyun .owner = THIS_MODULE,
375*4882a593Smuzhiyun .start = watchdog_start,
376*4882a593Smuzhiyun .stop = watchdog_stop,
377*4882a593Smuzhiyun .ping = watchdog_trigger,
378*4882a593Smuzhiyun .set_timeout = watchdog_set_timeout,
379*4882a593Smuzhiyun };
380*4882a593Smuzhiyun
sch56xx_watchdog_register(struct device * parent,u16 addr,u32 revision,struct mutex * io_lock,int check_enabled)381*4882a593Smuzhiyun struct sch56xx_watchdog_data *sch56xx_watchdog_register(struct device *parent,
382*4882a593Smuzhiyun u16 addr, u32 revision, struct mutex *io_lock, int check_enabled)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun struct sch56xx_watchdog_data *data;
385*4882a593Smuzhiyun int err, control, output_enable;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun /* Cache the watchdog registers */
388*4882a593Smuzhiyun mutex_lock(io_lock);
389*4882a593Smuzhiyun control =
390*4882a593Smuzhiyun sch56xx_read_virtual_reg(addr, SCH56XX_REG_WDOG_CONTROL);
391*4882a593Smuzhiyun output_enable =
392*4882a593Smuzhiyun sch56xx_read_virtual_reg(addr, SCH56XX_REG_WDOG_OUTPUT_ENABLE);
393*4882a593Smuzhiyun mutex_unlock(io_lock);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun if (control < 0)
396*4882a593Smuzhiyun return NULL;
397*4882a593Smuzhiyun if (output_enable < 0)
398*4882a593Smuzhiyun return NULL;
399*4882a593Smuzhiyun if (check_enabled && !(output_enable & SCH56XX_WDOG_OUTPUT_ENABLE)) {
400*4882a593Smuzhiyun pr_warn("Watchdog not enabled by BIOS, not registering\n");
401*4882a593Smuzhiyun return NULL;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun data = kzalloc(sizeof(struct sch56xx_watchdog_data), GFP_KERNEL);
405*4882a593Smuzhiyun if (!data)
406*4882a593Smuzhiyun return NULL;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun data->addr = addr;
409*4882a593Smuzhiyun data->io_lock = io_lock;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun strlcpy(data->wdinfo.identity, "sch56xx watchdog",
412*4882a593Smuzhiyun sizeof(data->wdinfo.identity));
413*4882a593Smuzhiyun data->wdinfo.firmware_version = revision;
414*4882a593Smuzhiyun data->wdinfo.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT;
415*4882a593Smuzhiyun if (!nowayout)
416*4882a593Smuzhiyun data->wdinfo.options |= WDIOF_MAGICCLOSE;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun data->wddev.info = &data->wdinfo;
419*4882a593Smuzhiyun data->wddev.ops = &watchdog_ops;
420*4882a593Smuzhiyun data->wddev.parent = parent;
421*4882a593Smuzhiyun data->wddev.timeout = 60;
422*4882a593Smuzhiyun data->wddev.min_timeout = 1;
423*4882a593Smuzhiyun data->wddev.max_timeout = 255 * 60;
424*4882a593Smuzhiyun if (nowayout)
425*4882a593Smuzhiyun set_bit(WDOG_NO_WAY_OUT, &data->wddev.status);
426*4882a593Smuzhiyun if (output_enable & SCH56XX_WDOG_OUTPUT_ENABLE)
427*4882a593Smuzhiyun set_bit(WDOG_HW_RUNNING, &data->wddev.status);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun /* Since the watchdog uses a downcounter there is no register to read
430*4882a593Smuzhiyun the BIOS set timeout from (if any was set at all) ->
431*4882a593Smuzhiyun Choose a preset which will give us a 1 minute timeout */
432*4882a593Smuzhiyun if (control & SCH56XX_WDOG_TIME_BASE_SEC)
433*4882a593Smuzhiyun data->watchdog_preset = 60; /* seconds */
434*4882a593Smuzhiyun else
435*4882a593Smuzhiyun data->watchdog_preset = 1; /* minute */
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun data->watchdog_control = control;
438*4882a593Smuzhiyun data->watchdog_output_enable = output_enable;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun watchdog_set_drvdata(&data->wddev, data);
441*4882a593Smuzhiyun err = watchdog_register_device(&data->wddev);
442*4882a593Smuzhiyun if (err) {
443*4882a593Smuzhiyun pr_err("Registering watchdog chardev: %d\n", err);
444*4882a593Smuzhiyun kfree(data);
445*4882a593Smuzhiyun return NULL;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun return data;
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun EXPORT_SYMBOL(sch56xx_watchdog_register);
451*4882a593Smuzhiyun
sch56xx_watchdog_unregister(struct sch56xx_watchdog_data * data)452*4882a593Smuzhiyun void sch56xx_watchdog_unregister(struct sch56xx_watchdog_data *data)
453*4882a593Smuzhiyun {
454*4882a593Smuzhiyun watchdog_unregister_device(&data->wddev);
455*4882a593Smuzhiyun kfree(data);
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun EXPORT_SYMBOL(sch56xx_watchdog_unregister);
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun /*
460*4882a593Smuzhiyun * platform dev find, add and remove functions
461*4882a593Smuzhiyun */
462*4882a593Smuzhiyun
sch56xx_find(int sioaddr,const char ** name)463*4882a593Smuzhiyun static int __init sch56xx_find(int sioaddr, const char **name)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun u8 devid;
466*4882a593Smuzhiyun unsigned short address;
467*4882a593Smuzhiyun int err;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun err = superio_enter(sioaddr);
470*4882a593Smuzhiyun if (err)
471*4882a593Smuzhiyun return err;
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun devid = superio_inb(sioaddr, SIO_REG_DEVID);
474*4882a593Smuzhiyun switch (devid) {
475*4882a593Smuzhiyun case SIO_SCH5627_ID:
476*4882a593Smuzhiyun *name = "sch5627";
477*4882a593Smuzhiyun break;
478*4882a593Smuzhiyun case SIO_SCH5636_ID:
479*4882a593Smuzhiyun *name = "sch5636";
480*4882a593Smuzhiyun break;
481*4882a593Smuzhiyun default:
482*4882a593Smuzhiyun pr_debug("Unsupported device id: 0x%02x\n",
483*4882a593Smuzhiyun (unsigned int)devid);
484*4882a593Smuzhiyun err = -ENODEV;
485*4882a593Smuzhiyun goto exit;
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun superio_select(sioaddr, SIO_SCH56XX_LD_EM);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun if (!(superio_inb(sioaddr, SIO_REG_ENABLE) & 0x01)) {
491*4882a593Smuzhiyun pr_warn("Device not activated\n");
492*4882a593Smuzhiyun err = -ENODEV;
493*4882a593Smuzhiyun goto exit;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun /*
497*4882a593Smuzhiyun * Warning the order of the low / high byte is the other way around
498*4882a593Smuzhiyun * as on most other superio devices!!
499*4882a593Smuzhiyun */
500*4882a593Smuzhiyun address = superio_inb(sioaddr, SIO_REG_ADDR) |
501*4882a593Smuzhiyun superio_inb(sioaddr, SIO_REG_ADDR + 1) << 8;
502*4882a593Smuzhiyun if (address == 0) {
503*4882a593Smuzhiyun pr_warn("Base address not set\n");
504*4882a593Smuzhiyun err = -ENODEV;
505*4882a593Smuzhiyun goto exit;
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun err = address;
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun exit:
510*4882a593Smuzhiyun superio_exit(sioaddr);
511*4882a593Smuzhiyun return err;
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
sch56xx_device_add(int address,const char * name)514*4882a593Smuzhiyun static int __init sch56xx_device_add(int address, const char *name)
515*4882a593Smuzhiyun {
516*4882a593Smuzhiyun struct resource res = {
517*4882a593Smuzhiyun .start = address,
518*4882a593Smuzhiyun .end = address + REGION_LENGTH - 1,
519*4882a593Smuzhiyun .flags = IORESOURCE_IO,
520*4882a593Smuzhiyun };
521*4882a593Smuzhiyun int err;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun sch56xx_pdev = platform_device_alloc(name, address);
524*4882a593Smuzhiyun if (!sch56xx_pdev)
525*4882a593Smuzhiyun return -ENOMEM;
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun res.name = sch56xx_pdev->name;
528*4882a593Smuzhiyun err = acpi_check_resource_conflict(&res);
529*4882a593Smuzhiyun if (err)
530*4882a593Smuzhiyun goto exit_device_put;
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun err = platform_device_add_resources(sch56xx_pdev, &res, 1);
533*4882a593Smuzhiyun if (err) {
534*4882a593Smuzhiyun pr_err("Device resource addition failed\n");
535*4882a593Smuzhiyun goto exit_device_put;
536*4882a593Smuzhiyun }
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun err = platform_device_add(sch56xx_pdev);
539*4882a593Smuzhiyun if (err) {
540*4882a593Smuzhiyun pr_err("Device addition failed\n");
541*4882a593Smuzhiyun goto exit_device_put;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun return 0;
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun exit_device_put:
547*4882a593Smuzhiyun platform_device_put(sch56xx_pdev);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun return err;
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun
sch56xx_init(void)552*4882a593Smuzhiyun static int __init sch56xx_init(void)
553*4882a593Smuzhiyun {
554*4882a593Smuzhiyun int address;
555*4882a593Smuzhiyun const char *name = NULL;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun address = sch56xx_find(0x4e, &name);
558*4882a593Smuzhiyun if (address < 0)
559*4882a593Smuzhiyun address = sch56xx_find(0x2e, &name);
560*4882a593Smuzhiyun if (address < 0)
561*4882a593Smuzhiyun return address;
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun return sch56xx_device_add(address, name);
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
sch56xx_exit(void)566*4882a593Smuzhiyun static void __exit sch56xx_exit(void)
567*4882a593Smuzhiyun {
568*4882a593Smuzhiyun platform_device_unregister(sch56xx_pdev);
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun MODULE_DESCRIPTION("SMSC SCH56xx Hardware Monitoring Common Code");
572*4882a593Smuzhiyun MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
573*4882a593Smuzhiyun MODULE_LICENSE("GPL");
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun module_init(sch56xx_init);
576*4882a593Smuzhiyun module_exit(sch56xx_exit);
577