xref: /OK3568_Linux_fs/kernel/drivers/hwmon/ina2xx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Driver for Texas Instruments INA219, INA226 power monitor chips
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * INA219:
6*4882a593Smuzhiyun  * Zero Drift Bi-Directional Current/Power Monitor with I2C Interface
7*4882a593Smuzhiyun  * Datasheet: https://www.ti.com/product/ina219
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * INA220:
10*4882a593Smuzhiyun  * Bi-Directional Current/Power Monitor with I2C Interface
11*4882a593Smuzhiyun  * Datasheet: https://www.ti.com/product/ina220
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * INA226:
14*4882a593Smuzhiyun  * Bi-Directional Current/Power Monitor with I2C Interface
15*4882a593Smuzhiyun  * Datasheet: https://www.ti.com/product/ina226
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  * INA230:
18*4882a593Smuzhiyun  * Bi-directional Current/Power Monitor with I2C Interface
19*4882a593Smuzhiyun  * Datasheet: https://www.ti.com/product/ina230
20*4882a593Smuzhiyun  *
21*4882a593Smuzhiyun  * Copyright (C) 2012 Lothar Felten <lothar.felten@gmail.com>
22*4882a593Smuzhiyun  * Thanks to Jan Volkering
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include <linux/kernel.h>
26*4882a593Smuzhiyun #include <linux/module.h>
27*4882a593Smuzhiyun #include <linux/init.h>
28*4882a593Smuzhiyun #include <linux/err.h>
29*4882a593Smuzhiyun #include <linux/slab.h>
30*4882a593Smuzhiyun #include <linux/i2c.h>
31*4882a593Smuzhiyun #include <linux/hwmon.h>
32*4882a593Smuzhiyun #include <linux/hwmon-sysfs.h>
33*4882a593Smuzhiyun #include <linux/jiffies.h>
34*4882a593Smuzhiyun #include <linux/of_device.h>
35*4882a593Smuzhiyun #include <linux/of.h>
36*4882a593Smuzhiyun #include <linux/delay.h>
37*4882a593Smuzhiyun #include <linux/util_macros.h>
38*4882a593Smuzhiyun #include <linux/regmap.h>
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #include <linux/platform_data/ina2xx.h>
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* common register definitions */
43*4882a593Smuzhiyun #define INA2XX_CONFIG			0x00
44*4882a593Smuzhiyun #define INA2XX_SHUNT_VOLTAGE		0x01 /* readonly */
45*4882a593Smuzhiyun #define INA2XX_BUS_VOLTAGE		0x02 /* readonly */
46*4882a593Smuzhiyun #define INA2XX_POWER			0x03 /* readonly */
47*4882a593Smuzhiyun #define INA2XX_CURRENT			0x04 /* readonly */
48*4882a593Smuzhiyun #define INA2XX_CALIBRATION		0x05
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /* INA226 register definitions */
51*4882a593Smuzhiyun #define INA226_MASK_ENABLE		0x06
52*4882a593Smuzhiyun #define INA226_ALERT_LIMIT		0x07
53*4882a593Smuzhiyun #define INA226_DIE_ID			0xFF
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun /* register count */
56*4882a593Smuzhiyun #define INA219_REGISTERS		6
57*4882a593Smuzhiyun #define INA226_REGISTERS		8
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define INA2XX_MAX_REGISTERS		8
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /* settings - depend on use case */
62*4882a593Smuzhiyun #define INA219_CONFIG_DEFAULT		0x399F	/* PGA=8 */
63*4882a593Smuzhiyun #define INA226_CONFIG_DEFAULT		0x4527	/* averages=16 */
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /* worst case is 68.10 ms (~14.6Hz, ina219) */
66*4882a593Smuzhiyun #define INA2XX_CONVERSION_RATE		15
67*4882a593Smuzhiyun #define INA2XX_MAX_DELAY		69 /* worst case delay in ms */
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define INA2XX_RSHUNT_DEFAULT		10000
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /* bit mask for reading the averaging setting in the configuration register */
72*4882a593Smuzhiyun #define INA226_AVG_RD_MASK		0x0E00
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define INA226_READ_AVG(reg)		(((reg) & INA226_AVG_RD_MASK) >> 9)
75*4882a593Smuzhiyun #define INA226_SHIFT_AVG(val)		((val) << 9)
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun /* bit number of alert functions in Mask/Enable Register */
78*4882a593Smuzhiyun #define INA226_SHUNT_OVER_VOLTAGE_BIT	15
79*4882a593Smuzhiyun #define INA226_SHUNT_UNDER_VOLTAGE_BIT	14
80*4882a593Smuzhiyun #define INA226_BUS_OVER_VOLTAGE_BIT	13
81*4882a593Smuzhiyun #define INA226_BUS_UNDER_VOLTAGE_BIT	12
82*4882a593Smuzhiyun #define INA226_POWER_OVER_LIMIT_BIT	11
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /* bit mask for alert config bits of Mask/Enable Register */
85*4882a593Smuzhiyun #define INA226_ALERT_CONFIG_MASK	0xFC00
86*4882a593Smuzhiyun #define INA226_ALERT_FUNCTION_FLAG	BIT(4)
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun /* common attrs, ina226 attrs and NULL */
89*4882a593Smuzhiyun #define INA2XX_MAX_ATTRIBUTE_GROUPS	3
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun /*
92*4882a593Smuzhiyun  * Both bus voltage and shunt voltage conversion times for ina226 are set
93*4882a593Smuzhiyun  * to 0b0100 on POR, which translates to 2200 microseconds in total.
94*4882a593Smuzhiyun  */
95*4882a593Smuzhiyun #define INA226_TOTAL_CONV_TIME_DEFAULT	2200
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun static struct regmap_config ina2xx_regmap_config = {
98*4882a593Smuzhiyun 	.reg_bits = 8,
99*4882a593Smuzhiyun 	.val_bits = 16,
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun enum ina2xx_ids { ina219, ina226 };
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun struct ina2xx_config {
105*4882a593Smuzhiyun 	u16 config_default;
106*4882a593Smuzhiyun 	int calibration_value;
107*4882a593Smuzhiyun 	int registers;
108*4882a593Smuzhiyun 	int shunt_div;
109*4882a593Smuzhiyun 	int bus_voltage_shift;
110*4882a593Smuzhiyun 	int bus_voltage_lsb;	/* uV */
111*4882a593Smuzhiyun 	int power_lsb_factor;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun struct ina2xx_data {
115*4882a593Smuzhiyun 	const struct ina2xx_config *config;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	long rshunt;
118*4882a593Smuzhiyun 	long current_lsb_uA;
119*4882a593Smuzhiyun 	long power_lsb_uW;
120*4882a593Smuzhiyun 	struct mutex config_lock;
121*4882a593Smuzhiyun 	struct regmap *regmap;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	const struct attribute_group *groups[INA2XX_MAX_ATTRIBUTE_GROUPS];
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun static const struct ina2xx_config ina2xx_config[] = {
127*4882a593Smuzhiyun 	[ina219] = {
128*4882a593Smuzhiyun 		.config_default = INA219_CONFIG_DEFAULT,
129*4882a593Smuzhiyun 		.calibration_value = 4096,
130*4882a593Smuzhiyun 		.registers = INA219_REGISTERS,
131*4882a593Smuzhiyun 		.shunt_div = 100,
132*4882a593Smuzhiyun 		.bus_voltage_shift = 3,
133*4882a593Smuzhiyun 		.bus_voltage_lsb = 4000,
134*4882a593Smuzhiyun 		.power_lsb_factor = 20,
135*4882a593Smuzhiyun 	},
136*4882a593Smuzhiyun 	[ina226] = {
137*4882a593Smuzhiyun 		.config_default = INA226_CONFIG_DEFAULT,
138*4882a593Smuzhiyun 		.calibration_value = 2048,
139*4882a593Smuzhiyun 		.registers = INA226_REGISTERS,
140*4882a593Smuzhiyun 		.shunt_div = 400,
141*4882a593Smuzhiyun 		.bus_voltage_shift = 0,
142*4882a593Smuzhiyun 		.bus_voltage_lsb = 1250,
143*4882a593Smuzhiyun 		.power_lsb_factor = 25,
144*4882a593Smuzhiyun 	},
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun /*
148*4882a593Smuzhiyun  * Available averaging rates for ina226. The indices correspond with
149*4882a593Smuzhiyun  * the bit values expected by the chip (according to the ina226 datasheet,
150*4882a593Smuzhiyun  * table 3 AVG bit settings, found at
151*4882a593Smuzhiyun  * https://www.ti.com/lit/ds/symlink/ina226.pdf.
152*4882a593Smuzhiyun  */
153*4882a593Smuzhiyun static const int ina226_avg_tab[] = { 1, 4, 16, 64, 128, 256, 512, 1024 };
154*4882a593Smuzhiyun 
ina226_reg_to_interval(u16 config)155*4882a593Smuzhiyun static int ina226_reg_to_interval(u16 config)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	int avg = ina226_avg_tab[INA226_READ_AVG(config)];
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	/*
160*4882a593Smuzhiyun 	 * Multiply the total conversion time by the number of averages.
161*4882a593Smuzhiyun 	 * Return the result in milliseconds.
162*4882a593Smuzhiyun 	 */
163*4882a593Smuzhiyun 	return DIV_ROUND_CLOSEST(avg * INA226_TOTAL_CONV_TIME_DEFAULT, 1000);
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun /*
167*4882a593Smuzhiyun  * Return the new, shifted AVG field value of CONFIG register,
168*4882a593Smuzhiyun  * to use with regmap_update_bits
169*4882a593Smuzhiyun  */
ina226_interval_to_reg(int interval)170*4882a593Smuzhiyun static u16 ina226_interval_to_reg(int interval)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun 	int avg, avg_bits;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	avg = DIV_ROUND_CLOSEST(interval * 1000,
175*4882a593Smuzhiyun 				INA226_TOTAL_CONV_TIME_DEFAULT);
176*4882a593Smuzhiyun 	avg_bits = find_closest(avg, ina226_avg_tab,
177*4882a593Smuzhiyun 				ARRAY_SIZE(ina226_avg_tab));
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	return INA226_SHIFT_AVG(avg_bits);
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun /*
183*4882a593Smuzhiyun  * Calibration register is set to the best value, which eliminates
184*4882a593Smuzhiyun  * truncation errors on calculating current register in hardware.
185*4882a593Smuzhiyun  * According to datasheet (eq. 3) the best values are 2048 for
186*4882a593Smuzhiyun  * ina226 and 4096 for ina219. They are hardcoded as calibration_value.
187*4882a593Smuzhiyun  */
ina2xx_calibrate(struct ina2xx_data * data)188*4882a593Smuzhiyun static int ina2xx_calibrate(struct ina2xx_data *data)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	return regmap_write(data->regmap, INA2XX_CALIBRATION,
191*4882a593Smuzhiyun 			    data->config->calibration_value);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun /*
195*4882a593Smuzhiyun  * Initialize the configuration and calibration registers.
196*4882a593Smuzhiyun  */
ina2xx_init(struct ina2xx_data * data)197*4882a593Smuzhiyun static int ina2xx_init(struct ina2xx_data *data)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun 	int ret = regmap_write(data->regmap, INA2XX_CONFIG,
200*4882a593Smuzhiyun 			       data->config->config_default);
201*4882a593Smuzhiyun 	if (ret < 0)
202*4882a593Smuzhiyun 		return ret;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	return ina2xx_calibrate(data);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun 
ina2xx_read_reg(struct device * dev,int reg,unsigned int * regval)207*4882a593Smuzhiyun static int ina2xx_read_reg(struct device *dev, int reg, unsigned int *regval)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun 	struct ina2xx_data *data = dev_get_drvdata(dev);
210*4882a593Smuzhiyun 	int ret, retry;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	dev_dbg(dev, "Starting register %d read\n", reg);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	for (retry = 5; retry; retry--) {
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 		ret = regmap_read(data->regmap, reg, regval);
217*4882a593Smuzhiyun 		if (ret < 0)
218*4882a593Smuzhiyun 			return ret;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 		dev_dbg(dev, "read %d, val = 0x%04x\n", reg, *regval);
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 		/*
223*4882a593Smuzhiyun 		 * If the current value in the calibration register is 0, the
224*4882a593Smuzhiyun 		 * power and current registers will also remain at 0. In case
225*4882a593Smuzhiyun 		 * the chip has been reset let's check the calibration
226*4882a593Smuzhiyun 		 * register and reinitialize if needed.
227*4882a593Smuzhiyun 		 * We do that extra read of the calibration register if there
228*4882a593Smuzhiyun 		 * is some hint of a chip reset.
229*4882a593Smuzhiyun 		 */
230*4882a593Smuzhiyun 		if (*regval == 0) {
231*4882a593Smuzhiyun 			unsigned int cal;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 			ret = regmap_read(data->regmap, INA2XX_CALIBRATION,
234*4882a593Smuzhiyun 					  &cal);
235*4882a593Smuzhiyun 			if (ret < 0)
236*4882a593Smuzhiyun 				return ret;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 			if (cal == 0) {
239*4882a593Smuzhiyun 				dev_warn(dev, "chip not calibrated, reinitializing\n");
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 				ret = ina2xx_init(data);
242*4882a593Smuzhiyun 				if (ret < 0)
243*4882a593Smuzhiyun 					return ret;
244*4882a593Smuzhiyun 				/*
245*4882a593Smuzhiyun 				 * Let's make sure the power and current
246*4882a593Smuzhiyun 				 * registers have been updated before trying
247*4882a593Smuzhiyun 				 * again.
248*4882a593Smuzhiyun 				 */
249*4882a593Smuzhiyun 				msleep(INA2XX_MAX_DELAY);
250*4882a593Smuzhiyun 				continue;
251*4882a593Smuzhiyun 			}
252*4882a593Smuzhiyun 		}
253*4882a593Smuzhiyun 		return 0;
254*4882a593Smuzhiyun 	}
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	/*
257*4882a593Smuzhiyun 	 * If we're here then although all write operations succeeded, the
258*4882a593Smuzhiyun 	 * chip still returns 0 in the calibration register. Nothing more we
259*4882a593Smuzhiyun 	 * can do here.
260*4882a593Smuzhiyun 	 */
261*4882a593Smuzhiyun 	dev_err(dev, "unable to reinitialize the chip\n");
262*4882a593Smuzhiyun 	return -ENODEV;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun 
ina2xx_get_value(struct ina2xx_data * data,u8 reg,unsigned int regval)265*4882a593Smuzhiyun static int ina2xx_get_value(struct ina2xx_data *data, u8 reg,
266*4882a593Smuzhiyun 			    unsigned int regval)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun 	int val;
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	switch (reg) {
271*4882a593Smuzhiyun 	case INA2XX_SHUNT_VOLTAGE:
272*4882a593Smuzhiyun 		/* signed register */
273*4882a593Smuzhiyun 		val = DIV_ROUND_CLOSEST((s16)regval, data->config->shunt_div);
274*4882a593Smuzhiyun 		break;
275*4882a593Smuzhiyun 	case INA2XX_BUS_VOLTAGE:
276*4882a593Smuzhiyun 		val = (regval >> data->config->bus_voltage_shift)
277*4882a593Smuzhiyun 		  * data->config->bus_voltage_lsb;
278*4882a593Smuzhiyun 		val = DIV_ROUND_CLOSEST(val, 1000);
279*4882a593Smuzhiyun 		break;
280*4882a593Smuzhiyun 	case INA2XX_POWER:
281*4882a593Smuzhiyun 		val = regval * data->power_lsb_uW;
282*4882a593Smuzhiyun 		break;
283*4882a593Smuzhiyun 	case INA2XX_CURRENT:
284*4882a593Smuzhiyun 		/* signed register, result in mA */
285*4882a593Smuzhiyun 		val = (s16)regval * data->current_lsb_uA;
286*4882a593Smuzhiyun 		val = DIV_ROUND_CLOSEST(val, 1000);
287*4882a593Smuzhiyun 		break;
288*4882a593Smuzhiyun 	case INA2XX_CALIBRATION:
289*4882a593Smuzhiyun 		val = regval;
290*4882a593Smuzhiyun 		break;
291*4882a593Smuzhiyun 	default:
292*4882a593Smuzhiyun 		/* programmer goofed */
293*4882a593Smuzhiyun 		WARN_ON_ONCE(1);
294*4882a593Smuzhiyun 		val = 0;
295*4882a593Smuzhiyun 		break;
296*4882a593Smuzhiyun 	}
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	return val;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun 
ina2xx_value_show(struct device * dev,struct device_attribute * da,char * buf)301*4882a593Smuzhiyun static ssize_t ina2xx_value_show(struct device *dev,
302*4882a593Smuzhiyun 				 struct device_attribute *da, char *buf)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun 	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
305*4882a593Smuzhiyun 	struct ina2xx_data *data = dev_get_drvdata(dev);
306*4882a593Smuzhiyun 	unsigned int regval;
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	int err = ina2xx_read_reg(dev, attr->index, &regval);
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	if (err < 0)
311*4882a593Smuzhiyun 		return err;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	return snprintf(buf, PAGE_SIZE, "%d\n",
314*4882a593Smuzhiyun 			ina2xx_get_value(data, attr->index, regval));
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun 
ina226_reg_to_alert(struct ina2xx_data * data,u8 bit,u16 regval)317*4882a593Smuzhiyun static int ina226_reg_to_alert(struct ina2xx_data *data, u8 bit, u16 regval)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun 	int reg;
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	switch (bit) {
322*4882a593Smuzhiyun 	case INA226_SHUNT_OVER_VOLTAGE_BIT:
323*4882a593Smuzhiyun 	case INA226_SHUNT_UNDER_VOLTAGE_BIT:
324*4882a593Smuzhiyun 		reg = INA2XX_SHUNT_VOLTAGE;
325*4882a593Smuzhiyun 		break;
326*4882a593Smuzhiyun 	case INA226_BUS_OVER_VOLTAGE_BIT:
327*4882a593Smuzhiyun 	case INA226_BUS_UNDER_VOLTAGE_BIT:
328*4882a593Smuzhiyun 		reg = INA2XX_BUS_VOLTAGE;
329*4882a593Smuzhiyun 		break;
330*4882a593Smuzhiyun 	case INA226_POWER_OVER_LIMIT_BIT:
331*4882a593Smuzhiyun 		reg = INA2XX_POWER;
332*4882a593Smuzhiyun 		break;
333*4882a593Smuzhiyun 	default:
334*4882a593Smuzhiyun 		/* programmer goofed */
335*4882a593Smuzhiyun 		WARN_ON_ONCE(1);
336*4882a593Smuzhiyun 		return 0;
337*4882a593Smuzhiyun 	}
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	return ina2xx_get_value(data, reg, regval);
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun /*
343*4882a593Smuzhiyun  * Turns alert limit values into register values.
344*4882a593Smuzhiyun  * Opposite of the formula in ina2xx_get_value().
345*4882a593Smuzhiyun  */
ina226_alert_to_reg(struct ina2xx_data * data,u8 bit,int val)346*4882a593Smuzhiyun static s16 ina226_alert_to_reg(struct ina2xx_data *data, u8 bit, int val)
347*4882a593Smuzhiyun {
348*4882a593Smuzhiyun 	switch (bit) {
349*4882a593Smuzhiyun 	case INA226_SHUNT_OVER_VOLTAGE_BIT:
350*4882a593Smuzhiyun 	case INA226_SHUNT_UNDER_VOLTAGE_BIT:
351*4882a593Smuzhiyun 		val *= data->config->shunt_div;
352*4882a593Smuzhiyun 		return clamp_val(val, SHRT_MIN, SHRT_MAX);
353*4882a593Smuzhiyun 	case INA226_BUS_OVER_VOLTAGE_BIT:
354*4882a593Smuzhiyun 	case INA226_BUS_UNDER_VOLTAGE_BIT:
355*4882a593Smuzhiyun 		val = (val * 1000) << data->config->bus_voltage_shift;
356*4882a593Smuzhiyun 		val = DIV_ROUND_CLOSEST(val, data->config->bus_voltage_lsb);
357*4882a593Smuzhiyun 		return clamp_val(val, 0, SHRT_MAX);
358*4882a593Smuzhiyun 	case INA226_POWER_OVER_LIMIT_BIT:
359*4882a593Smuzhiyun 		val = DIV_ROUND_CLOSEST(val, data->power_lsb_uW);
360*4882a593Smuzhiyun 		return clamp_val(val, 0, USHRT_MAX);
361*4882a593Smuzhiyun 	default:
362*4882a593Smuzhiyun 		/* programmer goofed */
363*4882a593Smuzhiyun 		WARN_ON_ONCE(1);
364*4882a593Smuzhiyun 		return 0;
365*4882a593Smuzhiyun 	}
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun 
ina226_alert_show(struct device * dev,struct device_attribute * da,char * buf)368*4882a593Smuzhiyun static ssize_t ina226_alert_show(struct device *dev,
369*4882a593Smuzhiyun 				 struct device_attribute *da, char *buf)
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun 	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
372*4882a593Smuzhiyun 	struct ina2xx_data *data = dev_get_drvdata(dev);
373*4882a593Smuzhiyun 	int regval;
374*4882a593Smuzhiyun 	int val = 0;
375*4882a593Smuzhiyun 	int ret;
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	mutex_lock(&data->config_lock);
378*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, INA226_MASK_ENABLE, &regval);
379*4882a593Smuzhiyun 	if (ret)
380*4882a593Smuzhiyun 		goto abort;
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	if (regval & BIT(attr->index)) {
383*4882a593Smuzhiyun 		ret = regmap_read(data->regmap, INA226_ALERT_LIMIT, &regval);
384*4882a593Smuzhiyun 		if (ret)
385*4882a593Smuzhiyun 			goto abort;
386*4882a593Smuzhiyun 		val = ina226_reg_to_alert(data, attr->index, regval);
387*4882a593Smuzhiyun 	}
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	ret = snprintf(buf, PAGE_SIZE, "%d\n", val);
390*4882a593Smuzhiyun abort:
391*4882a593Smuzhiyun 	mutex_unlock(&data->config_lock);
392*4882a593Smuzhiyun 	return ret;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun 
ina226_alert_store(struct device * dev,struct device_attribute * da,const char * buf,size_t count)395*4882a593Smuzhiyun static ssize_t ina226_alert_store(struct device *dev,
396*4882a593Smuzhiyun 				  struct device_attribute *da,
397*4882a593Smuzhiyun 				  const char *buf, size_t count)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun 	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
400*4882a593Smuzhiyun 	struct ina2xx_data *data = dev_get_drvdata(dev);
401*4882a593Smuzhiyun 	unsigned long val;
402*4882a593Smuzhiyun 	int ret;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	ret = kstrtoul(buf, 10, &val);
405*4882a593Smuzhiyun 	if (ret < 0)
406*4882a593Smuzhiyun 		return ret;
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	/*
409*4882a593Smuzhiyun 	 * Clear all alerts first to avoid accidentally triggering ALERT pin
410*4882a593Smuzhiyun 	 * due to register write sequence. Then, only enable the alert
411*4882a593Smuzhiyun 	 * if the value is non-zero.
412*4882a593Smuzhiyun 	 */
413*4882a593Smuzhiyun 	mutex_lock(&data->config_lock);
414*4882a593Smuzhiyun 	ret = regmap_update_bits(data->regmap, INA226_MASK_ENABLE,
415*4882a593Smuzhiyun 				 INA226_ALERT_CONFIG_MASK, 0);
416*4882a593Smuzhiyun 	if (ret < 0)
417*4882a593Smuzhiyun 		goto abort;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	ret = regmap_write(data->regmap, INA226_ALERT_LIMIT,
420*4882a593Smuzhiyun 			   ina226_alert_to_reg(data, attr->index, val));
421*4882a593Smuzhiyun 	if (ret < 0)
422*4882a593Smuzhiyun 		goto abort;
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	if (val != 0) {
425*4882a593Smuzhiyun 		ret = regmap_update_bits(data->regmap, INA226_MASK_ENABLE,
426*4882a593Smuzhiyun 					 INA226_ALERT_CONFIG_MASK,
427*4882a593Smuzhiyun 					 BIT(attr->index));
428*4882a593Smuzhiyun 		if (ret < 0)
429*4882a593Smuzhiyun 			goto abort;
430*4882a593Smuzhiyun 	}
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	ret = count;
433*4882a593Smuzhiyun abort:
434*4882a593Smuzhiyun 	mutex_unlock(&data->config_lock);
435*4882a593Smuzhiyun 	return ret;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun 
ina226_alarm_show(struct device * dev,struct device_attribute * da,char * buf)438*4882a593Smuzhiyun static ssize_t ina226_alarm_show(struct device *dev,
439*4882a593Smuzhiyun 				 struct device_attribute *da, char *buf)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun 	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
442*4882a593Smuzhiyun 	struct ina2xx_data *data = dev_get_drvdata(dev);
443*4882a593Smuzhiyun 	int regval;
444*4882a593Smuzhiyun 	int alarm = 0;
445*4882a593Smuzhiyun 	int ret;
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, INA226_MASK_ENABLE, &regval);
448*4882a593Smuzhiyun 	if (ret)
449*4882a593Smuzhiyun 		return ret;
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	alarm = (regval & BIT(attr->index)) &&
452*4882a593Smuzhiyun 		(regval & INA226_ALERT_FUNCTION_FLAG);
453*4882a593Smuzhiyun 	return snprintf(buf, PAGE_SIZE, "%d\n", alarm);
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun /*
457*4882a593Smuzhiyun  * In order to keep calibration register value fixed, the product
458*4882a593Smuzhiyun  * of current_lsb and shunt_resistor should also be fixed and equal
459*4882a593Smuzhiyun  * to shunt_voltage_lsb = 1 / shunt_div multiplied by 10^9 in order
460*4882a593Smuzhiyun  * to keep the scale.
461*4882a593Smuzhiyun  */
ina2xx_set_shunt(struct ina2xx_data * data,long val)462*4882a593Smuzhiyun static int ina2xx_set_shunt(struct ina2xx_data *data, long val)
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun 	unsigned int dividend = DIV_ROUND_CLOSEST(1000000000,
465*4882a593Smuzhiyun 						  data->config->shunt_div);
466*4882a593Smuzhiyun 	if (val <= 0 || val > dividend)
467*4882a593Smuzhiyun 		return -EINVAL;
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	mutex_lock(&data->config_lock);
470*4882a593Smuzhiyun 	data->rshunt = val;
471*4882a593Smuzhiyun 	data->current_lsb_uA = DIV_ROUND_CLOSEST(dividend, val);
472*4882a593Smuzhiyun 	data->power_lsb_uW = data->config->power_lsb_factor *
473*4882a593Smuzhiyun 			     data->current_lsb_uA;
474*4882a593Smuzhiyun 	mutex_unlock(&data->config_lock);
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	return 0;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun 
ina2xx_shunt_show(struct device * dev,struct device_attribute * da,char * buf)479*4882a593Smuzhiyun static ssize_t ina2xx_shunt_show(struct device *dev,
480*4882a593Smuzhiyun 				 struct device_attribute *da, char *buf)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun 	struct ina2xx_data *data = dev_get_drvdata(dev);
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	return snprintf(buf, PAGE_SIZE, "%li\n", data->rshunt);
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun 
ina2xx_shunt_store(struct device * dev,struct device_attribute * da,const char * buf,size_t count)487*4882a593Smuzhiyun static ssize_t ina2xx_shunt_store(struct device *dev,
488*4882a593Smuzhiyun 				  struct device_attribute *da,
489*4882a593Smuzhiyun 				  const char *buf, size_t count)
490*4882a593Smuzhiyun {
491*4882a593Smuzhiyun 	unsigned long val;
492*4882a593Smuzhiyun 	int status;
493*4882a593Smuzhiyun 	struct ina2xx_data *data = dev_get_drvdata(dev);
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	status = kstrtoul(buf, 10, &val);
496*4882a593Smuzhiyun 	if (status < 0)
497*4882a593Smuzhiyun 		return status;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	status = ina2xx_set_shunt(data, val);
500*4882a593Smuzhiyun 	if (status < 0)
501*4882a593Smuzhiyun 		return status;
502*4882a593Smuzhiyun 	return count;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun 
ina226_interval_store(struct device * dev,struct device_attribute * da,const char * buf,size_t count)505*4882a593Smuzhiyun static ssize_t ina226_interval_store(struct device *dev,
506*4882a593Smuzhiyun 				     struct device_attribute *da,
507*4882a593Smuzhiyun 				     const char *buf, size_t count)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun 	struct ina2xx_data *data = dev_get_drvdata(dev);
510*4882a593Smuzhiyun 	unsigned long val;
511*4882a593Smuzhiyun 	int status;
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun 	status = kstrtoul(buf, 10, &val);
514*4882a593Smuzhiyun 	if (status < 0)
515*4882a593Smuzhiyun 		return status;
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun 	if (val > INT_MAX || val == 0)
518*4882a593Smuzhiyun 		return -EINVAL;
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	status = regmap_update_bits(data->regmap, INA2XX_CONFIG,
521*4882a593Smuzhiyun 				    INA226_AVG_RD_MASK,
522*4882a593Smuzhiyun 				    ina226_interval_to_reg(val));
523*4882a593Smuzhiyun 	if (status < 0)
524*4882a593Smuzhiyun 		return status;
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun 	return count;
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun 
ina226_interval_show(struct device * dev,struct device_attribute * da,char * buf)529*4882a593Smuzhiyun static ssize_t ina226_interval_show(struct device *dev,
530*4882a593Smuzhiyun 				    struct device_attribute *da, char *buf)
531*4882a593Smuzhiyun {
532*4882a593Smuzhiyun 	struct ina2xx_data *data = dev_get_drvdata(dev);
533*4882a593Smuzhiyun 	int status;
534*4882a593Smuzhiyun 	unsigned int regval;
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	status = regmap_read(data->regmap, INA2XX_CONFIG, &regval);
537*4882a593Smuzhiyun 	if (status)
538*4882a593Smuzhiyun 		return status;
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	return snprintf(buf, PAGE_SIZE, "%d\n", ina226_reg_to_interval(regval));
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun /* shunt voltage */
544*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in0_input, ina2xx_value, INA2XX_SHUNT_VOLTAGE);
545*4882a593Smuzhiyun /* shunt voltage over/under voltage alert setting and alarm */
546*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RW(in0_crit, ina226_alert,
547*4882a593Smuzhiyun 			     INA226_SHUNT_OVER_VOLTAGE_BIT);
548*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RW(in0_lcrit, ina226_alert,
549*4882a593Smuzhiyun 			     INA226_SHUNT_UNDER_VOLTAGE_BIT);
550*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in0_crit_alarm, ina226_alarm,
551*4882a593Smuzhiyun 			     INA226_SHUNT_OVER_VOLTAGE_BIT);
552*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in0_lcrit_alarm, ina226_alarm,
553*4882a593Smuzhiyun 			     INA226_SHUNT_UNDER_VOLTAGE_BIT);
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun /* bus voltage */
556*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in1_input, ina2xx_value, INA2XX_BUS_VOLTAGE);
557*4882a593Smuzhiyun /* bus voltage over/under voltage alert setting and alarm */
558*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RW(in1_crit, ina226_alert,
559*4882a593Smuzhiyun 			     INA226_BUS_OVER_VOLTAGE_BIT);
560*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RW(in1_lcrit, ina226_alert,
561*4882a593Smuzhiyun 			     INA226_BUS_UNDER_VOLTAGE_BIT);
562*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in1_crit_alarm, ina226_alarm,
563*4882a593Smuzhiyun 			     INA226_BUS_OVER_VOLTAGE_BIT);
564*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in1_lcrit_alarm, ina226_alarm,
565*4882a593Smuzhiyun 			     INA226_BUS_UNDER_VOLTAGE_BIT);
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun /* calculated current */
568*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(curr1_input, ina2xx_value, INA2XX_CURRENT);
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun /* calculated power */
571*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(power1_input, ina2xx_value, INA2XX_POWER);
572*4882a593Smuzhiyun /* over-limit power alert setting and alarm */
573*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RW(power1_crit, ina226_alert,
574*4882a593Smuzhiyun 			     INA226_POWER_OVER_LIMIT_BIT);
575*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(power1_crit_alarm, ina226_alarm,
576*4882a593Smuzhiyun 			     INA226_POWER_OVER_LIMIT_BIT);
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun /* shunt resistance */
579*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RW(shunt_resistor, ina2xx_shunt, INA2XX_CALIBRATION);
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun /* update interval (ina226 only) */
582*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RW(update_interval, ina226_interval, 0);
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun /* pointers to created device attributes */
585*4882a593Smuzhiyun static struct attribute *ina2xx_attrs[] = {
586*4882a593Smuzhiyun 	&sensor_dev_attr_in0_input.dev_attr.attr,
587*4882a593Smuzhiyun 	&sensor_dev_attr_in1_input.dev_attr.attr,
588*4882a593Smuzhiyun 	&sensor_dev_attr_curr1_input.dev_attr.attr,
589*4882a593Smuzhiyun 	&sensor_dev_attr_power1_input.dev_attr.attr,
590*4882a593Smuzhiyun 	&sensor_dev_attr_shunt_resistor.dev_attr.attr,
591*4882a593Smuzhiyun 	NULL,
592*4882a593Smuzhiyun };
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun static const struct attribute_group ina2xx_group = {
595*4882a593Smuzhiyun 	.attrs = ina2xx_attrs,
596*4882a593Smuzhiyun };
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun static struct attribute *ina226_attrs[] = {
599*4882a593Smuzhiyun 	&sensor_dev_attr_in0_crit.dev_attr.attr,
600*4882a593Smuzhiyun 	&sensor_dev_attr_in0_lcrit.dev_attr.attr,
601*4882a593Smuzhiyun 	&sensor_dev_attr_in0_crit_alarm.dev_attr.attr,
602*4882a593Smuzhiyun 	&sensor_dev_attr_in0_lcrit_alarm.dev_attr.attr,
603*4882a593Smuzhiyun 	&sensor_dev_attr_in1_crit.dev_attr.attr,
604*4882a593Smuzhiyun 	&sensor_dev_attr_in1_lcrit.dev_attr.attr,
605*4882a593Smuzhiyun 	&sensor_dev_attr_in1_crit_alarm.dev_attr.attr,
606*4882a593Smuzhiyun 	&sensor_dev_attr_in1_lcrit_alarm.dev_attr.attr,
607*4882a593Smuzhiyun 	&sensor_dev_attr_power1_crit.dev_attr.attr,
608*4882a593Smuzhiyun 	&sensor_dev_attr_power1_crit_alarm.dev_attr.attr,
609*4882a593Smuzhiyun 	&sensor_dev_attr_update_interval.dev_attr.attr,
610*4882a593Smuzhiyun 	NULL,
611*4882a593Smuzhiyun };
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun static const struct attribute_group ina226_group = {
614*4882a593Smuzhiyun 	.attrs = ina226_attrs,
615*4882a593Smuzhiyun };
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun static const struct i2c_device_id ina2xx_id[];
618*4882a593Smuzhiyun 
ina2xx_probe(struct i2c_client * client)619*4882a593Smuzhiyun static int ina2xx_probe(struct i2c_client *client)
620*4882a593Smuzhiyun {
621*4882a593Smuzhiyun 	struct device *dev = &client->dev;
622*4882a593Smuzhiyun 	struct ina2xx_data *data;
623*4882a593Smuzhiyun 	struct device *hwmon_dev;
624*4882a593Smuzhiyun 	u32 val;
625*4882a593Smuzhiyun 	int ret, group = 0;
626*4882a593Smuzhiyun 	enum ina2xx_ids chip;
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 	if (client->dev.of_node)
629*4882a593Smuzhiyun 		chip = (enum ina2xx_ids)of_device_get_match_data(&client->dev);
630*4882a593Smuzhiyun 	else
631*4882a593Smuzhiyun 		chip = i2c_match_id(ina2xx_id, client)->driver_data;
632*4882a593Smuzhiyun 
633*4882a593Smuzhiyun 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
634*4882a593Smuzhiyun 	if (!data)
635*4882a593Smuzhiyun 		return -ENOMEM;
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	/* set the device type */
638*4882a593Smuzhiyun 	data->config = &ina2xx_config[chip];
639*4882a593Smuzhiyun 	mutex_init(&data->config_lock);
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	if (of_property_read_u32(dev->of_node, "shunt-resistor", &val) < 0) {
642*4882a593Smuzhiyun 		struct ina2xx_platform_data *pdata = dev_get_platdata(dev);
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun 		if (pdata)
645*4882a593Smuzhiyun 			val = pdata->shunt_uohms;
646*4882a593Smuzhiyun 		else
647*4882a593Smuzhiyun 			val = INA2XX_RSHUNT_DEFAULT;
648*4882a593Smuzhiyun 	}
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 	ina2xx_set_shunt(data, val);
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun 	ina2xx_regmap_config.max_register = data->config->registers;
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	data->regmap = devm_regmap_init_i2c(client, &ina2xx_regmap_config);
655*4882a593Smuzhiyun 	if (IS_ERR(data->regmap)) {
656*4882a593Smuzhiyun 		dev_err(dev, "failed to allocate register map\n");
657*4882a593Smuzhiyun 		return PTR_ERR(data->regmap);
658*4882a593Smuzhiyun 	}
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	ret = ina2xx_init(data);
661*4882a593Smuzhiyun 	if (ret < 0) {
662*4882a593Smuzhiyun 		dev_err(dev, "error configuring the device: %d\n", ret);
663*4882a593Smuzhiyun 		return -ENODEV;
664*4882a593Smuzhiyun 	}
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	data->groups[group++] = &ina2xx_group;
667*4882a593Smuzhiyun 	if (chip == ina226)
668*4882a593Smuzhiyun 		data->groups[group++] = &ina226_group;
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 	hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
671*4882a593Smuzhiyun 							   data, data->groups);
672*4882a593Smuzhiyun 	if (IS_ERR(hwmon_dev))
673*4882a593Smuzhiyun 		return PTR_ERR(hwmon_dev);
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun 	dev_info(dev, "power monitor %s (Rshunt = %li uOhm)\n",
676*4882a593Smuzhiyun 		 client->name, data->rshunt);
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun 	return 0;
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun static const struct i2c_device_id ina2xx_id[] = {
682*4882a593Smuzhiyun 	{ "ina219", ina219 },
683*4882a593Smuzhiyun 	{ "ina220", ina219 },
684*4882a593Smuzhiyun 	{ "ina226", ina226 },
685*4882a593Smuzhiyun 	{ "ina230", ina226 },
686*4882a593Smuzhiyun 	{ "ina231", ina226 },
687*4882a593Smuzhiyun 	{ }
688*4882a593Smuzhiyun };
689*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ina2xx_id);
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun static const struct of_device_id __maybe_unused ina2xx_of_match[] = {
692*4882a593Smuzhiyun 	{
693*4882a593Smuzhiyun 		.compatible = "ti,ina219",
694*4882a593Smuzhiyun 		.data = (void *)ina219
695*4882a593Smuzhiyun 	},
696*4882a593Smuzhiyun 	{
697*4882a593Smuzhiyun 		.compatible = "ti,ina220",
698*4882a593Smuzhiyun 		.data = (void *)ina219
699*4882a593Smuzhiyun 	},
700*4882a593Smuzhiyun 	{
701*4882a593Smuzhiyun 		.compatible = "ti,ina226",
702*4882a593Smuzhiyun 		.data = (void *)ina226
703*4882a593Smuzhiyun 	},
704*4882a593Smuzhiyun 	{
705*4882a593Smuzhiyun 		.compatible = "ti,ina230",
706*4882a593Smuzhiyun 		.data = (void *)ina226
707*4882a593Smuzhiyun 	},
708*4882a593Smuzhiyun 	{
709*4882a593Smuzhiyun 		.compatible = "ti,ina231",
710*4882a593Smuzhiyun 		.data = (void *)ina226
711*4882a593Smuzhiyun 	},
712*4882a593Smuzhiyun 	{ },
713*4882a593Smuzhiyun };
714*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ina2xx_of_match);
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun static struct i2c_driver ina2xx_driver = {
717*4882a593Smuzhiyun 	.driver = {
718*4882a593Smuzhiyun 		.name	= "ina2xx",
719*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(ina2xx_of_match),
720*4882a593Smuzhiyun 	},
721*4882a593Smuzhiyun 	.probe_new	= ina2xx_probe,
722*4882a593Smuzhiyun 	.id_table	= ina2xx_id,
723*4882a593Smuzhiyun };
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun module_i2c_driver(ina2xx_driver);
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun MODULE_AUTHOR("Lothar Felten <l-felten@ti.com>");
728*4882a593Smuzhiyun MODULE_DESCRIPTION("ina2xx driver");
729*4882a593Smuzhiyun MODULE_LICENSE("GPL");
730