xref: /OK3568_Linux_fs/kernel/drivers/hwmon/ads7871.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  ads7871 - driver for TI ADS7871 A/D converter
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (c) 2010 Paul Thomas <pthomas8589@gmail.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *	You need to have something like this in struct spi_board_info
8*4882a593Smuzhiyun  *	{
9*4882a593Smuzhiyun  *		.modalias	= "ads7871",
10*4882a593Smuzhiyun  *		.max_speed_hz	= 2*1000*1000,
11*4882a593Smuzhiyun  *		.chip_select	= 0,
12*4882a593Smuzhiyun  *		.bus_num	= 1,
13*4882a593Smuzhiyun  *	},
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /*From figure 18 in the datasheet*/
17*4882a593Smuzhiyun /*Register addresses*/
18*4882a593Smuzhiyun #define REG_LS_BYTE	0 /*A/D Output Data, LS Byte*/
19*4882a593Smuzhiyun #define REG_MS_BYTE	1 /*A/D Output Data, MS Byte*/
20*4882a593Smuzhiyun #define REG_PGA_VALID	2 /*PGA Valid Register*/
21*4882a593Smuzhiyun #define REG_AD_CONTROL	3 /*A/D Control Register*/
22*4882a593Smuzhiyun #define REG_GAIN_MUX	4 /*Gain/Mux Register*/
23*4882a593Smuzhiyun #define REG_IO_STATE	5 /*Digital I/O State Register*/
24*4882a593Smuzhiyun #define REG_IO_CONTROL	6 /*Digital I/O Control Register*/
25*4882a593Smuzhiyun #define REG_OSC_CONTROL	7 /*Rev/Oscillator Control Register*/
26*4882a593Smuzhiyun #define REG_SER_CONTROL 24 /*Serial Interface Control Register*/
27*4882a593Smuzhiyun #define REG_ID		31 /*ID Register*/
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun  * From figure 17 in the datasheet
31*4882a593Smuzhiyun  * These bits get ORed with the address to form
32*4882a593Smuzhiyun  * the instruction byte
33*4882a593Smuzhiyun  */
34*4882a593Smuzhiyun /*Instruction Bit masks*/
35*4882a593Smuzhiyun #define INST_MODE_BM	(1 << 7)
36*4882a593Smuzhiyun #define INST_READ_BM	(1 << 6)
37*4882a593Smuzhiyun #define INST_16BIT_BM	(1 << 5)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /*From figure 18 in the datasheet*/
40*4882a593Smuzhiyun /*bit masks for Rev/Oscillator Control Register*/
41*4882a593Smuzhiyun #define MUX_CNV_BV	7
42*4882a593Smuzhiyun #define MUX_CNV_BM	(1 << MUX_CNV_BV)
43*4882a593Smuzhiyun #define MUX_M3_BM	(1 << 3) /*M3 selects single ended*/
44*4882a593Smuzhiyun #define MUX_G_BV	4 /*allows for reg = (gain << MUX_G_BV) | ...*/
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /*From figure 18 in the datasheet*/
47*4882a593Smuzhiyun /*bit masks for Rev/Oscillator Control Register*/
48*4882a593Smuzhiyun #define OSC_OSCR_BM	(1 << 5)
49*4882a593Smuzhiyun #define OSC_OSCE_BM	(1 << 4)
50*4882a593Smuzhiyun #define OSC_REFE_BM	(1 << 3)
51*4882a593Smuzhiyun #define OSC_BUFE_BM	(1 << 2)
52*4882a593Smuzhiyun #define OSC_R2V_BM	(1 << 1)
53*4882a593Smuzhiyun #define OSC_RBG_BM	(1 << 0)
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #include <linux/module.h>
56*4882a593Smuzhiyun #include <linux/init.h>
57*4882a593Smuzhiyun #include <linux/spi/spi.h>
58*4882a593Smuzhiyun #include <linux/hwmon.h>
59*4882a593Smuzhiyun #include <linux/hwmon-sysfs.h>
60*4882a593Smuzhiyun #include <linux/err.h>
61*4882a593Smuzhiyun #include <linux/delay.h>
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #define DEVICE_NAME	"ads7871"
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun struct ads7871_data {
66*4882a593Smuzhiyun 	struct spi_device *spi;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
ads7871_read_reg8(struct spi_device * spi,int reg)69*4882a593Smuzhiyun static int ads7871_read_reg8(struct spi_device *spi, int reg)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	int ret;
72*4882a593Smuzhiyun 	reg = reg | INST_READ_BM;
73*4882a593Smuzhiyun 	ret = spi_w8r8(spi, reg);
74*4882a593Smuzhiyun 	return ret;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun 
ads7871_read_reg16(struct spi_device * spi,int reg)77*4882a593Smuzhiyun static int ads7871_read_reg16(struct spi_device *spi, int reg)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun 	int ret;
80*4882a593Smuzhiyun 	reg = reg | INST_READ_BM | INST_16BIT_BM;
81*4882a593Smuzhiyun 	ret = spi_w8r16(spi, reg);
82*4882a593Smuzhiyun 	return ret;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun 
ads7871_write_reg8(struct spi_device * spi,int reg,u8 val)85*4882a593Smuzhiyun static int ads7871_write_reg8(struct spi_device *spi, int reg, u8 val)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	u8 tmp[2] = {reg, val};
88*4882a593Smuzhiyun 	return spi_write(spi, tmp, sizeof(tmp));
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun 
voltage_show(struct device * dev,struct device_attribute * da,char * buf)91*4882a593Smuzhiyun static ssize_t voltage_show(struct device *dev, struct device_attribute *da,
92*4882a593Smuzhiyun 			    char *buf)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	struct ads7871_data *pdata = dev_get_drvdata(dev);
95*4882a593Smuzhiyun 	struct spi_device *spi = pdata->spi;
96*4882a593Smuzhiyun 	struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
97*4882a593Smuzhiyun 	int ret, val, i = 0;
98*4882a593Smuzhiyun 	uint8_t channel, mux_cnv;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	channel = attr->index;
101*4882a593Smuzhiyun 	/*
102*4882a593Smuzhiyun 	 * TODO: add support for conversions
103*4882a593Smuzhiyun 	 * other than single ended with a gain of 1
104*4882a593Smuzhiyun 	 */
105*4882a593Smuzhiyun 	/*MUX_M3_BM forces single ended*/
106*4882a593Smuzhiyun 	/*This is also where the gain of the PGA would be set*/
107*4882a593Smuzhiyun 	ads7871_write_reg8(spi, REG_GAIN_MUX,
108*4882a593Smuzhiyun 		(MUX_CNV_BM | MUX_M3_BM | channel));
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	ret = ads7871_read_reg8(spi, REG_GAIN_MUX);
111*4882a593Smuzhiyun 	mux_cnv = ((ret & MUX_CNV_BM) >> MUX_CNV_BV);
112*4882a593Smuzhiyun 	/*
113*4882a593Smuzhiyun 	 * on 400MHz arm9 platform the conversion
114*4882a593Smuzhiyun 	 * is already done when we do this test
115*4882a593Smuzhiyun 	 */
116*4882a593Smuzhiyun 	while ((i < 2) && mux_cnv) {
117*4882a593Smuzhiyun 		i++;
118*4882a593Smuzhiyun 		ret = ads7871_read_reg8(spi, REG_GAIN_MUX);
119*4882a593Smuzhiyun 		mux_cnv = ((ret & MUX_CNV_BM) >> MUX_CNV_BV);
120*4882a593Smuzhiyun 		msleep_interruptible(1);
121*4882a593Smuzhiyun 	}
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	if (mux_cnv == 0) {
124*4882a593Smuzhiyun 		val = ads7871_read_reg16(spi, REG_LS_BYTE);
125*4882a593Smuzhiyun 		/*result in volts*10000 = (val/8192)*2.5*10000*/
126*4882a593Smuzhiyun 		val = ((val >> 2) * 25000) / 8192;
127*4882a593Smuzhiyun 		return sprintf(buf, "%d\n", val);
128*4882a593Smuzhiyun 	} else {
129*4882a593Smuzhiyun 		return -1;
130*4882a593Smuzhiyun 	}
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in0_input, voltage, 0);
134*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in1_input, voltage, 1);
135*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in2_input, voltage, 2);
136*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in3_input, voltage, 3);
137*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in4_input, voltage, 4);
138*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in5_input, voltage, 5);
139*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in6_input, voltage, 6);
140*4882a593Smuzhiyun static SENSOR_DEVICE_ATTR_RO(in7_input, voltage, 7);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun static struct attribute *ads7871_attrs[] = {
143*4882a593Smuzhiyun 	&sensor_dev_attr_in0_input.dev_attr.attr,
144*4882a593Smuzhiyun 	&sensor_dev_attr_in1_input.dev_attr.attr,
145*4882a593Smuzhiyun 	&sensor_dev_attr_in2_input.dev_attr.attr,
146*4882a593Smuzhiyun 	&sensor_dev_attr_in3_input.dev_attr.attr,
147*4882a593Smuzhiyun 	&sensor_dev_attr_in4_input.dev_attr.attr,
148*4882a593Smuzhiyun 	&sensor_dev_attr_in5_input.dev_attr.attr,
149*4882a593Smuzhiyun 	&sensor_dev_attr_in6_input.dev_attr.attr,
150*4882a593Smuzhiyun 	&sensor_dev_attr_in7_input.dev_attr.attr,
151*4882a593Smuzhiyun 	NULL
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun ATTRIBUTE_GROUPS(ads7871);
155*4882a593Smuzhiyun 
ads7871_probe(struct spi_device * spi)156*4882a593Smuzhiyun static int ads7871_probe(struct spi_device *spi)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	struct device *dev = &spi->dev;
159*4882a593Smuzhiyun 	int ret;
160*4882a593Smuzhiyun 	uint8_t val;
161*4882a593Smuzhiyun 	struct ads7871_data *pdata;
162*4882a593Smuzhiyun 	struct device *hwmon_dev;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	/* Configure the SPI bus */
165*4882a593Smuzhiyun 	spi->mode = (SPI_MODE_0);
166*4882a593Smuzhiyun 	spi->bits_per_word = 8;
167*4882a593Smuzhiyun 	spi_setup(spi);
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	ads7871_write_reg8(spi, REG_SER_CONTROL, 0);
170*4882a593Smuzhiyun 	ads7871_write_reg8(spi, REG_AD_CONTROL, 0);
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	val = (OSC_OSCR_BM | OSC_OSCE_BM | OSC_REFE_BM | OSC_BUFE_BM);
173*4882a593Smuzhiyun 	ads7871_write_reg8(spi, REG_OSC_CONTROL, val);
174*4882a593Smuzhiyun 	ret = ads7871_read_reg8(spi, REG_OSC_CONTROL);
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	dev_dbg(dev, "REG_OSC_CONTROL write:%x, read:%x\n", val, ret);
177*4882a593Smuzhiyun 	/*
178*4882a593Smuzhiyun 	 * because there is no other error checking on an SPI bus
179*4882a593Smuzhiyun 	 * we need to make sure we really have a chip
180*4882a593Smuzhiyun 	 */
181*4882a593Smuzhiyun 	if (val != ret)
182*4882a593Smuzhiyun 		return -ENODEV;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	pdata = devm_kzalloc(dev, sizeof(struct ads7871_data), GFP_KERNEL);
185*4882a593Smuzhiyun 	if (!pdata)
186*4882a593Smuzhiyun 		return -ENOMEM;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	pdata->spi = spi;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	hwmon_dev = devm_hwmon_device_register_with_groups(dev, spi->modalias,
191*4882a593Smuzhiyun 							   pdata,
192*4882a593Smuzhiyun 							   ads7871_groups);
193*4882a593Smuzhiyun 	return PTR_ERR_OR_ZERO(hwmon_dev);
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun static struct spi_driver ads7871_driver = {
197*4882a593Smuzhiyun 	.driver = {
198*4882a593Smuzhiyun 		.name = DEVICE_NAME,
199*4882a593Smuzhiyun 	},
200*4882a593Smuzhiyun 	.probe = ads7871_probe,
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun module_spi_driver(ads7871_driver);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun MODULE_AUTHOR("Paul Thomas <pthomas8589@gmail.com>");
206*4882a593Smuzhiyun MODULE_DESCRIPTION("TI ADS7871 A/D driver");
207*4882a593Smuzhiyun MODULE_LICENSE("GPL");
208