1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Most ISHTP provider device and ISHTP logic declarations
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2003-2016, Intel Corporation.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _ISHTP_DEV_H_
9*4882a593Smuzhiyun #define _ISHTP_DEV_H_
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun #include <linux/spinlock.h>
13*4882a593Smuzhiyun #include "bus.h"
14*4882a593Smuzhiyun #include "hbm.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define IPC_PAYLOAD_SIZE 128
17*4882a593Smuzhiyun #define ISHTP_RD_MSG_BUF_SIZE IPC_PAYLOAD_SIZE
18*4882a593Smuzhiyun #define IPC_FULL_MSG_SIZE 132
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Number of messages to be held in ISR->BH FIFO */
21*4882a593Smuzhiyun #define RD_INT_FIFO_SIZE 64
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * Number of IPC messages to be held in Tx FIFO, to be sent by ISR -
25*4882a593Smuzhiyun * Tx complete interrupt or RX_COMPLETE handler
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun #define IPC_TX_FIFO_SIZE 512
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * Number of Maximum ISHTP Clients
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun #define ISHTP_CLIENTS_MAX 256
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /*
35*4882a593Smuzhiyun * Number of File descriptors/handles
36*4882a593Smuzhiyun * that can be opened to the driver.
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun * Limit to 255: 256 Total Clients
39*4882a593Smuzhiyun * minus internal client for ISHTP Bus Messages
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun #define ISHTP_MAX_OPEN_HANDLE_COUNT (ISHTP_CLIENTS_MAX - 1)
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Internal Clients Number */
44*4882a593Smuzhiyun #define ISHTP_HOST_CLIENT_ID_ANY (-1)
45*4882a593Smuzhiyun #define ISHTP_HBM_HOST_CLIENT_ID 0
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define MAX_DMA_DELAY 20
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* ISHTP device states */
50*4882a593Smuzhiyun enum ishtp_dev_state {
51*4882a593Smuzhiyun ISHTP_DEV_INITIALIZING = 0,
52*4882a593Smuzhiyun ISHTP_DEV_INIT_CLIENTS,
53*4882a593Smuzhiyun ISHTP_DEV_ENABLED,
54*4882a593Smuzhiyun ISHTP_DEV_RESETTING,
55*4882a593Smuzhiyun ISHTP_DEV_DISABLED,
56*4882a593Smuzhiyun ISHTP_DEV_POWER_DOWN,
57*4882a593Smuzhiyun ISHTP_DEV_POWER_UP
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun const char *ishtp_dev_state_str(int state);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun struct ishtp_cl;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /**
64*4882a593Smuzhiyun * struct ishtp_fw_client - representation of fw client
65*4882a593Smuzhiyun *
66*4882a593Smuzhiyun * @props - client properties
67*4882a593Smuzhiyun * @client_id - fw client id
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun struct ishtp_fw_client {
70*4882a593Smuzhiyun struct ishtp_client_properties props;
71*4882a593Smuzhiyun uint8_t client_id;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /*
75*4882a593Smuzhiyun * Control info for IPC messages ISHTP/IPC sending FIFO -
76*4882a593Smuzhiyun * list with inline data buffer
77*4882a593Smuzhiyun * This structure will be filled with parameters submitted
78*4882a593Smuzhiyun * by the caller glue layer
79*4882a593Smuzhiyun * 'buf' may be pointing to the external buffer or to 'inline_data'
80*4882a593Smuzhiyun * 'offset' will be initialized to 0 by submitting
81*4882a593Smuzhiyun *
82*4882a593Smuzhiyun * 'ipc_send_compl' is intended for use by clients that send fragmented
83*4882a593Smuzhiyun * messages. When a fragment is sent down to IPC msg regs,
84*4882a593Smuzhiyun * it will be called.
85*4882a593Smuzhiyun * If it has more fragments to send, it will do it. With last fragment
86*4882a593Smuzhiyun * it will send appropriate ISHTP "message-complete" flag.
87*4882a593Smuzhiyun * It will remove the outstanding message
88*4882a593Smuzhiyun * (mark outstanding buffer as available).
89*4882a593Smuzhiyun * If counting flow control is in work and there are more flow control
90*4882a593Smuzhiyun * credits, it can put the next client message queued in cl.
91*4882a593Smuzhiyun * structure for IPC processing.
92*4882a593Smuzhiyun *
93*4882a593Smuzhiyun */
94*4882a593Smuzhiyun struct wr_msg_ctl_info {
95*4882a593Smuzhiyun /* Will be called with 'ipc_send_compl_prm' as parameter */
96*4882a593Smuzhiyun void (*ipc_send_compl)(void *);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun void *ipc_send_compl_prm;
99*4882a593Smuzhiyun size_t length;
100*4882a593Smuzhiyun struct list_head link;
101*4882a593Smuzhiyun unsigned char inline_data[IPC_FULL_MSG_SIZE];
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /*
105*4882a593Smuzhiyun * The ISHTP layer talks to hardware IPC message using the following
106*4882a593Smuzhiyun * callbacks
107*4882a593Smuzhiyun */
108*4882a593Smuzhiyun struct ishtp_hw_ops {
109*4882a593Smuzhiyun int (*hw_reset)(struct ishtp_device *dev);
110*4882a593Smuzhiyun int (*ipc_reset)(struct ishtp_device *dev);
111*4882a593Smuzhiyun uint32_t (*ipc_get_header)(struct ishtp_device *dev, int length,
112*4882a593Smuzhiyun int busy);
113*4882a593Smuzhiyun int (*write)(struct ishtp_device *dev,
114*4882a593Smuzhiyun void (*ipc_send_compl)(void *), void *ipc_send_compl_prm,
115*4882a593Smuzhiyun unsigned char *msg, int length);
116*4882a593Smuzhiyun uint32_t (*ishtp_read_hdr)(const struct ishtp_device *dev);
117*4882a593Smuzhiyun int (*ishtp_read)(struct ishtp_device *dev, unsigned char *buffer,
118*4882a593Smuzhiyun unsigned long buffer_length);
119*4882a593Smuzhiyun uint32_t (*get_fw_status)(struct ishtp_device *dev);
120*4882a593Smuzhiyun void (*sync_fw_clock)(struct ishtp_device *dev);
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /**
124*4882a593Smuzhiyun * struct ishtp_device - ISHTP private device struct
125*4882a593Smuzhiyun */
126*4882a593Smuzhiyun struct ishtp_device {
127*4882a593Smuzhiyun struct device *devc; /* pointer to lowest device */
128*4882a593Smuzhiyun struct pci_dev *pdev; /* PCI device to get device ids */
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* waitq for waiting for suspend response */
131*4882a593Smuzhiyun wait_queue_head_t suspend_wait;
132*4882a593Smuzhiyun bool suspend_flag; /* Suspend is active */
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* waitq for waiting for resume response */
135*4882a593Smuzhiyun wait_queue_head_t resume_wait;
136*4882a593Smuzhiyun bool resume_flag; /*Resume is active */
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /*
139*4882a593Smuzhiyun * lock for the device, for everything that doesn't have
140*4882a593Smuzhiyun * a dedicated spinlock
141*4882a593Smuzhiyun */
142*4882a593Smuzhiyun spinlock_t device_lock;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun bool recvd_hw_ready;
145*4882a593Smuzhiyun struct hbm_version version;
146*4882a593Smuzhiyun int transfer_path; /* Choice of transfer path: IPC or DMA */
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* ishtp device states */
149*4882a593Smuzhiyun enum ishtp_dev_state dev_state;
150*4882a593Smuzhiyun enum ishtp_hbm_state hbm_state;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /* driver read queue */
153*4882a593Smuzhiyun struct ishtp_cl_rb read_list;
154*4882a593Smuzhiyun spinlock_t read_list_spinlock;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* list of ishtp_cl's */
157*4882a593Smuzhiyun struct list_head cl_list;
158*4882a593Smuzhiyun spinlock_t cl_list_lock;
159*4882a593Smuzhiyun long open_handle_count;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun /* List of bus devices */
162*4882a593Smuzhiyun struct list_head device_list;
163*4882a593Smuzhiyun spinlock_t device_list_lock;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* waiting queues for receive message from FW */
166*4882a593Smuzhiyun wait_queue_head_t wait_hw_ready;
167*4882a593Smuzhiyun wait_queue_head_t wait_hbm_recvd_msg;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /* FIFO for input messages for BH processing */
170*4882a593Smuzhiyun unsigned char rd_msg_fifo[RD_INT_FIFO_SIZE * IPC_PAYLOAD_SIZE];
171*4882a593Smuzhiyun unsigned int rd_msg_fifo_head, rd_msg_fifo_tail;
172*4882a593Smuzhiyun spinlock_t rd_msg_spinlock;
173*4882a593Smuzhiyun struct work_struct bh_hbm_work;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /* IPC write queue */
176*4882a593Smuzhiyun struct list_head wr_processing_list, wr_free_list;
177*4882a593Smuzhiyun /* For both processing list and free list */
178*4882a593Smuzhiyun spinlock_t wr_processing_spinlock;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun struct ishtp_fw_client *fw_clients; /*Note:memory has to be allocated*/
181*4882a593Smuzhiyun DECLARE_BITMAP(fw_clients_map, ISHTP_CLIENTS_MAX);
182*4882a593Smuzhiyun DECLARE_BITMAP(host_clients_map, ISHTP_CLIENTS_MAX);
183*4882a593Smuzhiyun uint8_t fw_clients_num;
184*4882a593Smuzhiyun uint8_t fw_client_presentation_num;
185*4882a593Smuzhiyun uint8_t fw_client_index;
186*4882a593Smuzhiyun spinlock_t fw_clients_lock;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun /* TX DMA buffers and slots */
189*4882a593Smuzhiyun int ishtp_host_dma_enabled;
190*4882a593Smuzhiyun void *ishtp_host_dma_tx_buf;
191*4882a593Smuzhiyun unsigned int ishtp_host_dma_tx_buf_size;
192*4882a593Smuzhiyun uint64_t ishtp_host_dma_tx_buf_phys;
193*4882a593Smuzhiyun int ishtp_dma_num_slots;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* map of 4k blocks in Tx dma buf: 0-free, 1-used */
196*4882a593Smuzhiyun uint8_t *ishtp_dma_tx_map;
197*4882a593Smuzhiyun spinlock_t ishtp_dma_tx_lock;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /* RX DMA buffers and slots */
200*4882a593Smuzhiyun void *ishtp_host_dma_rx_buf;
201*4882a593Smuzhiyun unsigned int ishtp_host_dma_rx_buf_size;
202*4882a593Smuzhiyun uint64_t ishtp_host_dma_rx_buf_phys;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /* Dump to trace buffers if enabled*/
205*4882a593Smuzhiyun __printf(2, 3) void (*print_log)(struct ishtp_device *dev,
206*4882a593Smuzhiyun const char *format, ...);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /* Debug stats */
209*4882a593Smuzhiyun unsigned int ipc_rx_cnt;
210*4882a593Smuzhiyun unsigned long long ipc_rx_bytes_cnt;
211*4882a593Smuzhiyun unsigned int ipc_tx_cnt;
212*4882a593Smuzhiyun unsigned long long ipc_tx_bytes_cnt;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun const struct ishtp_hw_ops *ops;
215*4882a593Smuzhiyun size_t mtu;
216*4882a593Smuzhiyun uint32_t ishtp_msg_hdr;
217*4882a593Smuzhiyun char hw[] __aligned(sizeof(void *));
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun
ishtp_secs_to_jiffies(unsigned long sec)220*4882a593Smuzhiyun static inline unsigned long ishtp_secs_to_jiffies(unsigned long sec)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun return msecs_to_jiffies(sec * MSEC_PER_SEC);
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /*
226*4882a593Smuzhiyun * Register Access Function
227*4882a593Smuzhiyun */
ish_ipc_reset(struct ishtp_device * dev)228*4882a593Smuzhiyun static inline int ish_ipc_reset(struct ishtp_device *dev)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun return dev->ops->ipc_reset(dev);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun /* Exported function */
234*4882a593Smuzhiyun void ishtp_device_init(struct ishtp_device *dev);
235*4882a593Smuzhiyun int ishtp_start(struct ishtp_device *dev);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun #endif /*_ISHTP_DEV_H_*/
238