1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * H/W layer of ISHTP provider device (ISH) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2014-2016, Intel Corporation. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ISHTP_HW_ISH_H_ 9*4882a593Smuzhiyun #define _ISHTP_HW_ISH_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/pci.h> 12*4882a593Smuzhiyun #include <linux/interrupt.h> 13*4882a593Smuzhiyun #include "hw-ish-regs.h" 14*4882a593Smuzhiyun #include "ishtp-dev.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CHV_DEVICE_ID 0x22D8 17*4882a593Smuzhiyun #define BXT_Ax_DEVICE_ID 0x0AA2 18*4882a593Smuzhiyun #define BXT_Bx_DEVICE_ID 0x1AA2 19*4882a593Smuzhiyun #define APL_Ax_DEVICE_ID 0x5AA2 20*4882a593Smuzhiyun #define SPT_Ax_DEVICE_ID 0x9D35 21*4882a593Smuzhiyun #define CNL_Ax_DEVICE_ID 0x9DFC 22*4882a593Smuzhiyun #define GLK_Ax_DEVICE_ID 0x31A2 23*4882a593Smuzhiyun #define CNL_H_DEVICE_ID 0xA37C 24*4882a593Smuzhiyun #define ICL_MOBILE_DEVICE_ID 0x34FC 25*4882a593Smuzhiyun #define SPT_H_DEVICE_ID 0xA135 26*4882a593Smuzhiyun #define CML_LP_DEVICE_ID 0x02FC 27*4882a593Smuzhiyun #define CMP_H_DEVICE_ID 0x06FC 28*4882a593Smuzhiyun #define EHL_Ax_DEVICE_ID 0x4BB3 29*4882a593Smuzhiyun #define TGL_LP_DEVICE_ID 0xA0FC 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define REVISION_ID_CHT_A0 0x6 32*4882a593Smuzhiyun #define REVISION_ID_CHT_Ax_SI 0x0 33*4882a593Smuzhiyun #define REVISION_ID_CHT_Bx_SI 0x10 34*4882a593Smuzhiyun #define REVISION_ID_CHT_Kx_SI 0x20 35*4882a593Smuzhiyun #define REVISION_ID_CHT_Dx_SI 0x30 36*4882a593Smuzhiyun #define REVISION_ID_CHT_B0 0xB0 37*4882a593Smuzhiyun #define REVISION_ID_SI_MASK 0x70 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct ipc_rst_payload_type { 40*4882a593Smuzhiyun uint16_t reset_id; 41*4882a593Smuzhiyun uint16_t reserved; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct time_sync_format { 45*4882a593Smuzhiyun uint8_t ts1_source; 46*4882a593Smuzhiyun uint8_t ts2_source; 47*4882a593Smuzhiyun uint16_t reserved; 48*4882a593Smuzhiyun } __packed; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct ipc_time_update_msg { 51*4882a593Smuzhiyun uint64_t primary_host_time; 52*4882a593Smuzhiyun struct time_sync_format sync_info; 53*4882a593Smuzhiyun uint64_t secondary_host_time; 54*4882a593Smuzhiyun } __packed; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun enum { 57*4882a593Smuzhiyun HOST_UTC_TIME_USEC = 0, 58*4882a593Smuzhiyun HOST_SYSTEM_TIME_USEC = 1 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun struct ish_hw { 62*4882a593Smuzhiyun void __iomem *mem_addr; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* 66*4882a593Smuzhiyun * ISH FW status type 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun enum { 69*4882a593Smuzhiyun FWSTS_AFTER_RESET = 0, 70*4882a593Smuzhiyun FWSTS_WAIT_FOR_HOST = 4, 71*4882a593Smuzhiyun FWSTS_START_KERNEL_DMA = 5, 72*4882a593Smuzhiyun FWSTS_FW_IS_RUNNING = 7, 73*4882a593Smuzhiyun FWSTS_SENSOR_APP_LOADED = 8, 74*4882a593Smuzhiyun FWSTS_SENSOR_APP_RUNNING = 15 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define to_ish_hw(dev) (struct ish_hw *)((dev)->hw) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun irqreturn_t ish_irq_handler(int irq, void *dev_id); 80*4882a593Smuzhiyun struct ishtp_device *ish_dev_init(struct pci_dev *pdev); 81*4882a593Smuzhiyun int ish_hw_start(struct ishtp_device *dev); 82*4882a593Smuzhiyun void ish_device_disable(struct ishtp_device *dev); 83*4882a593Smuzhiyun int ish_disable_dma(struct ishtp_device *dev); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* _ISHTP_HW_ISH_H_ */ 86