xref: /OK3568_Linux_fs/kernel/drivers/gpu/ipu-v3/ipu-vdi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2012-2016 Mentor Graphics Inc.
4*4882a593Smuzhiyun  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun #include <linux/io.h>
7*4882a593Smuzhiyun #include "ipu-prv.h"
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun struct ipu_vdi {
10*4882a593Smuzhiyun 	void __iomem *base;
11*4882a593Smuzhiyun 	u32 module;
12*4882a593Smuzhiyun 	spinlock_t lock;
13*4882a593Smuzhiyun 	int use_count;
14*4882a593Smuzhiyun 	struct ipu_soc *ipu;
15*4882a593Smuzhiyun };
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* VDI Register Offsets */
19*4882a593Smuzhiyun #define VDI_FSIZE 0x0000
20*4882a593Smuzhiyun #define VDI_C     0x0004
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* VDI Register Fields */
23*4882a593Smuzhiyun #define VDI_C_CH_420             (0 << 1)
24*4882a593Smuzhiyun #define VDI_C_CH_422             (1 << 1)
25*4882a593Smuzhiyun #define VDI_C_MOT_SEL_MASK       (0x3 << 2)
26*4882a593Smuzhiyun #define VDI_C_MOT_SEL_FULL       (2 << 2)
27*4882a593Smuzhiyun #define VDI_C_MOT_SEL_LOW        (1 << 2)
28*4882a593Smuzhiyun #define VDI_C_MOT_SEL_MED        (0 << 2)
29*4882a593Smuzhiyun #define VDI_C_BURST_SIZE1_4      (3 << 4)
30*4882a593Smuzhiyun #define VDI_C_BURST_SIZE2_4      (3 << 8)
31*4882a593Smuzhiyun #define VDI_C_BURST_SIZE3_4      (3 << 12)
32*4882a593Smuzhiyun #define VDI_C_BURST_SIZE_MASK    0xF
33*4882a593Smuzhiyun #define VDI_C_BURST_SIZE1_OFFSET 4
34*4882a593Smuzhiyun #define VDI_C_BURST_SIZE2_OFFSET 8
35*4882a593Smuzhiyun #define VDI_C_BURST_SIZE3_OFFSET 12
36*4882a593Smuzhiyun #define VDI_C_VWM1_SET_1         (0 << 16)
37*4882a593Smuzhiyun #define VDI_C_VWM1_SET_2         (1 << 16)
38*4882a593Smuzhiyun #define VDI_C_VWM1_CLR_2         (1 << 19)
39*4882a593Smuzhiyun #define VDI_C_VWM3_SET_1         (0 << 22)
40*4882a593Smuzhiyun #define VDI_C_VWM3_SET_2         (1 << 22)
41*4882a593Smuzhiyun #define VDI_C_VWM3_CLR_2         (1 << 25)
42*4882a593Smuzhiyun #define VDI_C_TOP_FIELD_MAN_1    (1 << 30)
43*4882a593Smuzhiyun #define VDI_C_TOP_FIELD_AUTO_1   (1 << 31)
44*4882a593Smuzhiyun 
ipu_vdi_read(struct ipu_vdi * vdi,unsigned int offset)45*4882a593Smuzhiyun static inline u32 ipu_vdi_read(struct ipu_vdi *vdi, unsigned int offset)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun 	return readl(vdi->base + offset);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun 
ipu_vdi_write(struct ipu_vdi * vdi,u32 value,unsigned int offset)50*4882a593Smuzhiyun static inline void ipu_vdi_write(struct ipu_vdi *vdi, u32 value,
51*4882a593Smuzhiyun 				 unsigned int offset)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun 	writel(value, vdi->base + offset);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun 
ipu_vdi_set_field_order(struct ipu_vdi * vdi,v4l2_std_id std,u32 field)56*4882a593Smuzhiyun void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun 	bool top_field_0 = false;
59*4882a593Smuzhiyun 	unsigned long flags;
60*4882a593Smuzhiyun 	u32 reg;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	switch (field) {
63*4882a593Smuzhiyun 	case V4L2_FIELD_INTERLACED_TB:
64*4882a593Smuzhiyun 	case V4L2_FIELD_SEQ_TB:
65*4882a593Smuzhiyun 	case V4L2_FIELD_TOP:
66*4882a593Smuzhiyun 		top_field_0 = true;
67*4882a593Smuzhiyun 		break;
68*4882a593Smuzhiyun 	case V4L2_FIELD_INTERLACED_BT:
69*4882a593Smuzhiyun 	case V4L2_FIELD_SEQ_BT:
70*4882a593Smuzhiyun 	case V4L2_FIELD_BOTTOM:
71*4882a593Smuzhiyun 		top_field_0 = false;
72*4882a593Smuzhiyun 		break;
73*4882a593Smuzhiyun 	default:
74*4882a593Smuzhiyun 		top_field_0 = (std & V4L2_STD_525_60) ? true : false;
75*4882a593Smuzhiyun 		break;
76*4882a593Smuzhiyun 	}
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	spin_lock_irqsave(&vdi->lock, flags);
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	reg = ipu_vdi_read(vdi, VDI_C);
81*4882a593Smuzhiyun 	if (top_field_0)
82*4882a593Smuzhiyun 		reg &= ~(VDI_C_TOP_FIELD_MAN_1 | VDI_C_TOP_FIELD_AUTO_1);
83*4882a593Smuzhiyun 	else
84*4882a593Smuzhiyun 		reg |= VDI_C_TOP_FIELD_MAN_1 | VDI_C_TOP_FIELD_AUTO_1;
85*4882a593Smuzhiyun 	ipu_vdi_write(vdi, reg, VDI_C);
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	spin_unlock_irqrestore(&vdi->lock, flags);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ipu_vdi_set_field_order);
90*4882a593Smuzhiyun 
ipu_vdi_set_motion(struct ipu_vdi * vdi,enum ipu_motion_sel motion_sel)91*4882a593Smuzhiyun void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	unsigned long flags;
94*4882a593Smuzhiyun 	u32 reg;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	spin_lock_irqsave(&vdi->lock, flags);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	reg = ipu_vdi_read(vdi, VDI_C);
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	reg &= ~VDI_C_MOT_SEL_MASK;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	switch (motion_sel) {
103*4882a593Smuzhiyun 	case MED_MOTION:
104*4882a593Smuzhiyun 		reg |= VDI_C_MOT_SEL_MED;
105*4882a593Smuzhiyun 		break;
106*4882a593Smuzhiyun 	case HIGH_MOTION:
107*4882a593Smuzhiyun 		reg |= VDI_C_MOT_SEL_FULL;
108*4882a593Smuzhiyun 		break;
109*4882a593Smuzhiyun 	default:
110*4882a593Smuzhiyun 		reg |= VDI_C_MOT_SEL_LOW;
111*4882a593Smuzhiyun 		break;
112*4882a593Smuzhiyun 	}
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	ipu_vdi_write(vdi, reg, VDI_C);
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	spin_unlock_irqrestore(&vdi->lock, flags);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ipu_vdi_set_motion);
119*4882a593Smuzhiyun 
ipu_vdi_setup(struct ipu_vdi * vdi,u32 code,int xres,int yres)120*4882a593Smuzhiyun void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	unsigned long flags;
123*4882a593Smuzhiyun 	u32 pixel_fmt, reg;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	spin_lock_irqsave(&vdi->lock, flags);
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	reg = ((yres - 1) << 16) | (xres - 1);
128*4882a593Smuzhiyun 	ipu_vdi_write(vdi, reg, VDI_FSIZE);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	/*
131*4882a593Smuzhiyun 	 * Full motion, only vertical filter is used.
132*4882a593Smuzhiyun 	 * Burst size is 4 accesses
133*4882a593Smuzhiyun 	 */
134*4882a593Smuzhiyun 	if (code == MEDIA_BUS_FMT_UYVY8_2X8 ||
135*4882a593Smuzhiyun 	    code == MEDIA_BUS_FMT_UYVY8_1X16 ||
136*4882a593Smuzhiyun 	    code == MEDIA_BUS_FMT_YUYV8_2X8 ||
137*4882a593Smuzhiyun 	    code == MEDIA_BUS_FMT_YUYV8_1X16)
138*4882a593Smuzhiyun 		pixel_fmt = VDI_C_CH_422;
139*4882a593Smuzhiyun 	else
140*4882a593Smuzhiyun 		pixel_fmt = VDI_C_CH_420;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	reg = ipu_vdi_read(vdi, VDI_C);
143*4882a593Smuzhiyun 	reg |= pixel_fmt;
144*4882a593Smuzhiyun 	reg |= VDI_C_BURST_SIZE2_4;
145*4882a593Smuzhiyun 	reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_CLR_2;
146*4882a593Smuzhiyun 	reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_CLR_2;
147*4882a593Smuzhiyun 	ipu_vdi_write(vdi, reg, VDI_C);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	spin_unlock_irqrestore(&vdi->lock, flags);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ipu_vdi_setup);
152*4882a593Smuzhiyun 
ipu_vdi_unsetup(struct ipu_vdi * vdi)153*4882a593Smuzhiyun void ipu_vdi_unsetup(struct ipu_vdi *vdi)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun 	unsigned long flags;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	spin_lock_irqsave(&vdi->lock, flags);
158*4882a593Smuzhiyun 	ipu_vdi_write(vdi, 0, VDI_FSIZE);
159*4882a593Smuzhiyun 	ipu_vdi_write(vdi, 0, VDI_C);
160*4882a593Smuzhiyun 	spin_unlock_irqrestore(&vdi->lock, flags);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ipu_vdi_unsetup);
163*4882a593Smuzhiyun 
ipu_vdi_enable(struct ipu_vdi * vdi)164*4882a593Smuzhiyun int ipu_vdi_enable(struct ipu_vdi *vdi)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	unsigned long flags;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	spin_lock_irqsave(&vdi->lock, flags);
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	if (!vdi->use_count)
171*4882a593Smuzhiyun 		ipu_module_enable(vdi->ipu, vdi->module);
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	vdi->use_count++;
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	spin_unlock_irqrestore(&vdi->lock, flags);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	return 0;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ipu_vdi_enable);
180*4882a593Smuzhiyun 
ipu_vdi_disable(struct ipu_vdi * vdi)181*4882a593Smuzhiyun int ipu_vdi_disable(struct ipu_vdi *vdi)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	unsigned long flags;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	spin_lock_irqsave(&vdi->lock, flags);
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	if (vdi->use_count) {
188*4882a593Smuzhiyun 		if (!--vdi->use_count)
189*4882a593Smuzhiyun 			ipu_module_disable(vdi->ipu, vdi->module);
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	spin_unlock_irqrestore(&vdi->lock, flags);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	return 0;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ipu_vdi_disable);
197*4882a593Smuzhiyun 
ipu_vdi_get(struct ipu_soc * ipu)198*4882a593Smuzhiyun struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	return ipu->vdi_priv;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ipu_vdi_get);
203*4882a593Smuzhiyun 
ipu_vdi_put(struct ipu_vdi * vdi)204*4882a593Smuzhiyun void ipu_vdi_put(struct ipu_vdi *vdi)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ipu_vdi_put);
208*4882a593Smuzhiyun 
ipu_vdi_init(struct ipu_soc * ipu,struct device * dev,unsigned long base,u32 module)209*4882a593Smuzhiyun int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
210*4882a593Smuzhiyun 		 unsigned long base, u32 module)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun 	struct ipu_vdi *vdi;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	vdi = devm_kzalloc(dev, sizeof(*vdi), GFP_KERNEL);
215*4882a593Smuzhiyun 	if (!vdi)
216*4882a593Smuzhiyun 		return -ENOMEM;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	ipu->vdi_priv = vdi;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	spin_lock_init(&vdi->lock);
221*4882a593Smuzhiyun 	vdi->module = module;
222*4882a593Smuzhiyun 	vdi->base = devm_ioremap(dev, base, PAGE_SIZE);
223*4882a593Smuzhiyun 	if (!vdi->base)
224*4882a593Smuzhiyun 		return -ENOMEM;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	dev_dbg(dev, "VDI base: 0x%08lx remapped to %p\n", base, vdi->base);
227*4882a593Smuzhiyun 	vdi->ipu = ipu;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	return 0;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun 
ipu_vdi_exit(struct ipu_soc * ipu)232*4882a593Smuzhiyun void ipu_vdi_exit(struct ipu_soc *ipu)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun }
235