xref: /OK3568_Linux_fs/kernel/drivers/gpu/host1x/hw/debug_hw.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2010 Google, Inc.
4*4882a593Smuzhiyun  * Author: Erik Gilling <konkers@android.com>
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2011-2013 NVIDIA Corporation
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include "../dev.h"
10*4882a593Smuzhiyun #include "../debug.h"
11*4882a593Smuzhiyun #include "../cdma.h"
12*4882a593Smuzhiyun #include "../channel.h"
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #define HOST1X_DEBUG_MAX_PAGE_OFFSET 102400
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun enum {
17*4882a593Smuzhiyun 	HOST1X_OPCODE_SETCLASS	= 0x00,
18*4882a593Smuzhiyun 	HOST1X_OPCODE_INCR	= 0x01,
19*4882a593Smuzhiyun 	HOST1X_OPCODE_NONINCR	= 0x02,
20*4882a593Smuzhiyun 	HOST1X_OPCODE_MASK	= 0x03,
21*4882a593Smuzhiyun 	HOST1X_OPCODE_IMM	= 0x04,
22*4882a593Smuzhiyun 	HOST1X_OPCODE_RESTART	= 0x05,
23*4882a593Smuzhiyun 	HOST1X_OPCODE_GATHER	= 0x06,
24*4882a593Smuzhiyun 	HOST1X_OPCODE_SETSTRMID = 0x07,
25*4882a593Smuzhiyun 	HOST1X_OPCODE_SETAPPID  = 0x08,
26*4882a593Smuzhiyun 	HOST1X_OPCODE_SETPYLD   = 0x09,
27*4882a593Smuzhiyun 	HOST1X_OPCODE_INCR_W    = 0x0a,
28*4882a593Smuzhiyun 	HOST1X_OPCODE_NONINCR_W = 0x0b,
29*4882a593Smuzhiyun 	HOST1X_OPCODE_GATHER_W  = 0x0c,
30*4882a593Smuzhiyun 	HOST1X_OPCODE_RESTART_W = 0x0d,
31*4882a593Smuzhiyun 	HOST1X_OPCODE_EXTEND	= 0x0e,
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun enum {
35*4882a593Smuzhiyun 	HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK	= 0x00,
36*4882a593Smuzhiyun 	HOST1X_OPCODE_EXTEND_RELEASE_MLOCK	= 0x01,
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define INVALID_PAYLOAD				0xffffffff
40*4882a593Smuzhiyun 
show_channel_command(struct output * o,u32 val,u32 * payload)41*4882a593Smuzhiyun static unsigned int show_channel_command(struct output *o, u32 val,
42*4882a593Smuzhiyun 					 u32 *payload)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun 	unsigned int mask, subop, num, opcode;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	opcode = val >> 28;
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	switch (opcode) {
49*4882a593Smuzhiyun 	case HOST1X_OPCODE_SETCLASS:
50*4882a593Smuzhiyun 		mask = val & 0x3f;
51*4882a593Smuzhiyun 		if (mask) {
52*4882a593Smuzhiyun 			host1x_debug_cont(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [",
53*4882a593Smuzhiyun 					    val >> 6 & 0x3ff,
54*4882a593Smuzhiyun 					    val >> 16 & 0xfff, mask);
55*4882a593Smuzhiyun 			return hweight8(mask);
56*4882a593Smuzhiyun 		}
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 		host1x_debug_cont(o, "SETCL(class=%03x)\n", val >> 6 & 0x3ff);
59*4882a593Smuzhiyun 		return 0;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	case HOST1X_OPCODE_INCR:
62*4882a593Smuzhiyun 		num = val & 0xffff;
63*4882a593Smuzhiyun 		host1x_debug_cont(o, "INCR(offset=%03x, [",
64*4882a593Smuzhiyun 				    val >> 16 & 0xfff);
65*4882a593Smuzhiyun 		if (!num)
66*4882a593Smuzhiyun 			host1x_debug_cont(o, "])\n");
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 		return num;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	case HOST1X_OPCODE_NONINCR:
71*4882a593Smuzhiyun 		num = val & 0xffff;
72*4882a593Smuzhiyun 		host1x_debug_cont(o, "NONINCR(offset=%03x, [",
73*4882a593Smuzhiyun 				    val >> 16 & 0xfff);
74*4882a593Smuzhiyun 		if (!num)
75*4882a593Smuzhiyun 			host1x_debug_cont(o, "])\n");
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 		return num;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	case HOST1X_OPCODE_MASK:
80*4882a593Smuzhiyun 		mask = val & 0xffff;
81*4882a593Smuzhiyun 		host1x_debug_cont(o, "MASK(offset=%03x, mask=%03x, [",
82*4882a593Smuzhiyun 				    val >> 16 & 0xfff, mask);
83*4882a593Smuzhiyun 		if (!mask)
84*4882a593Smuzhiyun 			host1x_debug_cont(o, "])\n");
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 		return hweight16(mask);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	case HOST1X_OPCODE_IMM:
89*4882a593Smuzhiyun 		host1x_debug_cont(o, "IMM(offset=%03x, data=%03x)\n",
90*4882a593Smuzhiyun 				    val >> 16 & 0xfff, val & 0xffff);
91*4882a593Smuzhiyun 		return 0;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	case HOST1X_OPCODE_RESTART:
94*4882a593Smuzhiyun 		host1x_debug_cont(o, "RESTART(offset=%08x)\n", val << 4);
95*4882a593Smuzhiyun 		return 0;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	case HOST1X_OPCODE_GATHER:
98*4882a593Smuzhiyun 		host1x_debug_cont(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[",
99*4882a593Smuzhiyun 				    val >> 16 & 0xfff, val >> 15 & 0x1,
100*4882a593Smuzhiyun 				    val >> 14 & 0x1, val & 0x3fff);
101*4882a593Smuzhiyun 		return 1;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun #if HOST1X_HW >= 6
104*4882a593Smuzhiyun 	case HOST1X_OPCODE_SETSTRMID:
105*4882a593Smuzhiyun 		host1x_debug_cont(o, "SETSTRMID(offset=%06x)\n",
106*4882a593Smuzhiyun 				  val & 0x3fffff);
107*4882a593Smuzhiyun 		return 0;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	case HOST1X_OPCODE_SETAPPID:
110*4882a593Smuzhiyun 		host1x_debug_cont(o, "SETAPPID(appid=%02x)\n", val & 0xff);
111*4882a593Smuzhiyun 		return 0;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	case HOST1X_OPCODE_SETPYLD:
114*4882a593Smuzhiyun 		*payload = val & 0xffff;
115*4882a593Smuzhiyun 		host1x_debug_cont(o, "SETPYLD(data=%04x)\n", *payload);
116*4882a593Smuzhiyun 		return 0;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	case HOST1X_OPCODE_INCR_W:
119*4882a593Smuzhiyun 	case HOST1X_OPCODE_NONINCR_W:
120*4882a593Smuzhiyun 		host1x_debug_cont(o, "%s(offset=%06x, ",
121*4882a593Smuzhiyun 				  opcode == HOST1X_OPCODE_INCR_W ?
122*4882a593Smuzhiyun 					"INCR_W" : "NONINCR_W",
123*4882a593Smuzhiyun 				  val & 0x3fffff);
124*4882a593Smuzhiyun 		if (*payload == 0) {
125*4882a593Smuzhiyun 			host1x_debug_cont(o, "[])\n");
126*4882a593Smuzhiyun 			return 0;
127*4882a593Smuzhiyun 		} else if (*payload == INVALID_PAYLOAD) {
128*4882a593Smuzhiyun 			host1x_debug_cont(o, "unknown)\n");
129*4882a593Smuzhiyun 			return 0;
130*4882a593Smuzhiyun 		} else {
131*4882a593Smuzhiyun 			host1x_debug_cont(o, "[");
132*4882a593Smuzhiyun 			return *payload;
133*4882a593Smuzhiyun 		}
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	case HOST1X_OPCODE_GATHER_W:
136*4882a593Smuzhiyun 		host1x_debug_cont(o, "GATHER_W(count=%04x, addr=[",
137*4882a593Smuzhiyun 				  val & 0x3fff);
138*4882a593Smuzhiyun 		return 2;
139*4882a593Smuzhiyun #endif
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	case HOST1X_OPCODE_EXTEND:
142*4882a593Smuzhiyun 		subop = val >> 24 & 0xf;
143*4882a593Smuzhiyun 		if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)
144*4882a593Smuzhiyun 			host1x_debug_cont(o, "ACQUIRE_MLOCK(index=%d)\n",
145*4882a593Smuzhiyun 					    val & 0xff);
146*4882a593Smuzhiyun 		else if (subop == HOST1X_OPCODE_EXTEND_RELEASE_MLOCK)
147*4882a593Smuzhiyun 			host1x_debug_cont(o, "RELEASE_MLOCK(index=%d)\n",
148*4882a593Smuzhiyun 					    val & 0xff);
149*4882a593Smuzhiyun 		else
150*4882a593Smuzhiyun 			host1x_debug_cont(o, "EXTEND_UNKNOWN(%08x)\n", val);
151*4882a593Smuzhiyun 		return 0;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	default:
154*4882a593Smuzhiyun 		host1x_debug_cont(o, "UNKNOWN\n");
155*4882a593Smuzhiyun 		return 0;
156*4882a593Smuzhiyun 	}
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun 
show_gather(struct output * o,phys_addr_t phys_addr,unsigned int words,struct host1x_cdma * cdma,phys_addr_t pin_addr,u32 * map_addr)159*4882a593Smuzhiyun static void show_gather(struct output *o, phys_addr_t phys_addr,
160*4882a593Smuzhiyun 			unsigned int words, struct host1x_cdma *cdma,
161*4882a593Smuzhiyun 			phys_addr_t pin_addr, u32 *map_addr)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun 	/* Map dmaget cursor to corresponding mem handle */
164*4882a593Smuzhiyun 	u32 offset = phys_addr - pin_addr;
165*4882a593Smuzhiyun 	unsigned int data_count = 0, i;
166*4882a593Smuzhiyun 	u32 payload = INVALID_PAYLOAD;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	/*
169*4882a593Smuzhiyun 	 * Sometimes we're given different hardware address to the same
170*4882a593Smuzhiyun 	 * page - in these cases the offset will get an invalid number and
171*4882a593Smuzhiyun 	 * we just have to bail out.
172*4882a593Smuzhiyun 	 */
173*4882a593Smuzhiyun 	if (offset > HOST1X_DEBUG_MAX_PAGE_OFFSET) {
174*4882a593Smuzhiyun 		host1x_debug_output(o, "[address mismatch]\n");
175*4882a593Smuzhiyun 		return;
176*4882a593Smuzhiyun 	}
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	for (i = 0; i < words; i++) {
179*4882a593Smuzhiyun 		u32 addr = phys_addr + i * 4;
180*4882a593Smuzhiyun 		u32 val = *(map_addr + offset / 4 + i);
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 		if (!data_count) {
183*4882a593Smuzhiyun 			host1x_debug_output(o, "%08x: %08x: ", addr, val);
184*4882a593Smuzhiyun 			data_count = show_channel_command(o, val, &payload);
185*4882a593Smuzhiyun 		} else {
186*4882a593Smuzhiyun 			host1x_debug_cont(o, "%08x%s", val,
187*4882a593Smuzhiyun 					    data_count > 1 ? ", " : "])\n");
188*4882a593Smuzhiyun 			data_count--;
189*4882a593Smuzhiyun 		}
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun 
show_channel_gathers(struct output * o,struct host1x_cdma * cdma)193*4882a593Smuzhiyun static void show_channel_gathers(struct output *o, struct host1x_cdma *cdma)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun 	struct push_buffer *pb = &cdma->push_buffer;
196*4882a593Smuzhiyun 	struct host1x_job *job;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	host1x_debug_output(o, "PUSHBUF at %pad, %u words\n",
199*4882a593Smuzhiyun 			    &pb->dma, pb->size / 4);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	show_gather(o, pb->dma, pb->size / 4, cdma, pb->dma, pb->mapped);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	list_for_each_entry(job, &cdma->sync_queue, list) {
204*4882a593Smuzhiyun 		unsigned int i;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 		host1x_debug_output(o, "\n%p: JOB, syncpt_id=%d, syncpt_val=%d, first_get=%08x, timeout=%d num_slots=%d, num_handles=%d\n",
207*4882a593Smuzhiyun 				    job, job->syncpt_id, job->syncpt_end,
208*4882a593Smuzhiyun 				    job->first_get, job->timeout,
209*4882a593Smuzhiyun 				    job->num_slots, job->num_unpins);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 		for (i = 0; i < job->num_gathers; i++) {
212*4882a593Smuzhiyun 			struct host1x_job_gather *g = &job->gathers[i];
213*4882a593Smuzhiyun 			u32 *mapped;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 			if (job->gather_copy_mapped)
216*4882a593Smuzhiyun 				mapped = (u32 *)job->gather_copy_mapped;
217*4882a593Smuzhiyun 			else
218*4882a593Smuzhiyun 				mapped = host1x_bo_mmap(g->bo);
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 			if (!mapped) {
221*4882a593Smuzhiyun 				host1x_debug_output(o, "[could not mmap]\n");
222*4882a593Smuzhiyun 				continue;
223*4882a593Smuzhiyun 			}
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 			host1x_debug_output(o, "    GATHER at %pad+%#x, %d words\n",
226*4882a593Smuzhiyun 					    &g->base, g->offset, g->words);
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 			show_gather(o, g->base + g->offset, g->words, cdma,
229*4882a593Smuzhiyun 				    g->base, mapped);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 			if (!job->gather_copy_mapped)
232*4882a593Smuzhiyun 				host1x_bo_munmap(g->bo, mapped);
233*4882a593Smuzhiyun 		}
234*4882a593Smuzhiyun 	}
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun #if HOST1X_HW >= 6
238*4882a593Smuzhiyun #include "debug_hw_1x06.c"
239*4882a593Smuzhiyun #else
240*4882a593Smuzhiyun #include "debug_hw_1x01.c"
241*4882a593Smuzhiyun #endif
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun static const struct host1x_debug_ops host1x_debug_ops = {
244*4882a593Smuzhiyun 	.show_channel_cdma = host1x_debug_show_channel_cdma,
245*4882a593Smuzhiyun 	.show_channel_fifo = host1x_debug_show_channel_fifo,
246*4882a593Smuzhiyun 	.show_mlocks = host1x_debug_show_mlocks,
247*4882a593Smuzhiyun };
248