1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Tegra host1x Command DMA 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2010-2013, NVIDIA Corporation. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __HOST1X_CDMA_H 9*4882a593Smuzhiyun #define __HOST1X_CDMA_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/sched.h> 12*4882a593Smuzhiyun #include <linux/completion.h> 13*4882a593Smuzhiyun #include <linux/list.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct host1x_syncpt; 16*4882a593Smuzhiyun struct host1x_userctx_timeout; 17*4882a593Smuzhiyun struct host1x_job; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * cdma 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * This is in charge of a host command DMA channel. 23*4882a593Smuzhiyun * Sends ops to a push buffer, and takes responsibility for unpinning 24*4882a593Smuzhiyun * (& possibly freeing) of memory after those ops have completed. 25*4882a593Smuzhiyun * Producer: 26*4882a593Smuzhiyun * begin 27*4882a593Smuzhiyun * push - send ops to the push buffer 28*4882a593Smuzhiyun * end - start command DMA and enqueue handles to be unpinned 29*4882a593Smuzhiyun * Consumer: 30*4882a593Smuzhiyun * update - call to update sync queue and push buffer, unpin memory 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct push_buffer { 34*4882a593Smuzhiyun void *mapped; /* mapped pushbuffer memory */ 35*4882a593Smuzhiyun dma_addr_t dma; /* device address of pushbuffer */ 36*4882a593Smuzhiyun dma_addr_t phys; /* physical address of pushbuffer */ 37*4882a593Smuzhiyun u32 fence; /* index we've written */ 38*4882a593Smuzhiyun u32 pos; /* index to write to */ 39*4882a593Smuzhiyun u32 size; 40*4882a593Smuzhiyun u32 alloc_size; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct buffer_timeout { 44*4882a593Smuzhiyun struct delayed_work wq; /* work queue */ 45*4882a593Smuzhiyun bool initialized; /* timer one-time setup flag */ 46*4882a593Smuzhiyun struct host1x_syncpt *syncpt; /* buffer completion syncpt */ 47*4882a593Smuzhiyun u32 syncpt_val; /* syncpt value when completed */ 48*4882a593Smuzhiyun ktime_t start_ktime; /* starting time */ 49*4882a593Smuzhiyun /* context timeout information */ 50*4882a593Smuzhiyun struct host1x_client *client; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun enum cdma_event { 54*4882a593Smuzhiyun CDMA_EVENT_NONE, /* not waiting for any event */ 55*4882a593Smuzhiyun CDMA_EVENT_SYNC_QUEUE_EMPTY, /* wait for empty sync queue */ 56*4882a593Smuzhiyun CDMA_EVENT_PUSH_BUFFER_SPACE /* wait for space in push buffer */ 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct host1x_cdma { 60*4882a593Smuzhiyun struct mutex lock; /* controls access to shared state */ 61*4882a593Smuzhiyun struct completion complete; /* signalled when event occurs */ 62*4882a593Smuzhiyun enum cdma_event event; /* event that complete is waiting for */ 63*4882a593Smuzhiyun unsigned int slots_used; /* pb slots used in current submit */ 64*4882a593Smuzhiyun unsigned int slots_free; /* pb slots free in current submit */ 65*4882a593Smuzhiyun unsigned int first_get; /* DMAGET value, where submit begins */ 66*4882a593Smuzhiyun unsigned int last_pos; /* last value written to DMAPUT */ 67*4882a593Smuzhiyun struct push_buffer push_buffer; /* channel's push buffer */ 68*4882a593Smuzhiyun struct list_head sync_queue; /* job queue */ 69*4882a593Smuzhiyun struct buffer_timeout timeout; /* channel's timeout state/wq */ 70*4882a593Smuzhiyun bool running; 71*4882a593Smuzhiyun bool torndown; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define cdma_to_channel(cdma) container_of(cdma, struct host1x_channel, cdma) 75*4882a593Smuzhiyun #define cdma_to_host1x(cdma) dev_get_drvdata(cdma_to_channel(cdma)->dev->parent) 76*4882a593Smuzhiyun #define pb_to_cdma(pb) container_of(pb, struct host1x_cdma, push_buffer) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun int host1x_cdma_init(struct host1x_cdma *cdma); 79*4882a593Smuzhiyun int host1x_cdma_deinit(struct host1x_cdma *cdma); 80*4882a593Smuzhiyun int host1x_cdma_begin(struct host1x_cdma *cdma, struct host1x_job *job); 81*4882a593Smuzhiyun void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2); 82*4882a593Smuzhiyun void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2, 83*4882a593Smuzhiyun u32 op3, u32 op4); 84*4882a593Smuzhiyun void host1x_cdma_end(struct host1x_cdma *cdma, struct host1x_job *job); 85*4882a593Smuzhiyun void host1x_cdma_update(struct host1x_cdma *cdma); 86*4882a593Smuzhiyun void host1x_cdma_peek(struct host1x_cdma *cdma, u32 dmaget, int slot, 87*4882a593Smuzhiyun u32 *out); 88*4882a593Smuzhiyun unsigned int host1x_cdma_wait_locked(struct host1x_cdma *cdma, 89*4882a593Smuzhiyun enum cdma_event event); 90*4882a593Smuzhiyun void host1x_cdma_update_sync_queue(struct host1x_cdma *cdma, 91*4882a593Smuzhiyun struct device *dev); 92*4882a593Smuzhiyun #endif 93