1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Linaro Ltd. 4*4882a593Smuzhiyun * Copyright 2016 ZTE Corporation. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ZX_VOU_H__ 8*4882a593Smuzhiyun #define __ZX_VOU_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define VOU_CRTC_MASK 0x3 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* VOU output interfaces */ 13*4882a593Smuzhiyun enum vou_inf_id { 14*4882a593Smuzhiyun VOU_HDMI = 0, 15*4882a593Smuzhiyun VOU_RGB_LCD = 1, 16*4882a593Smuzhiyun VOU_TV_ENC = 2, 17*4882a593Smuzhiyun VOU_MIPI_DSI = 3, 18*4882a593Smuzhiyun VOU_LVDS = 4, 19*4882a593Smuzhiyun VOU_VGA = 5, 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun enum vou_inf_hdmi_audio { 23*4882a593Smuzhiyun VOU_HDMI_AUD_SPDIF = BIT(0), 24*4882a593Smuzhiyun VOU_HDMI_AUD_I2S = BIT(1), 25*4882a593Smuzhiyun VOU_HDMI_AUD_DSD = BIT(2), 26*4882a593Smuzhiyun VOU_HDMI_AUD_HBR = BIT(3), 27*4882a593Smuzhiyun VOU_HDMI_AUD_PARALLEL = BIT(4), 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun void vou_inf_hdmi_audio_sel(struct drm_crtc *crtc, 31*4882a593Smuzhiyun enum vou_inf_hdmi_audio aud); 32*4882a593Smuzhiyun void vou_inf_enable(enum vou_inf_id id, struct drm_crtc *crtc); 33*4882a593Smuzhiyun void vou_inf_disable(enum vou_inf_id id, struct drm_crtc *crtc); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun enum vou_div_id { 36*4882a593Smuzhiyun VOU_DIV_VGA, 37*4882a593Smuzhiyun VOU_DIV_PIC, 38*4882a593Smuzhiyun VOU_DIV_TVENC, 39*4882a593Smuzhiyun VOU_DIV_HDMI_PNX, 40*4882a593Smuzhiyun VOU_DIV_HDMI, 41*4882a593Smuzhiyun VOU_DIV_INF, 42*4882a593Smuzhiyun VOU_DIV_LAYER, 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun enum vou_div_val { 46*4882a593Smuzhiyun VOU_DIV_1 = 0, 47*4882a593Smuzhiyun VOU_DIV_2 = 1, 48*4882a593Smuzhiyun VOU_DIV_4 = 3, 49*4882a593Smuzhiyun VOU_DIV_8 = 7, 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct vou_div_config { 53*4882a593Smuzhiyun enum vou_div_id id; 54*4882a593Smuzhiyun enum vou_div_val val; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun void zx_vou_config_dividers(struct drm_crtc *crtc, 58*4882a593Smuzhiyun struct vou_div_config *configs, int num); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun void zx_vou_layer_enable(struct drm_plane *plane); 61*4882a593Smuzhiyun void zx_vou_layer_disable(struct drm_plane *plane, 62*4882a593Smuzhiyun struct drm_plane_state *old_state); 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* __ZX_VOU_H__ */ 65