1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2017 Sanechips Technology Co., Ltd. 4*4882a593Smuzhiyun * Copyright 2017 Linaro Ltd. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ZX_VGA_REGS_H__ 8*4882a593Smuzhiyun #define __ZX_VGA_REGS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define VGA_CMD_CFG 0x04 11*4882a593Smuzhiyun #define VGA_CMD_TRANS BIT(6) 12*4882a593Smuzhiyun #define VGA_CMD_COMBO BIT(5) 13*4882a593Smuzhiyun #define VGA_CMD_RW BIT(4) 14*4882a593Smuzhiyun #define VGA_SUB_ADDR 0x0c 15*4882a593Smuzhiyun #define VGA_DEVICE_ADDR 0x10 16*4882a593Smuzhiyun #define VGA_CLK_DIV_FS 0x14 17*4882a593Smuzhiyun #define VGA_RXF_CTRL 0x20 18*4882a593Smuzhiyun #define VGA_RX_FIFO_CLEAR BIT(7) 19*4882a593Smuzhiyun #define VGA_DATA 0x24 20*4882a593Smuzhiyun #define VGA_I2C_STATUS 0x28 21*4882a593Smuzhiyun #define VGA_DEVICE_DISCONNECTED BIT(7) 22*4882a593Smuzhiyun #define VGA_DEVICE_CONNECTED BIT(6) 23*4882a593Smuzhiyun #define VGA_CLEAR_IRQ BIT(4) 24*4882a593Smuzhiyun #define VGA_TRANS_DONE BIT(0) 25*4882a593Smuzhiyun #define VGA_RXF_STATUS 0x30 26*4882a593Smuzhiyun #define VGA_RXF_COUNT_SHIFT 2 27*4882a593Smuzhiyun #define VGA_RXF_COUNT_MASK GENMASK(7, 2) 28*4882a593Smuzhiyun #define VGA_AUTO_DETECT_PARA 0x34 29*4882a593Smuzhiyun #define VGA_AUTO_DETECT_SEL 0x38 30*4882a593Smuzhiyun #define VGA_DETECT_SEL_HAS_DEVICE BIT(1) 31*4882a593Smuzhiyun #define VGA_DETECT_SEL_NO_DEVICE BIT(0) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif /* __ZX_VGA_REGS_H__ */ 34