xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/zte/zx_vga.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2017 Sanechips Technology Co., Ltd.
4*4882a593Smuzhiyun  * Copyright 2017 Linaro Ltd.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/clk.h>
8*4882a593Smuzhiyun #include <linux/component.h>
9*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
15*4882a593Smuzhiyun #include <drm/drm_print.h>
16*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
17*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include "zx_drm_drv.h"
20*4882a593Smuzhiyun #include "zx_vga_regs.h"
21*4882a593Smuzhiyun #include "zx_vou.h"
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun struct zx_vga_pwrctrl {
24*4882a593Smuzhiyun 	struct regmap *regmap;
25*4882a593Smuzhiyun 	u32 reg;
26*4882a593Smuzhiyun 	u32 mask;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun struct zx_vga_i2c {
30*4882a593Smuzhiyun 	struct i2c_adapter adap;
31*4882a593Smuzhiyun 	struct mutex lock;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun struct zx_vga {
35*4882a593Smuzhiyun 	struct drm_connector connector;
36*4882a593Smuzhiyun 	struct drm_encoder encoder;
37*4882a593Smuzhiyun 	struct zx_vga_i2c *ddc;
38*4882a593Smuzhiyun 	struct device *dev;
39*4882a593Smuzhiyun 	void __iomem *mmio;
40*4882a593Smuzhiyun 	struct clk *i2c_wclk;
41*4882a593Smuzhiyun 	struct zx_vga_pwrctrl pwrctrl;
42*4882a593Smuzhiyun 	struct completion complete;
43*4882a593Smuzhiyun 	bool connected;
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define to_zx_vga(x) container_of(x, struct zx_vga, x)
47*4882a593Smuzhiyun 
zx_vga_encoder_enable(struct drm_encoder * encoder)48*4882a593Smuzhiyun static void zx_vga_encoder_enable(struct drm_encoder *encoder)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun 	struct zx_vga *vga = to_zx_vga(encoder);
51*4882a593Smuzhiyun 	struct zx_vga_pwrctrl *pwrctrl = &vga->pwrctrl;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	/* Set bit to power up VGA DACs */
54*4882a593Smuzhiyun 	regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask,
55*4882a593Smuzhiyun 			   pwrctrl->mask);
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	vou_inf_enable(VOU_VGA, encoder->crtc);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
zx_vga_encoder_disable(struct drm_encoder * encoder)60*4882a593Smuzhiyun static void zx_vga_encoder_disable(struct drm_encoder *encoder)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun 	struct zx_vga *vga = to_zx_vga(encoder);
63*4882a593Smuzhiyun 	struct zx_vga_pwrctrl *pwrctrl = &vga->pwrctrl;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	vou_inf_disable(VOU_VGA, encoder->crtc);
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	/* Clear bit to power down VGA DACs */
68*4882a593Smuzhiyun 	regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, 0);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs zx_vga_encoder_helper_funcs = {
72*4882a593Smuzhiyun 	.enable	= zx_vga_encoder_enable,
73*4882a593Smuzhiyun 	.disable = zx_vga_encoder_disable,
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
zx_vga_connector_get_modes(struct drm_connector * connector)76*4882a593Smuzhiyun static int zx_vga_connector_get_modes(struct drm_connector *connector)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	struct zx_vga *vga = to_zx_vga(connector);
79*4882a593Smuzhiyun 	struct edid *edid;
80*4882a593Smuzhiyun 	int ret;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	/*
83*4882a593Smuzhiyun 	 * Clear both detection bits to switch I2C bus from device
84*4882a593Smuzhiyun 	 * detecting to EDID reading.
85*4882a593Smuzhiyun 	 */
86*4882a593Smuzhiyun 	zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, 0);
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	edid = drm_get_edid(connector, &vga->ddc->adap);
89*4882a593Smuzhiyun 	if (!edid) {
90*4882a593Smuzhiyun 		/*
91*4882a593Smuzhiyun 		 * If EDID reading fails, we set the device state into
92*4882a593Smuzhiyun 		 * disconnected.  Locking is not required here, since the
93*4882a593Smuzhiyun 		 * VGA_AUTO_DETECT_SEL register write in irq handler cannot
94*4882a593Smuzhiyun 		 * be triggered when both detection bits are cleared as above.
95*4882a593Smuzhiyun 		 */
96*4882a593Smuzhiyun 		zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL,
97*4882a593Smuzhiyun 			  VGA_DETECT_SEL_NO_DEVICE);
98*4882a593Smuzhiyun 		vga->connected = false;
99*4882a593Smuzhiyun 		return 0;
100*4882a593Smuzhiyun 	}
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	/*
103*4882a593Smuzhiyun 	 * As edid reading succeeds, device must be connected, so we set
104*4882a593Smuzhiyun 	 * up detection bit for unplug interrupt here.
105*4882a593Smuzhiyun 	 */
106*4882a593Smuzhiyun 	zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, VGA_DETECT_SEL_HAS_DEVICE);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	drm_connector_update_edid_property(connector, edid);
109*4882a593Smuzhiyun 	ret = drm_add_edid_modes(connector, edid);
110*4882a593Smuzhiyun 	kfree(edid);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	return ret;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun static enum drm_mode_status
zx_vga_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)116*4882a593Smuzhiyun zx_vga_connector_mode_valid(struct drm_connector *connector,
117*4882a593Smuzhiyun 			    struct drm_display_mode *mode)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	return MODE_OK;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun static struct drm_connector_helper_funcs zx_vga_connector_helper_funcs = {
123*4882a593Smuzhiyun 	.get_modes = zx_vga_connector_get_modes,
124*4882a593Smuzhiyun 	.mode_valid = zx_vga_connector_mode_valid,
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun static enum drm_connector_status
zx_vga_connector_detect(struct drm_connector * connector,bool force)128*4882a593Smuzhiyun zx_vga_connector_detect(struct drm_connector *connector, bool force)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun 	struct zx_vga *vga = to_zx_vga(connector);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	return vga->connected ? connector_status_connected :
133*4882a593Smuzhiyun 				connector_status_disconnected;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun static const struct drm_connector_funcs zx_vga_connector_funcs = {
137*4882a593Smuzhiyun 	.fill_modes = drm_helper_probe_single_connector_modes,
138*4882a593Smuzhiyun 	.detect = zx_vga_connector_detect,
139*4882a593Smuzhiyun 	.destroy = drm_connector_cleanup,
140*4882a593Smuzhiyun 	.reset = drm_atomic_helper_connector_reset,
141*4882a593Smuzhiyun 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
142*4882a593Smuzhiyun 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun 
zx_vga_register(struct drm_device * drm,struct zx_vga * vga)145*4882a593Smuzhiyun static int zx_vga_register(struct drm_device *drm, struct zx_vga *vga)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun 	struct drm_encoder *encoder = &vga->encoder;
148*4882a593Smuzhiyun 	struct drm_connector *connector = &vga->connector;
149*4882a593Smuzhiyun 	struct device *dev = vga->dev;
150*4882a593Smuzhiyun 	int ret;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	encoder->possible_crtcs = VOU_CRTC_MASK;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_DAC);
155*4882a593Smuzhiyun 	if (ret) {
156*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to init encoder: %d\n", ret);
157*4882a593Smuzhiyun 		return ret;
158*4882a593Smuzhiyun 	}
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	drm_encoder_helper_add(encoder, &zx_vga_encoder_helper_funcs);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	vga->connector.polled = DRM_CONNECTOR_POLL_HPD;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	ret = drm_connector_init_with_ddc(drm, connector,
165*4882a593Smuzhiyun 					  &zx_vga_connector_funcs,
166*4882a593Smuzhiyun 					  DRM_MODE_CONNECTOR_VGA,
167*4882a593Smuzhiyun 					  &vga->ddc->adap);
168*4882a593Smuzhiyun 	if (ret) {
169*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to init connector: %d\n", ret);
170*4882a593Smuzhiyun 		goto clean_encoder;
171*4882a593Smuzhiyun 	}
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	drm_connector_helper_add(connector, &zx_vga_connector_helper_funcs);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	ret = drm_connector_attach_encoder(connector, encoder);
176*4882a593Smuzhiyun 	if (ret) {
177*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to attach encoder: %d\n", ret);
178*4882a593Smuzhiyun 		goto clean_connector;
179*4882a593Smuzhiyun 	}
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	return 0;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun clean_connector:
184*4882a593Smuzhiyun 	drm_connector_cleanup(connector);
185*4882a593Smuzhiyun clean_encoder:
186*4882a593Smuzhiyun 	drm_encoder_cleanup(encoder);
187*4882a593Smuzhiyun 	return ret;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun 
zx_vga_pwrctrl_init(struct zx_vga * vga)190*4882a593Smuzhiyun static int zx_vga_pwrctrl_init(struct zx_vga *vga)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun 	struct zx_vga_pwrctrl *pwrctrl = &vga->pwrctrl;
193*4882a593Smuzhiyun 	struct device *dev = vga->dev;
194*4882a593Smuzhiyun 	struct of_phandle_args out_args;
195*4882a593Smuzhiyun 	struct regmap *regmap;
196*4882a593Smuzhiyun 	int ret;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	ret = of_parse_phandle_with_fixed_args(dev->of_node,
199*4882a593Smuzhiyun 				"zte,vga-power-control", 2, 0, &out_args);
200*4882a593Smuzhiyun 	if (ret)
201*4882a593Smuzhiyun 		return ret;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	regmap = syscon_node_to_regmap(out_args.np);
204*4882a593Smuzhiyun 	if (IS_ERR(regmap)) {
205*4882a593Smuzhiyun 		ret = PTR_ERR(regmap);
206*4882a593Smuzhiyun 		goto out;
207*4882a593Smuzhiyun 	}
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	pwrctrl->regmap = regmap;
210*4882a593Smuzhiyun 	pwrctrl->reg = out_args.args[0];
211*4882a593Smuzhiyun 	pwrctrl->mask = out_args.args[1];
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun out:
214*4882a593Smuzhiyun 	of_node_put(out_args.np);
215*4882a593Smuzhiyun 	return ret;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun 
zx_vga_i2c_read(struct zx_vga * vga,struct i2c_msg * msg)218*4882a593Smuzhiyun static int zx_vga_i2c_read(struct zx_vga *vga, struct i2c_msg *msg)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun 	int len = msg->len;
221*4882a593Smuzhiyun 	u8 *buf = msg->buf;
222*4882a593Smuzhiyun 	u32 offset = 0;
223*4882a593Smuzhiyun 	int i;
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	reinit_completion(&vga->complete);
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	/* Select combo write */
228*4882a593Smuzhiyun 	zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_COMBO, VGA_CMD_COMBO);
229*4882a593Smuzhiyun 	zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_RW, 0);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	while (len > 0) {
232*4882a593Smuzhiyun 		u32 cnt;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 		/* Clear RX FIFO */
235*4882a593Smuzhiyun 		zx_writel_mask(vga->mmio + VGA_RXF_CTRL, VGA_RX_FIFO_CLEAR,
236*4882a593Smuzhiyun 			       VGA_RX_FIFO_CLEAR);
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 		/* Data offset to read from */
239*4882a593Smuzhiyun 		zx_writel(vga->mmio + VGA_SUB_ADDR, offset);
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 		/* Kick off the transfer */
242*4882a593Smuzhiyun 		zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_TRANS,
243*4882a593Smuzhiyun 			       VGA_CMD_TRANS);
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 		if (!wait_for_completion_timeout(&vga->complete,
246*4882a593Smuzhiyun 						 msecs_to_jiffies(1000))) {
247*4882a593Smuzhiyun 			DRM_DEV_ERROR(vga->dev, "transfer timeout\n");
248*4882a593Smuzhiyun 			return -ETIMEDOUT;
249*4882a593Smuzhiyun 		}
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 		cnt = zx_readl(vga->mmio + VGA_RXF_STATUS);
252*4882a593Smuzhiyun 		cnt = (cnt & VGA_RXF_COUNT_MASK) >> VGA_RXF_COUNT_SHIFT;
253*4882a593Smuzhiyun 		/* FIFO status may report more data than we need to read */
254*4882a593Smuzhiyun 		cnt = min_t(u32, len, cnt);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 		for (i = 0; i < cnt; i++)
257*4882a593Smuzhiyun 			*buf++ = zx_readl(vga->mmio + VGA_DATA);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 		len -= cnt;
260*4882a593Smuzhiyun 		offset += cnt;
261*4882a593Smuzhiyun 	}
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	return 0;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun 
zx_vga_i2c_write(struct zx_vga * vga,struct i2c_msg * msg)266*4882a593Smuzhiyun static int zx_vga_i2c_write(struct zx_vga *vga, struct i2c_msg *msg)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun 	/*
269*4882a593Smuzhiyun 	 * The DDC I2C adapter is only for reading EDID data, so we assume
270*4882a593Smuzhiyun 	 * that the write to this adapter must be the EDID data offset.
271*4882a593Smuzhiyun 	 */
272*4882a593Smuzhiyun 	if ((msg->len != 1) || ((msg->addr != DDC_ADDR)))
273*4882a593Smuzhiyun 		return -EINVAL;
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	/* Hardware will take care of the slave address shifting */
276*4882a593Smuzhiyun 	zx_writel(vga->mmio + VGA_DEVICE_ADDR, msg->addr);
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	return 0;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun 
zx_vga_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)281*4882a593Smuzhiyun static int zx_vga_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
282*4882a593Smuzhiyun 			   int num)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun 	struct zx_vga *vga = i2c_get_adapdata(adap);
285*4882a593Smuzhiyun 	struct zx_vga_i2c *ddc = vga->ddc;
286*4882a593Smuzhiyun 	int ret = 0;
287*4882a593Smuzhiyun 	int i;
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	mutex_lock(&ddc->lock);
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	for (i = 0; i < num; i++) {
292*4882a593Smuzhiyun 		if (msgs[i].flags & I2C_M_RD)
293*4882a593Smuzhiyun 			ret = zx_vga_i2c_read(vga, &msgs[i]);
294*4882a593Smuzhiyun 		else
295*4882a593Smuzhiyun 			ret = zx_vga_i2c_write(vga, &msgs[i]);
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 		if (ret < 0)
298*4882a593Smuzhiyun 			break;
299*4882a593Smuzhiyun 	}
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	if (!ret)
302*4882a593Smuzhiyun 		ret = num;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	mutex_unlock(&ddc->lock);
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	return ret;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun 
zx_vga_i2c_func(struct i2c_adapter * adapter)309*4882a593Smuzhiyun static u32 zx_vga_i2c_func(struct i2c_adapter *adapter)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun static const struct i2c_algorithm zx_vga_algorithm = {
315*4882a593Smuzhiyun 	.master_xfer	= zx_vga_i2c_xfer,
316*4882a593Smuzhiyun 	.functionality	= zx_vga_i2c_func,
317*4882a593Smuzhiyun };
318*4882a593Smuzhiyun 
zx_vga_ddc_register(struct zx_vga * vga)319*4882a593Smuzhiyun static int zx_vga_ddc_register(struct zx_vga *vga)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun 	struct device *dev = vga->dev;
322*4882a593Smuzhiyun 	struct i2c_adapter *adap;
323*4882a593Smuzhiyun 	struct zx_vga_i2c *ddc;
324*4882a593Smuzhiyun 	int ret;
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
327*4882a593Smuzhiyun 	if (!ddc)
328*4882a593Smuzhiyun 		return -ENOMEM;
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	vga->ddc = ddc;
331*4882a593Smuzhiyun 	mutex_init(&ddc->lock);
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	adap = &ddc->adap;
334*4882a593Smuzhiyun 	adap->owner = THIS_MODULE;
335*4882a593Smuzhiyun 	adap->class = I2C_CLASS_DDC;
336*4882a593Smuzhiyun 	adap->dev.parent = dev;
337*4882a593Smuzhiyun 	adap->algo = &zx_vga_algorithm;
338*4882a593Smuzhiyun 	snprintf(adap->name, sizeof(adap->name), "zx vga i2c");
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	ret = i2c_add_adapter(adap);
341*4882a593Smuzhiyun 	if (ret) {
342*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to add I2C adapter: %d\n", ret);
343*4882a593Smuzhiyun 		return ret;
344*4882a593Smuzhiyun 	}
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	i2c_set_adapdata(adap, vga);
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	return 0;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun 
zx_vga_irq_thread(int irq,void * dev_id)351*4882a593Smuzhiyun static irqreturn_t zx_vga_irq_thread(int irq, void *dev_id)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	struct zx_vga *vga = dev_id;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	drm_helper_hpd_irq_event(vga->connector.dev);
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	return IRQ_HANDLED;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun 
zx_vga_irq_handler(int irq,void * dev_id)360*4882a593Smuzhiyun static irqreturn_t zx_vga_irq_handler(int irq, void *dev_id)
361*4882a593Smuzhiyun {
362*4882a593Smuzhiyun 	struct zx_vga *vga = dev_id;
363*4882a593Smuzhiyun 	u32 status;
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	status = zx_readl(vga->mmio + VGA_I2C_STATUS);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	/* Clear interrupt status */
368*4882a593Smuzhiyun 	zx_writel_mask(vga->mmio + VGA_I2C_STATUS, VGA_CLEAR_IRQ,
369*4882a593Smuzhiyun 		       VGA_CLEAR_IRQ);
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	if (status & VGA_DEVICE_CONNECTED) {
372*4882a593Smuzhiyun 		/*
373*4882a593Smuzhiyun 		 * Since VGA_DETECT_SEL bits need to be reset for switching DDC
374*4882a593Smuzhiyun 		 * bus from device detection to EDID read, rather than setting
375*4882a593Smuzhiyun 		 * up HAS_DEVICE bit here, we need to do that in .get_modes
376*4882a593Smuzhiyun 		 * hook for unplug detecting after EDID read succeeds.
377*4882a593Smuzhiyun 		 */
378*4882a593Smuzhiyun 		vga->connected = true;
379*4882a593Smuzhiyun 		return IRQ_WAKE_THREAD;
380*4882a593Smuzhiyun 	}
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	if (status & VGA_DEVICE_DISCONNECTED) {
383*4882a593Smuzhiyun 		zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL,
384*4882a593Smuzhiyun 			  VGA_DETECT_SEL_NO_DEVICE);
385*4882a593Smuzhiyun 		vga->connected = false;
386*4882a593Smuzhiyun 		return IRQ_WAKE_THREAD;
387*4882a593Smuzhiyun 	}
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	if (status & VGA_TRANS_DONE) {
390*4882a593Smuzhiyun 		complete(&vga->complete);
391*4882a593Smuzhiyun 		return IRQ_HANDLED;
392*4882a593Smuzhiyun 	}
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	return IRQ_NONE;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun 
zx_vga_hw_init(struct zx_vga * vga)397*4882a593Smuzhiyun static void zx_vga_hw_init(struct zx_vga *vga)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun 	unsigned long ref = clk_get_rate(vga->i2c_wclk);
400*4882a593Smuzhiyun 	int div;
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	/*
403*4882a593Smuzhiyun 	 * Set up I2C fast speed divider per formula below to get 400kHz.
404*4882a593Smuzhiyun 	 *   scl = ref / ((div + 1) * 4)
405*4882a593Smuzhiyun 	 */
406*4882a593Smuzhiyun 	div = DIV_ROUND_UP(ref / 1000, 400 * 4) - 1;
407*4882a593Smuzhiyun 	zx_writel(vga->mmio + VGA_CLK_DIV_FS, div);
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	/* Set up device detection */
410*4882a593Smuzhiyun 	zx_writel(vga->mmio + VGA_AUTO_DETECT_PARA, 0x80);
411*4882a593Smuzhiyun 	zx_writel(vga->mmio + VGA_AUTO_DETECT_SEL, VGA_DETECT_SEL_NO_DEVICE);
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	/*
414*4882a593Smuzhiyun 	 * We need to poke monitor via DDC bus to get connection irq
415*4882a593Smuzhiyun 	 * start working.
416*4882a593Smuzhiyun 	 */
417*4882a593Smuzhiyun 	zx_writel(vga->mmio + VGA_DEVICE_ADDR, DDC_ADDR);
418*4882a593Smuzhiyun 	zx_writel_mask(vga->mmio + VGA_CMD_CFG, VGA_CMD_TRANS, VGA_CMD_TRANS);
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun 
zx_vga_bind(struct device * dev,struct device * master,void * data)421*4882a593Smuzhiyun static int zx_vga_bind(struct device *dev, struct device *master, void *data)
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun 	struct platform_device *pdev = to_platform_device(dev);
424*4882a593Smuzhiyun 	struct drm_device *drm = data;
425*4882a593Smuzhiyun 	struct resource *res;
426*4882a593Smuzhiyun 	struct zx_vga *vga;
427*4882a593Smuzhiyun 	int irq;
428*4882a593Smuzhiyun 	int ret;
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	vga = devm_kzalloc(dev, sizeof(*vga), GFP_KERNEL);
431*4882a593Smuzhiyun 	if (!vga)
432*4882a593Smuzhiyun 		return -ENOMEM;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	vga->dev = dev;
435*4882a593Smuzhiyun 	dev_set_drvdata(dev, vga);
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
438*4882a593Smuzhiyun 	vga->mmio = devm_ioremap_resource(dev, res);
439*4882a593Smuzhiyun 	if (IS_ERR(vga->mmio))
440*4882a593Smuzhiyun 		return PTR_ERR(vga->mmio);
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
443*4882a593Smuzhiyun 	if (irq < 0)
444*4882a593Smuzhiyun 		return irq;
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	vga->i2c_wclk = devm_clk_get(dev, "i2c_wclk");
447*4882a593Smuzhiyun 	if (IS_ERR(vga->i2c_wclk)) {
448*4882a593Smuzhiyun 		ret = PTR_ERR(vga->i2c_wclk);
449*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to get i2c_wclk: %d\n", ret);
450*4882a593Smuzhiyun 		return ret;
451*4882a593Smuzhiyun 	}
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	ret = zx_vga_pwrctrl_init(vga);
454*4882a593Smuzhiyun 	if (ret) {
455*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to init power control: %d\n", ret);
456*4882a593Smuzhiyun 		return ret;
457*4882a593Smuzhiyun 	}
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	ret = zx_vga_ddc_register(vga);
460*4882a593Smuzhiyun 	if (ret) {
461*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to register ddc: %d\n", ret);
462*4882a593Smuzhiyun 		return ret;
463*4882a593Smuzhiyun 	}
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	ret = zx_vga_register(drm, vga);
466*4882a593Smuzhiyun 	if (ret) {
467*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to register vga: %d\n", ret);
468*4882a593Smuzhiyun 		return ret;
469*4882a593Smuzhiyun 	}
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	init_completion(&vga->complete);
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 	ret = devm_request_threaded_irq(dev, irq, zx_vga_irq_handler,
474*4882a593Smuzhiyun 					zx_vga_irq_thread, IRQF_SHARED,
475*4882a593Smuzhiyun 					dev_name(dev), vga);
476*4882a593Smuzhiyun 	if (ret) {
477*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to request threaded irq: %d\n", ret);
478*4882a593Smuzhiyun 		return ret;
479*4882a593Smuzhiyun 	}
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	ret = clk_prepare_enable(vga->i2c_wclk);
482*4882a593Smuzhiyun 	if (ret)
483*4882a593Smuzhiyun 		return ret;
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	zx_vga_hw_init(vga);
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun 	return 0;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun 
zx_vga_unbind(struct device * dev,struct device * master,void * data)490*4882a593Smuzhiyun static void zx_vga_unbind(struct device *dev, struct device *master,
491*4882a593Smuzhiyun 			  void *data)
492*4882a593Smuzhiyun {
493*4882a593Smuzhiyun 	struct zx_vga *vga = dev_get_drvdata(dev);
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	clk_disable_unprepare(vga->i2c_wclk);
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun static const struct component_ops zx_vga_component_ops = {
499*4882a593Smuzhiyun 	.bind = zx_vga_bind,
500*4882a593Smuzhiyun 	.unbind = zx_vga_unbind,
501*4882a593Smuzhiyun };
502*4882a593Smuzhiyun 
zx_vga_probe(struct platform_device * pdev)503*4882a593Smuzhiyun static int zx_vga_probe(struct platform_device *pdev)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun 	return component_add(&pdev->dev, &zx_vga_component_ops);
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun 
zx_vga_remove(struct platform_device * pdev)508*4882a593Smuzhiyun static int zx_vga_remove(struct platform_device *pdev)
509*4882a593Smuzhiyun {
510*4882a593Smuzhiyun 	component_del(&pdev->dev, &zx_vga_component_ops);
511*4882a593Smuzhiyun 	return 0;
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun static const struct of_device_id zx_vga_of_match[] = {
515*4882a593Smuzhiyun 	{ .compatible = "zte,zx296718-vga", },
516*4882a593Smuzhiyun 	{ /* end */ },
517*4882a593Smuzhiyun };
518*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, zx_vga_of_match);
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun struct platform_driver zx_vga_driver = {
521*4882a593Smuzhiyun 	.probe = zx_vga_probe,
522*4882a593Smuzhiyun 	.remove = zx_vga_remove,
523*4882a593Smuzhiyun 	.driver	= {
524*4882a593Smuzhiyun 		.name = "zx-vga",
525*4882a593Smuzhiyun 		.of_match_table	= zx_vga_of_match,
526*4882a593Smuzhiyun 	},
527*4882a593Smuzhiyun };
528