xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/zte/zx_tvenc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 2017 Linaro Ltd.
4*4882a593Smuzhiyun  * Copyright 2017 ZTE Corporation.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/clk.h>
8*4882a593Smuzhiyun #include <linux/component.h>
9*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
15*4882a593Smuzhiyun #include <drm/drm_print.h>
16*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
17*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include "zx_drm_drv.h"
20*4882a593Smuzhiyun #include "zx_tvenc_regs.h"
21*4882a593Smuzhiyun #include "zx_vou.h"
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun struct zx_tvenc_pwrctrl {
24*4882a593Smuzhiyun 	struct regmap *regmap;
25*4882a593Smuzhiyun 	u32 reg;
26*4882a593Smuzhiyun 	u32 mask;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun struct zx_tvenc {
30*4882a593Smuzhiyun 	struct drm_connector connector;
31*4882a593Smuzhiyun 	struct drm_encoder encoder;
32*4882a593Smuzhiyun 	struct device *dev;
33*4882a593Smuzhiyun 	void __iomem *mmio;
34*4882a593Smuzhiyun 	const struct vou_inf *inf;
35*4882a593Smuzhiyun 	struct zx_tvenc_pwrctrl pwrctrl;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define to_zx_tvenc(x) container_of(x, struct zx_tvenc, x)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun struct zx_tvenc_mode {
41*4882a593Smuzhiyun 	struct drm_display_mode mode;
42*4882a593Smuzhiyun 	u32 video_info;
43*4882a593Smuzhiyun 	u32 video_res;
44*4882a593Smuzhiyun 	u32 field1_param;
45*4882a593Smuzhiyun 	u32 field2_param;
46*4882a593Smuzhiyun 	u32 burst_line_odd1;
47*4882a593Smuzhiyun 	u32 burst_line_even1;
48*4882a593Smuzhiyun 	u32 burst_line_odd2;
49*4882a593Smuzhiyun 	u32 burst_line_even2;
50*4882a593Smuzhiyun 	u32 line_timing_param;
51*4882a593Smuzhiyun 	u32 weight_value;
52*4882a593Smuzhiyun 	u32 blank_black_level;
53*4882a593Smuzhiyun 	u32 burst_level;
54*4882a593Smuzhiyun 	u32 control_param;
55*4882a593Smuzhiyun 	u32 sub_carrier_phase1;
56*4882a593Smuzhiyun 	u32 phase_line_incr_cvbs;
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun  * The CRM cannot directly provide a suitable frequency, and we have to
61*4882a593Smuzhiyun  * ask a multiplied rate from CRM and use the divider in VOU to get the
62*4882a593Smuzhiyun  * desired one.
63*4882a593Smuzhiyun  */
64*4882a593Smuzhiyun #define TVENC_CLOCK_MULTIPLIER	4
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun static const struct zx_tvenc_mode tvenc_mode_pal = {
67*4882a593Smuzhiyun 	.mode = {
68*4882a593Smuzhiyun 		.clock = 13500 * TVENC_CLOCK_MULTIPLIER,
69*4882a593Smuzhiyun 		.hdisplay = 720,
70*4882a593Smuzhiyun 		.hsync_start = 720 + 12,
71*4882a593Smuzhiyun 		.hsync_end = 720 + 12 + 2,
72*4882a593Smuzhiyun 		.htotal = 720 + 12 + 2 + 130,
73*4882a593Smuzhiyun 		.vdisplay = 576,
74*4882a593Smuzhiyun 		.vsync_start = 576 + 2,
75*4882a593Smuzhiyun 		.vsync_end = 576 + 2 + 2,
76*4882a593Smuzhiyun 		.vtotal = 576 + 2 + 2 + 20,
77*4882a593Smuzhiyun 		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
78*4882a593Smuzhiyun 			 DRM_MODE_FLAG_INTERLACE,
79*4882a593Smuzhiyun 	},
80*4882a593Smuzhiyun 	.video_info = 0x00040040,
81*4882a593Smuzhiyun 	.video_res = 0x05a9c760,
82*4882a593Smuzhiyun 	.field1_param = 0x0004d416,
83*4882a593Smuzhiyun 	.field2_param = 0x0009b94f,
84*4882a593Smuzhiyun 	.burst_line_odd1 = 0x0004d406,
85*4882a593Smuzhiyun 	.burst_line_even1 = 0x0009b53e,
86*4882a593Smuzhiyun 	.burst_line_odd2 = 0x0004d805,
87*4882a593Smuzhiyun 	.burst_line_even2 = 0x0009b93f,
88*4882a593Smuzhiyun 	.line_timing_param = 0x06a96fdf,
89*4882a593Smuzhiyun 	.weight_value = 0x00c188a0,
90*4882a593Smuzhiyun 	.blank_black_level = 0x0000fcfc,
91*4882a593Smuzhiyun 	.burst_level = 0x00001595,
92*4882a593Smuzhiyun 	.control_param = 0x00000001,
93*4882a593Smuzhiyun 	.sub_carrier_phase1 = 0x1504c566,
94*4882a593Smuzhiyun 	.phase_line_incr_cvbs = 0xc068db8c,
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun static const struct zx_tvenc_mode tvenc_mode_ntsc = {
98*4882a593Smuzhiyun 	.mode = {
99*4882a593Smuzhiyun 		.clock = 13500 * TVENC_CLOCK_MULTIPLIER,
100*4882a593Smuzhiyun 		.hdisplay = 720,
101*4882a593Smuzhiyun 		.hsync_start = 720 + 16,
102*4882a593Smuzhiyun 		.hsync_end = 720 + 16 + 2,
103*4882a593Smuzhiyun 		.htotal = 720 + 16 + 2 + 120,
104*4882a593Smuzhiyun 		.vdisplay = 480,
105*4882a593Smuzhiyun 		.vsync_start = 480 + 3,
106*4882a593Smuzhiyun 		.vsync_end = 480 + 3 + 2,
107*4882a593Smuzhiyun 		.vtotal = 480 + 3 + 2 + 17,
108*4882a593Smuzhiyun 		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
109*4882a593Smuzhiyun 			 DRM_MODE_FLAG_INTERLACE,
110*4882a593Smuzhiyun 	},
111*4882a593Smuzhiyun 	.video_info = 0x00040080,
112*4882a593Smuzhiyun 	.video_res = 0x05a8375a,
113*4882a593Smuzhiyun 	.field1_param = 0x00041817,
114*4882a593Smuzhiyun 	.field2_param = 0x0008351e,
115*4882a593Smuzhiyun 	.burst_line_odd1 = 0x00041006,
116*4882a593Smuzhiyun 	.burst_line_even1 = 0x0008290d,
117*4882a593Smuzhiyun 	.burst_line_odd2 = 0x00000000,
118*4882a593Smuzhiyun 	.burst_line_even2 = 0x00000000,
119*4882a593Smuzhiyun 	.line_timing_param = 0x06a8ef9e,
120*4882a593Smuzhiyun 	.weight_value = 0x00b68197,
121*4882a593Smuzhiyun 	.blank_black_level = 0x0000f0f0,
122*4882a593Smuzhiyun 	.burst_level = 0x0000009c,
123*4882a593Smuzhiyun 	.control_param = 0x00000001,
124*4882a593Smuzhiyun 	.sub_carrier_phase1 = 0x10f83e10,
125*4882a593Smuzhiyun 	.phase_line_incr_cvbs = 0x80000000,
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun static const struct zx_tvenc_mode *tvenc_modes[] = {
129*4882a593Smuzhiyun 	&tvenc_mode_pal,
130*4882a593Smuzhiyun 	&tvenc_mode_ntsc,
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun static const struct zx_tvenc_mode *
zx_tvenc_find_zmode(struct drm_display_mode * mode)134*4882a593Smuzhiyun zx_tvenc_find_zmode(struct drm_display_mode *mode)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun 	int i;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(tvenc_modes); i++) {
139*4882a593Smuzhiyun 		const struct zx_tvenc_mode *zmode = tvenc_modes[i];
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 		if (drm_mode_equal(mode, &zmode->mode))
142*4882a593Smuzhiyun 			return zmode;
143*4882a593Smuzhiyun 	}
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	return NULL;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
zx_tvenc_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adj_mode)148*4882a593Smuzhiyun static void zx_tvenc_encoder_mode_set(struct drm_encoder *encoder,
149*4882a593Smuzhiyun 				      struct drm_display_mode *mode,
150*4882a593Smuzhiyun 				      struct drm_display_mode *adj_mode)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun 	struct zx_tvenc *tvenc = to_zx_tvenc(encoder);
153*4882a593Smuzhiyun 	const struct zx_tvenc_mode *zmode;
154*4882a593Smuzhiyun 	struct vou_div_config configs[] = {
155*4882a593Smuzhiyun 		{ VOU_DIV_INF,   VOU_DIV_4 },
156*4882a593Smuzhiyun 		{ VOU_DIV_TVENC, VOU_DIV_1 },
157*4882a593Smuzhiyun 		{ VOU_DIV_LAYER, VOU_DIV_2 },
158*4882a593Smuzhiyun 	};
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	zx_vou_config_dividers(encoder->crtc, configs, ARRAY_SIZE(configs));
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	zmode = zx_tvenc_find_zmode(mode);
163*4882a593Smuzhiyun 	if (!zmode) {
164*4882a593Smuzhiyun 		DRM_DEV_ERROR(tvenc->dev, "failed to find zmode\n");
165*4882a593Smuzhiyun 		return;
166*4882a593Smuzhiyun 	}
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_VIDEO_INFO, zmode->video_info);
169*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_VIDEO_RES, zmode->video_res);
170*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_FIELD1_PARAM, zmode->field1_param);
171*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_FIELD2_PARAM, zmode->field2_param);
172*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_LINE_O_1, zmode->burst_line_odd1);
173*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_LINE_E_1, zmode->burst_line_even1);
174*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_LINE_O_2, zmode->burst_line_odd2);
175*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_LINE_E_2, zmode->burst_line_even2);
176*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_LINE_TIMING_PARAM,
177*4882a593Smuzhiyun 		  zmode->line_timing_param);
178*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_WEIGHT_VALUE, zmode->weight_value);
179*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_BLANK_BLACK_LEVEL,
180*4882a593Smuzhiyun 		  zmode->blank_black_level);
181*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_BURST_LEVEL, zmode->burst_level);
182*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_CONTROL_PARAM, zmode->control_param);
183*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_SUB_CARRIER_PHASE1,
184*4882a593Smuzhiyun 		  zmode->sub_carrier_phase1);
185*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_PHASE_LINE_INCR_CVBS,
186*4882a593Smuzhiyun 		  zmode->phase_line_incr_cvbs);
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun 
zx_tvenc_encoder_enable(struct drm_encoder * encoder)189*4882a593Smuzhiyun static void zx_tvenc_encoder_enable(struct drm_encoder *encoder)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun 	struct zx_tvenc *tvenc = to_zx_tvenc(encoder);
192*4882a593Smuzhiyun 	struct zx_tvenc_pwrctrl *pwrctrl = &tvenc->pwrctrl;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	/* Set bit to power up TVENC DAC */
195*4882a593Smuzhiyun 	regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask,
196*4882a593Smuzhiyun 			   pwrctrl->mask);
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	vou_inf_enable(VOU_TV_ENC, encoder->crtc);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_ENABLE, 1);
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun 
zx_tvenc_encoder_disable(struct drm_encoder * encoder)203*4882a593Smuzhiyun static void zx_tvenc_encoder_disable(struct drm_encoder *encoder)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun 	struct zx_tvenc *tvenc = to_zx_tvenc(encoder);
206*4882a593Smuzhiyun 	struct zx_tvenc_pwrctrl *pwrctrl = &tvenc->pwrctrl;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	zx_writel(tvenc->mmio + VENC_ENABLE, 0);
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	vou_inf_disable(VOU_TV_ENC, encoder->crtc);
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	/* Clear bit to power down TVENC DAC */
213*4882a593Smuzhiyun 	regmap_update_bits(pwrctrl->regmap, pwrctrl->reg, pwrctrl->mask, 0);
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs zx_tvenc_encoder_helper_funcs = {
217*4882a593Smuzhiyun 	.enable	= zx_tvenc_encoder_enable,
218*4882a593Smuzhiyun 	.disable = zx_tvenc_encoder_disable,
219*4882a593Smuzhiyun 	.mode_set = zx_tvenc_encoder_mode_set,
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun 
zx_tvenc_connector_get_modes(struct drm_connector * connector)222*4882a593Smuzhiyun static int zx_tvenc_connector_get_modes(struct drm_connector *connector)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun 	struct zx_tvenc *tvenc = to_zx_tvenc(connector);
225*4882a593Smuzhiyun 	struct device *dev = tvenc->dev;
226*4882a593Smuzhiyun 	int i;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(tvenc_modes); i++) {
229*4882a593Smuzhiyun 		const struct zx_tvenc_mode *zmode = tvenc_modes[i];
230*4882a593Smuzhiyun 		struct drm_display_mode *mode;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 		mode = drm_mode_duplicate(connector->dev, &zmode->mode);
233*4882a593Smuzhiyun 		if (!mode) {
234*4882a593Smuzhiyun 			DRM_DEV_ERROR(dev, "failed to duplicate drm mode\n");
235*4882a593Smuzhiyun 			continue;
236*4882a593Smuzhiyun 		}
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 		drm_mode_set_name(mode);
239*4882a593Smuzhiyun 		drm_mode_probed_add(connector, mode);
240*4882a593Smuzhiyun 	}
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	return i;
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun static enum drm_mode_status
zx_tvenc_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)246*4882a593Smuzhiyun zx_tvenc_connector_mode_valid(struct drm_connector *connector,
247*4882a593Smuzhiyun 			      struct drm_display_mode *mode)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun 	struct zx_tvenc *tvenc = to_zx_tvenc(connector);
250*4882a593Smuzhiyun 	const struct zx_tvenc_mode *zmode;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	zmode = zx_tvenc_find_zmode(mode);
253*4882a593Smuzhiyun 	if (!zmode) {
254*4882a593Smuzhiyun 		DRM_DEV_ERROR(tvenc->dev, "unsupported mode: %s\n", mode->name);
255*4882a593Smuzhiyun 		return MODE_NOMODE;
256*4882a593Smuzhiyun 	}
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	return MODE_OK;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun static struct drm_connector_helper_funcs zx_tvenc_connector_helper_funcs = {
262*4882a593Smuzhiyun 	.get_modes = zx_tvenc_connector_get_modes,
263*4882a593Smuzhiyun 	.mode_valid = zx_tvenc_connector_mode_valid,
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun static const struct drm_connector_funcs zx_tvenc_connector_funcs = {
267*4882a593Smuzhiyun 	.fill_modes = drm_helper_probe_single_connector_modes,
268*4882a593Smuzhiyun 	.destroy = drm_connector_cleanup,
269*4882a593Smuzhiyun 	.reset = drm_atomic_helper_connector_reset,
270*4882a593Smuzhiyun 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
271*4882a593Smuzhiyun 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
272*4882a593Smuzhiyun };
273*4882a593Smuzhiyun 
zx_tvenc_register(struct drm_device * drm,struct zx_tvenc * tvenc)274*4882a593Smuzhiyun static int zx_tvenc_register(struct drm_device *drm, struct zx_tvenc *tvenc)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun 	struct drm_encoder *encoder = &tvenc->encoder;
277*4882a593Smuzhiyun 	struct drm_connector *connector = &tvenc->connector;
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	/*
280*4882a593Smuzhiyun 	 * The tvenc is designed to use aux channel, as there is a deflicker
281*4882a593Smuzhiyun 	 * block for the channel.
282*4882a593Smuzhiyun 	 */
283*4882a593Smuzhiyun 	encoder->possible_crtcs = BIT(1);
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TVDAC);
286*4882a593Smuzhiyun 	drm_encoder_helper_add(encoder, &zx_tvenc_encoder_helper_funcs);
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	connector->interlace_allowed = true;
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	drm_connector_init(drm, connector, &zx_tvenc_connector_funcs,
291*4882a593Smuzhiyun 			   DRM_MODE_CONNECTOR_Composite);
292*4882a593Smuzhiyun 	drm_connector_helper_add(connector, &zx_tvenc_connector_helper_funcs);
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	drm_connector_attach_encoder(connector, encoder);
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	return 0;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun 
zx_tvenc_pwrctrl_init(struct zx_tvenc * tvenc)299*4882a593Smuzhiyun static int zx_tvenc_pwrctrl_init(struct zx_tvenc *tvenc)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun 	struct zx_tvenc_pwrctrl *pwrctrl = &tvenc->pwrctrl;
302*4882a593Smuzhiyun 	struct device *dev = tvenc->dev;
303*4882a593Smuzhiyun 	struct of_phandle_args out_args;
304*4882a593Smuzhiyun 	struct regmap *regmap;
305*4882a593Smuzhiyun 	int ret;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	ret = of_parse_phandle_with_fixed_args(dev->of_node,
308*4882a593Smuzhiyun 				"zte,tvenc-power-control", 2, 0, &out_args);
309*4882a593Smuzhiyun 	if (ret)
310*4882a593Smuzhiyun 		return ret;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	regmap = syscon_node_to_regmap(out_args.np);
313*4882a593Smuzhiyun 	if (IS_ERR(regmap)) {
314*4882a593Smuzhiyun 		ret = PTR_ERR(regmap);
315*4882a593Smuzhiyun 		goto out;
316*4882a593Smuzhiyun 	}
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	pwrctrl->regmap = regmap;
319*4882a593Smuzhiyun 	pwrctrl->reg = out_args.args[0];
320*4882a593Smuzhiyun 	pwrctrl->mask = out_args.args[1];
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun out:
323*4882a593Smuzhiyun 	of_node_put(out_args.np);
324*4882a593Smuzhiyun 	return ret;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun 
zx_tvenc_bind(struct device * dev,struct device * master,void * data)327*4882a593Smuzhiyun static int zx_tvenc_bind(struct device *dev, struct device *master, void *data)
328*4882a593Smuzhiyun {
329*4882a593Smuzhiyun 	struct platform_device *pdev = to_platform_device(dev);
330*4882a593Smuzhiyun 	struct drm_device *drm = data;
331*4882a593Smuzhiyun 	struct resource *res;
332*4882a593Smuzhiyun 	struct zx_tvenc *tvenc;
333*4882a593Smuzhiyun 	int ret;
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	tvenc = devm_kzalloc(dev, sizeof(*tvenc), GFP_KERNEL);
336*4882a593Smuzhiyun 	if (!tvenc)
337*4882a593Smuzhiyun 		return -ENOMEM;
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	tvenc->dev = dev;
340*4882a593Smuzhiyun 	dev_set_drvdata(dev, tvenc);
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343*4882a593Smuzhiyun 	tvenc->mmio = devm_ioremap_resource(dev, res);
344*4882a593Smuzhiyun 	if (IS_ERR(tvenc->mmio)) {
345*4882a593Smuzhiyun 		ret = PTR_ERR(tvenc->mmio);
346*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to remap tvenc region: %d\n", ret);
347*4882a593Smuzhiyun 		return ret;
348*4882a593Smuzhiyun 	}
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	ret = zx_tvenc_pwrctrl_init(tvenc);
351*4882a593Smuzhiyun 	if (ret) {
352*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to init power control: %d\n", ret);
353*4882a593Smuzhiyun 		return ret;
354*4882a593Smuzhiyun 	}
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	ret = zx_tvenc_register(drm, tvenc);
357*4882a593Smuzhiyun 	if (ret) {
358*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to register tvenc: %d\n", ret);
359*4882a593Smuzhiyun 		return ret;
360*4882a593Smuzhiyun 	}
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	return 0;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun 
zx_tvenc_unbind(struct device * dev,struct device * master,void * data)365*4882a593Smuzhiyun static void zx_tvenc_unbind(struct device *dev, struct device *master,
366*4882a593Smuzhiyun 			    void *data)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun 	/* Nothing to do */
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun static const struct component_ops zx_tvenc_component_ops = {
372*4882a593Smuzhiyun 	.bind = zx_tvenc_bind,
373*4882a593Smuzhiyun 	.unbind = zx_tvenc_unbind,
374*4882a593Smuzhiyun };
375*4882a593Smuzhiyun 
zx_tvenc_probe(struct platform_device * pdev)376*4882a593Smuzhiyun static int zx_tvenc_probe(struct platform_device *pdev)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun 	return component_add(&pdev->dev, &zx_tvenc_component_ops);
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun 
zx_tvenc_remove(struct platform_device * pdev)381*4882a593Smuzhiyun static int zx_tvenc_remove(struct platform_device *pdev)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun 	component_del(&pdev->dev, &zx_tvenc_component_ops);
384*4882a593Smuzhiyun 	return 0;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun static const struct of_device_id zx_tvenc_of_match[] = {
388*4882a593Smuzhiyun 	{ .compatible = "zte,zx296718-tvenc", },
389*4882a593Smuzhiyun 	{ /* end */ },
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, zx_tvenc_of_match);
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun struct platform_driver zx_tvenc_driver = {
394*4882a593Smuzhiyun 	.probe = zx_tvenc_probe,
395*4882a593Smuzhiyun 	.remove = zx_tvenc_remove,
396*4882a593Smuzhiyun 	.driver	= {
397*4882a593Smuzhiyun 		.name = "zx-tvenc",
398*4882a593Smuzhiyun 		.of_match_table	= zx_tvenc_of_match,
399*4882a593Smuzhiyun 	},
400*4882a593Smuzhiyun };
401