1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Linaro Ltd. 4*4882a593Smuzhiyun * Copyright 2016 ZTE Corporation. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ZX_PLANE_REGS_H__ 8*4882a593Smuzhiyun #define __ZX_PLANE_REGS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* GL registers */ 11*4882a593Smuzhiyun #define GL_CTRL0 0x00 12*4882a593Smuzhiyun #define GL_UPDATE BIT(5) 13*4882a593Smuzhiyun #define GL_CTRL1 0x04 14*4882a593Smuzhiyun #define GL_DATA_FMT_SHIFT 0 15*4882a593Smuzhiyun #define GL_DATA_FMT_MASK (0xf << GL_DATA_FMT_SHIFT) 16*4882a593Smuzhiyun #define GL_FMT_ARGB8888 0 17*4882a593Smuzhiyun #define GL_FMT_RGB888 1 18*4882a593Smuzhiyun #define GL_FMT_RGB565 2 19*4882a593Smuzhiyun #define GL_FMT_ARGB1555 3 20*4882a593Smuzhiyun #define GL_FMT_ARGB4444 4 21*4882a593Smuzhiyun #define GL_CTRL2 0x08 22*4882a593Smuzhiyun #define GL_GLOBAL_ALPHA_SHIFT 8 23*4882a593Smuzhiyun #define GL_GLOBAL_ALPHA_MASK (0xff << GL_GLOBAL_ALPHA_SHIFT) 24*4882a593Smuzhiyun #define GL_CTRL3 0x0c 25*4882a593Smuzhiyun #define GL_SCALER_BYPASS_MODE BIT(0) 26*4882a593Smuzhiyun #define GL_STRIDE 0x18 27*4882a593Smuzhiyun #define GL_ADDR 0x1c 28*4882a593Smuzhiyun #define GL_SRC_SIZE 0x38 29*4882a593Smuzhiyun #define GL_SRC_W_SHIFT 16 30*4882a593Smuzhiyun #define GL_SRC_W_MASK (0x3fff << GL_SRC_W_SHIFT) 31*4882a593Smuzhiyun #define GL_SRC_H_SHIFT 0 32*4882a593Smuzhiyun #define GL_SRC_H_MASK (0x3fff << GL_SRC_H_SHIFT) 33*4882a593Smuzhiyun #define GL_POS_START 0x9c 34*4882a593Smuzhiyun #define GL_POS_END 0xa0 35*4882a593Smuzhiyun #define GL_POS_X_SHIFT 16 36*4882a593Smuzhiyun #define GL_POS_X_MASK (0x1fff << GL_POS_X_SHIFT) 37*4882a593Smuzhiyun #define GL_POS_Y_SHIFT 0 38*4882a593Smuzhiyun #define GL_POS_Y_MASK (0x1fff << GL_POS_Y_SHIFT) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define GL_SRC_W(x) (((x) << GL_SRC_W_SHIFT) & GL_SRC_W_MASK) 41*4882a593Smuzhiyun #define GL_SRC_H(x) (((x) << GL_SRC_H_SHIFT) & GL_SRC_H_MASK) 42*4882a593Smuzhiyun #define GL_POS_X(x) (((x) << GL_POS_X_SHIFT) & GL_POS_X_MASK) 43*4882a593Smuzhiyun #define GL_POS_Y(x) (((x) << GL_POS_Y_SHIFT) & GL_POS_Y_MASK) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* VL registers */ 46*4882a593Smuzhiyun #define VL_CTRL0 0x00 47*4882a593Smuzhiyun #define VL_UPDATE BIT(3) 48*4882a593Smuzhiyun #define VL_CTRL1 0x04 49*4882a593Smuzhiyun #define VL_YUV420_PLANAR BIT(5) 50*4882a593Smuzhiyun #define VL_YUV422_SHIFT 3 51*4882a593Smuzhiyun #define VL_YUV422_YUYV (0 << VL_YUV422_SHIFT) 52*4882a593Smuzhiyun #define VL_YUV422_YVYU (1 << VL_YUV422_SHIFT) 53*4882a593Smuzhiyun #define VL_YUV422_UYVY (2 << VL_YUV422_SHIFT) 54*4882a593Smuzhiyun #define VL_YUV422_VYUY (3 << VL_YUV422_SHIFT) 55*4882a593Smuzhiyun #define VL_FMT_YUV420 0 56*4882a593Smuzhiyun #define VL_FMT_YUV422 1 57*4882a593Smuzhiyun #define VL_FMT_YUV420_P010 2 58*4882a593Smuzhiyun #define VL_FMT_YUV420_HANTRO 3 59*4882a593Smuzhiyun #define VL_FMT_YUV444_8BIT 4 60*4882a593Smuzhiyun #define VL_FMT_YUV444_10BIT 5 61*4882a593Smuzhiyun #define VL_CTRL2 0x08 62*4882a593Smuzhiyun #define VL_SCALER_BYPASS_MODE BIT(0) 63*4882a593Smuzhiyun #define VL_STRIDE 0x0c 64*4882a593Smuzhiyun #define LUMA_STRIDE_SHIFT 16 65*4882a593Smuzhiyun #define LUMA_STRIDE_MASK (0xffff << LUMA_STRIDE_SHIFT) 66*4882a593Smuzhiyun #define CHROMA_STRIDE_SHIFT 0 67*4882a593Smuzhiyun #define CHROMA_STRIDE_MASK (0xffff << CHROMA_STRIDE_SHIFT) 68*4882a593Smuzhiyun #define VL_SRC_SIZE 0x10 69*4882a593Smuzhiyun #define VL_Y 0x14 70*4882a593Smuzhiyun #define VL_POS_START 0x30 71*4882a593Smuzhiyun #define VL_POS_END 0x34 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define LUMA_STRIDE(x) (((x) << LUMA_STRIDE_SHIFT) & LUMA_STRIDE_MASK) 74*4882a593Smuzhiyun #define CHROMA_STRIDE(x) (((x) << CHROMA_STRIDE_SHIFT) & CHROMA_STRIDE_MASK) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* RSZ registers */ 77*4882a593Smuzhiyun #define RSZ_SRC_CFG 0x00 78*4882a593Smuzhiyun #define RSZ_DEST_CFG 0x04 79*4882a593Smuzhiyun #define RSZ_ENABLE_CFG 0x14 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define RSZ_VL_LUMA_HOR 0x08 82*4882a593Smuzhiyun #define RSZ_VL_LUMA_VER 0x0c 83*4882a593Smuzhiyun #define RSZ_VL_CHROMA_HOR 0x10 84*4882a593Smuzhiyun #define RSZ_VL_CHROMA_VER 0x14 85*4882a593Smuzhiyun #define RSZ_VL_CTRL_CFG 0x18 86*4882a593Smuzhiyun #define RSZ_VL_FMT_SHIFT 3 87*4882a593Smuzhiyun #define RSZ_VL_FMT_MASK (0x3 << RSZ_VL_FMT_SHIFT) 88*4882a593Smuzhiyun #define RSZ_VL_FMT_YCBCR420 (0x0 << RSZ_VL_FMT_SHIFT) 89*4882a593Smuzhiyun #define RSZ_VL_FMT_YCBCR422 (0x1 << RSZ_VL_FMT_SHIFT) 90*4882a593Smuzhiyun #define RSZ_VL_FMT_YCBCR444 (0x2 << RSZ_VL_FMT_SHIFT) 91*4882a593Smuzhiyun #define RSZ_VL_ENABLE_CFG 0x1c 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define RSZ_VER_SHIFT 16 94*4882a593Smuzhiyun #define RSZ_VER_MASK (0xffff << RSZ_VER_SHIFT) 95*4882a593Smuzhiyun #define RSZ_HOR_SHIFT 0 96*4882a593Smuzhiyun #define RSZ_HOR_MASK (0xffff << RSZ_HOR_SHIFT) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define RSZ_VER(x) (((x) << RSZ_VER_SHIFT) & RSZ_VER_MASK) 99*4882a593Smuzhiyun #define RSZ_HOR(x) (((x) << RSZ_HOR_SHIFT) & RSZ_HOR_MASK) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define RSZ_DATA_STEP_SHIFT 16 102*4882a593Smuzhiyun #define RSZ_DATA_STEP_MASK (0xffff << RSZ_DATA_STEP_SHIFT) 103*4882a593Smuzhiyun #define RSZ_PARA_STEP_SHIFT 0 104*4882a593Smuzhiyun #define RSZ_PARA_STEP_MASK (0xffff << RSZ_PARA_STEP_SHIFT) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define RSZ_DATA_STEP(x) (((x) << RSZ_DATA_STEP_SHIFT) & RSZ_DATA_STEP_MASK) 107*4882a593Smuzhiyun #define RSZ_PARA_STEP(x) (((x) << RSZ_PARA_STEP_SHIFT) & RSZ_PARA_STEP_MASK) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* HBSC registers */ 110*4882a593Smuzhiyun #define HBSC_SATURATION 0x00 111*4882a593Smuzhiyun #define HBSC_HUE 0x04 112*4882a593Smuzhiyun #define HBSC_BRIGHT 0x08 113*4882a593Smuzhiyun #define HBSC_CONTRAST 0x0c 114*4882a593Smuzhiyun #define HBSC_THRESHOLD_COL1 0x10 115*4882a593Smuzhiyun #define HBSC_THRESHOLD_COL2 0x14 116*4882a593Smuzhiyun #define HBSC_THRESHOLD_COL3 0x18 117*4882a593Smuzhiyun #define HBSC_CTRL0 0x28 118*4882a593Smuzhiyun #define HBSC_CTRL_EN BIT(2) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif /* __ZX_PLANE_REGS_H__ */ 121