1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016 Linaro Ltd. 4*4882a593Smuzhiyun * Copyright 2016 ZTE Corporation. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ZX_HDMI_REGS_H__ 8*4882a593Smuzhiyun #define __ZX_HDMI_REGS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define FUNC_SEL 0x000b 11*4882a593Smuzhiyun #define FUNC_HDMI_EN BIT(0) 12*4882a593Smuzhiyun #define CLKPWD 0x000d 13*4882a593Smuzhiyun #define CLKPWD_PDIDCK BIT(2) 14*4882a593Smuzhiyun #define P2T_CTRL 0x0066 15*4882a593Smuzhiyun #define P2T_DC_PKT_EN BIT(7) 16*4882a593Smuzhiyun #define L1_INTR_STAT 0x007e 17*4882a593Smuzhiyun #define L1_INTR_STAT_INTR1 BIT(0) 18*4882a593Smuzhiyun #define INTR1_STAT 0x008f 19*4882a593Smuzhiyun #define INTR1_MASK 0x0095 20*4882a593Smuzhiyun #define INTR1_MONITOR_DETECT (BIT(5) | BIT(6)) 21*4882a593Smuzhiyun #define ZX_DDC_ADDR 0x00ed 22*4882a593Smuzhiyun #define ZX_DDC_SEGM 0x00ee 23*4882a593Smuzhiyun #define ZX_DDC_OFFSET 0x00ef 24*4882a593Smuzhiyun #define ZX_DDC_DIN_CNT1 0x00f0 25*4882a593Smuzhiyun #define ZX_DDC_DIN_CNT2 0x00f1 26*4882a593Smuzhiyun #define ZX_DDC_CMD 0x00f3 27*4882a593Smuzhiyun #define DDC_CMD_MASK 0xf 28*4882a593Smuzhiyun #define DDC_CMD_CLEAR_FIFO 0x9 29*4882a593Smuzhiyun #define DDC_CMD_SEQUENTIAL_READ 0x2 30*4882a593Smuzhiyun #define ZX_DDC_DATA 0x00f4 31*4882a593Smuzhiyun #define ZX_DDC_DOUT_CNT 0x00f5 32*4882a593Smuzhiyun #define DDC_DOUT_CNT_MASK 0x1f 33*4882a593Smuzhiyun #define TEST_TXCTRL 0x00f7 34*4882a593Smuzhiyun #define TEST_TXCTRL_HDMI_MODE BIT(1) 35*4882a593Smuzhiyun #define HDMICTL4 0x0235 36*4882a593Smuzhiyun #define TPI_HPD_RSEN 0x063b 37*4882a593Smuzhiyun #define TPI_HPD_CONNECTION (BIT(1) | BIT(2)) 38*4882a593Smuzhiyun #define TPI_INFO_FSEL 0x06bf 39*4882a593Smuzhiyun #define FSEL_AVI 0 40*4882a593Smuzhiyun #define FSEL_GBD 1 41*4882a593Smuzhiyun #define FSEL_AUDIO 2 42*4882a593Smuzhiyun #define FSEL_SPD 3 43*4882a593Smuzhiyun #define FSEL_MPEG 4 44*4882a593Smuzhiyun #define FSEL_VSIF 5 45*4882a593Smuzhiyun #define TPI_INFO_B0 0x06c0 46*4882a593Smuzhiyun #define TPI_INFO_EN 0x06df 47*4882a593Smuzhiyun #define TPI_INFO_TRANS_EN BIT(7) 48*4882a593Smuzhiyun #define TPI_INFO_TRANS_RPT BIT(6) 49*4882a593Smuzhiyun #define TPI_DDC_MASTER_EN 0x06f8 50*4882a593Smuzhiyun #define HW_DDC_MASTER BIT(7) 51*4882a593Smuzhiyun #define N_SVAL1 0xa03 52*4882a593Smuzhiyun #define N_SVAL2 0xa04 53*4882a593Smuzhiyun #define N_SVAL3 0xa05 54*4882a593Smuzhiyun #define AUD_EN 0xa13 55*4882a593Smuzhiyun #define AUD_IN_EN BIT(0) 56*4882a593Smuzhiyun #define AUD_MODE 0xa14 57*4882a593Smuzhiyun #define SPDIF_EN BIT(1) 58*4882a593Smuzhiyun #define TPI_AUD_CONFIG 0xa62 59*4882a593Smuzhiyun #define SPDIF_SAMPLE_SIZE_SHIFT 6 60*4882a593Smuzhiyun #define SPDIF_SAMPLE_SIZE_MASK (0x3 << SPDIF_SAMPLE_SIZE_SHIFT) 61*4882a593Smuzhiyun #define SPDIF_SAMPLE_SIZE_16BIT (0x1 << SPDIF_SAMPLE_SIZE_SHIFT) 62*4882a593Smuzhiyun #define SPDIF_SAMPLE_SIZE_20BIT (0x2 << SPDIF_SAMPLE_SIZE_SHIFT) 63*4882a593Smuzhiyun #define SPDIF_SAMPLE_SIZE_24BIT (0x3 << SPDIF_SAMPLE_SIZE_SHIFT) 64*4882a593Smuzhiyun #define TPI_AUD_MUTE BIT(4) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif /* __ZX_HDMI_REGS_H__ */ 67