1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ZynqMP DPSUB Subsystem Driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017 - 2020 Xilinx, Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Authors: 8*4882a593Smuzhiyun * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9*4882a593Smuzhiyun * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _ZYNQMP_DPSUB_H_ 13*4882a593Smuzhiyun #define _ZYNQMP_DPSUB_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct clk; 16*4882a593Smuzhiyun struct device; 17*4882a593Smuzhiyun struct drm_device; 18*4882a593Smuzhiyun struct zynqmp_disp; 19*4882a593Smuzhiyun struct zynqmp_dp; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun enum zynqmp_dpsub_format { 22*4882a593Smuzhiyun ZYNQMP_DPSUB_FORMAT_RGB, 23*4882a593Smuzhiyun ZYNQMP_DPSUB_FORMAT_YCRCB444, 24*4882a593Smuzhiyun ZYNQMP_DPSUB_FORMAT_YCRCB422, 25*4882a593Smuzhiyun ZYNQMP_DPSUB_FORMAT_YONLY, 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /** 29*4882a593Smuzhiyun * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem 30*4882a593Smuzhiyun * @drm: The DRM/KMS device 31*4882a593Smuzhiyun * @dev: The physical device 32*4882a593Smuzhiyun * @apb_clk: The APB clock 33*4882a593Smuzhiyun * @disp: The display controller 34*4882a593Smuzhiyun * @dp: The DisplayPort controller 35*4882a593Smuzhiyun * @dma_align: DMA alignment constraint (must be a power of 2) 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun struct zynqmp_dpsub { 38*4882a593Smuzhiyun struct drm_device drm; 39*4882a593Smuzhiyun struct device *dev; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct clk *apb_clk; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct zynqmp_disp *disp; 44*4882a593Smuzhiyun struct zynqmp_dp *dp; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun unsigned int dma_align; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun to_zynqmp_dpsub(struct drm_device * drm)49*4882a593Smuzhiyunstatic inline struct zynqmp_dpsub *to_zynqmp_dpsub(struct drm_device *drm) 50*4882a593Smuzhiyun { 51*4882a593Smuzhiyun return container_of(drm, struct zynqmp_dpsub, drm); 52*4882a593Smuzhiyun } 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #endif /* _ZYNQMP_DPSUB_H_ */ 55