xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 OR MIT
2*4882a593Smuzhiyun /******************************************************************************
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * COPYRIGHT (C) 2014-2015 VMware, Inc., Palo Alto, CA., USA
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
7*4882a593Smuzhiyun  * copy of this software and associated documentation files (the
8*4882a593Smuzhiyun  * "Software"), to deal in the Software without restriction, including
9*4882a593Smuzhiyun  * without limitation the rights to use, copy, modify, merge, publish,
10*4882a593Smuzhiyun  * distribute, sub license, and/or sell copies of the Software, and to
11*4882a593Smuzhiyun  * permit persons to whom the Software is furnished to do so, subject to
12*4882a593Smuzhiyun  * the following conditions:
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * The above copyright notice and this permission notice (including the
15*4882a593Smuzhiyun  * next paragraph) shall be included in all copies or substantial portions
16*4882a593Smuzhiyun  * of the Software.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21*4882a593Smuzhiyun  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22*4882a593Smuzhiyun  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23*4882a593Smuzhiyun  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24*4882a593Smuzhiyun  * USE OR OTHER DEALINGS IN THE SOFTWARE.
25*4882a593Smuzhiyun  *
26*4882a593Smuzhiyun  ******************************************************************************/
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #include <drm/drm_atomic.h>
29*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
30*4882a593Smuzhiyun #include <drm/drm_damage_helper.h>
31*4882a593Smuzhiyun #include <drm/drm_fourcc.h>
32*4882a593Smuzhiyun #include <drm/drm_plane_helper.h>
33*4882a593Smuzhiyun #include <drm/drm_vblank.h>
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #include "vmwgfx_kms.h"
36*4882a593Smuzhiyun #include "device_include/svga3d_surfacedefs.h"
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define vmw_crtc_to_stdu(x) \
39*4882a593Smuzhiyun 	container_of(x, struct vmw_screen_target_display_unit, base.crtc)
40*4882a593Smuzhiyun #define vmw_encoder_to_stdu(x) \
41*4882a593Smuzhiyun 	container_of(x, struct vmw_screen_target_display_unit, base.encoder)
42*4882a593Smuzhiyun #define vmw_connector_to_stdu(x) \
43*4882a593Smuzhiyun 	container_of(x, struct vmw_screen_target_display_unit, base.connector)
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun enum stdu_content_type {
48*4882a593Smuzhiyun 	SAME_AS_DISPLAY = 0,
49*4882a593Smuzhiyun 	SEPARATE_SURFACE,
50*4882a593Smuzhiyun 	SEPARATE_BO
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun /**
54*4882a593Smuzhiyun  * struct vmw_stdu_dirty - closure structure for the update functions
55*4882a593Smuzhiyun  *
56*4882a593Smuzhiyun  * @base: The base type we derive from. Used by vmw_kms_helper_dirty().
57*4882a593Smuzhiyun  * @transfer: Transfer direction for DMA command.
58*4882a593Smuzhiyun  * @left: Left side of bounding box.
59*4882a593Smuzhiyun  * @right: Right side of bounding box.
60*4882a593Smuzhiyun  * @top: Top side of bounding box.
61*4882a593Smuzhiyun  * @bottom: Bottom side of bounding box.
62*4882a593Smuzhiyun  * @fb_left: Left side of the framebuffer/content bounding box
63*4882a593Smuzhiyun  * @fb_top: Top of the framebuffer/content bounding box
64*4882a593Smuzhiyun  * @buf: buffer object when DMA-ing between buffer and screen targets.
65*4882a593Smuzhiyun  * @sid: Surface ID when copying between surface and screen targets.
66*4882a593Smuzhiyun  */
67*4882a593Smuzhiyun struct vmw_stdu_dirty {
68*4882a593Smuzhiyun 	struct vmw_kms_dirty base;
69*4882a593Smuzhiyun 	SVGA3dTransferType  transfer;
70*4882a593Smuzhiyun 	s32 left, right, top, bottom;
71*4882a593Smuzhiyun 	s32 fb_left, fb_top;
72*4882a593Smuzhiyun 	u32 pitch;
73*4882a593Smuzhiyun 	union {
74*4882a593Smuzhiyun 		struct vmw_buffer_object *buf;
75*4882a593Smuzhiyun 		u32 sid;
76*4882a593Smuzhiyun 	};
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun  * SVGA commands that are used by this code. Please see the device headers
81*4882a593Smuzhiyun  * for explanation.
82*4882a593Smuzhiyun  */
83*4882a593Smuzhiyun struct vmw_stdu_update {
84*4882a593Smuzhiyun 	SVGA3dCmdHeader header;
85*4882a593Smuzhiyun 	SVGA3dCmdUpdateGBScreenTarget body;
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun struct vmw_stdu_dma {
89*4882a593Smuzhiyun 	SVGA3dCmdHeader     header;
90*4882a593Smuzhiyun 	SVGA3dCmdSurfaceDMA body;
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun struct vmw_stdu_surface_copy {
94*4882a593Smuzhiyun 	SVGA3dCmdHeader      header;
95*4882a593Smuzhiyun 	SVGA3dCmdSurfaceCopy body;
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun struct vmw_stdu_update_gb_image {
99*4882a593Smuzhiyun 	SVGA3dCmdHeader header;
100*4882a593Smuzhiyun 	SVGA3dCmdUpdateGBImage body;
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /**
104*4882a593Smuzhiyun  * struct vmw_screen_target_display_unit
105*4882a593Smuzhiyun  *
106*4882a593Smuzhiyun  * @base: VMW specific DU structure
107*4882a593Smuzhiyun  * @display_srf: surface to be displayed.  The dimension of this will always
108*4882a593Smuzhiyun  *               match the display mode.  If the display mode matches
109*4882a593Smuzhiyun  *               content_vfbs dimensions, then this is a pointer into the
110*4882a593Smuzhiyun  *               corresponding field in content_vfbs.  If not, then this
111*4882a593Smuzhiyun  *               is a separate buffer to which content_vfbs will blit to.
112*4882a593Smuzhiyun  * @content_type:  content_fb type
113*4882a593Smuzhiyun  * @defined:  true if the current display unit has been initialized
114*4882a593Smuzhiyun  */
115*4882a593Smuzhiyun struct vmw_screen_target_display_unit {
116*4882a593Smuzhiyun 	struct vmw_display_unit base;
117*4882a593Smuzhiyun 	struct vmw_surface *display_srf;
118*4882a593Smuzhiyun 	enum stdu_content_type content_fb_type;
119*4882a593Smuzhiyun 	s32 display_width, display_height;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	bool defined;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	/* For CPU Blit */
124*4882a593Smuzhiyun 	unsigned int cpp;
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu);
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun /******************************************************************************
134*4882a593Smuzhiyun  * Screen Target Display Unit CRTC Functions
135*4882a593Smuzhiyun  *****************************************************************************/
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun /**
139*4882a593Smuzhiyun  * vmw_stdu_crtc_destroy - cleans up the STDU
140*4882a593Smuzhiyun  *
141*4882a593Smuzhiyun  * @crtc: used to get a reference to the containing STDU
142*4882a593Smuzhiyun  */
vmw_stdu_crtc_destroy(struct drm_crtc * crtc)143*4882a593Smuzhiyun static void vmw_stdu_crtc_destroy(struct drm_crtc *crtc)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	vmw_stdu_destroy(vmw_crtc_to_stdu(crtc));
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun /**
149*4882a593Smuzhiyun  * vmw_stdu_define_st - Defines a Screen Target
150*4882a593Smuzhiyun  *
151*4882a593Smuzhiyun  * @dev_priv:  VMW DRM device
152*4882a593Smuzhiyun  * @stdu: display unit to create a Screen Target for
153*4882a593Smuzhiyun  * @mode: The mode to set.
154*4882a593Smuzhiyun  * @crtc_x: X coordinate of screen target relative to framebuffer origin.
155*4882a593Smuzhiyun  * @crtc_y: Y coordinate of screen target relative to framebuffer origin.
156*4882a593Smuzhiyun  *
157*4882a593Smuzhiyun  * Creates a STDU that we can used later.  This function is called whenever the
158*4882a593Smuzhiyun  * framebuffer size changes.
159*4882a593Smuzhiyun  *
160*4882a593Smuzhiyun  * RETURNs:
161*4882a593Smuzhiyun  * 0 on success, error code on failure
162*4882a593Smuzhiyun  */
vmw_stdu_define_st(struct vmw_private * dev_priv,struct vmw_screen_target_display_unit * stdu,struct drm_display_mode * mode,int crtc_x,int crtc_y)163*4882a593Smuzhiyun static int vmw_stdu_define_st(struct vmw_private *dev_priv,
164*4882a593Smuzhiyun 			      struct vmw_screen_target_display_unit *stdu,
165*4882a593Smuzhiyun 			      struct drm_display_mode *mode,
166*4882a593Smuzhiyun 			      int crtc_x, int crtc_y)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	struct {
169*4882a593Smuzhiyun 		SVGA3dCmdHeader header;
170*4882a593Smuzhiyun 		SVGA3dCmdDefineGBScreenTarget body;
171*4882a593Smuzhiyun 	} *cmd;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
174*4882a593Smuzhiyun 	if (unlikely(cmd == NULL))
175*4882a593Smuzhiyun 		return -ENOMEM;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	cmd->header.id   = SVGA_3D_CMD_DEFINE_GB_SCREENTARGET;
178*4882a593Smuzhiyun 	cmd->header.size = sizeof(cmd->body);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	cmd->body.stid   = stdu->base.unit;
181*4882a593Smuzhiyun 	cmd->body.width  = mode->hdisplay;
182*4882a593Smuzhiyun 	cmd->body.height = mode->vdisplay;
183*4882a593Smuzhiyun 	cmd->body.flags  = (0 == cmd->body.stid) ? SVGA_STFLAG_PRIMARY : 0;
184*4882a593Smuzhiyun 	cmd->body.dpi    = 0;
185*4882a593Smuzhiyun 	cmd->body.xRoot  = crtc_x;
186*4882a593Smuzhiyun 	cmd->body.yRoot  = crtc_y;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	stdu->base.set_gui_x = cmd->body.xRoot;
189*4882a593Smuzhiyun 	stdu->base.set_gui_y = cmd->body.yRoot;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	vmw_fifo_commit(dev_priv, sizeof(*cmd));
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	stdu->defined = true;
194*4882a593Smuzhiyun 	stdu->display_width  = mode->hdisplay;
195*4882a593Smuzhiyun 	stdu->display_height = mode->vdisplay;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	return 0;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun /**
203*4882a593Smuzhiyun  * vmw_stdu_bind_st - Binds a surface to a Screen Target
204*4882a593Smuzhiyun  *
205*4882a593Smuzhiyun  * @dev_priv: VMW DRM device
206*4882a593Smuzhiyun  * @stdu: display unit affected
207*4882a593Smuzhiyun  * @res: Buffer to bind to the screen target.  Set to NULL to blank screen.
208*4882a593Smuzhiyun  *
209*4882a593Smuzhiyun  * Binding a surface to a Screen Target the same as flipping
210*4882a593Smuzhiyun  */
vmw_stdu_bind_st(struct vmw_private * dev_priv,struct vmw_screen_target_display_unit * stdu,const struct vmw_resource * res)211*4882a593Smuzhiyun static int vmw_stdu_bind_st(struct vmw_private *dev_priv,
212*4882a593Smuzhiyun 			    struct vmw_screen_target_display_unit *stdu,
213*4882a593Smuzhiyun 			    const struct vmw_resource *res)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	SVGA3dSurfaceImageId image;
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	struct {
218*4882a593Smuzhiyun 		SVGA3dCmdHeader header;
219*4882a593Smuzhiyun 		SVGA3dCmdBindGBScreenTarget body;
220*4882a593Smuzhiyun 	} *cmd;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	if (!stdu->defined) {
224*4882a593Smuzhiyun 		DRM_ERROR("No screen target defined\n");
225*4882a593Smuzhiyun 		return -EINVAL;
226*4882a593Smuzhiyun 	}
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	/* Set up image using information in vfb */
229*4882a593Smuzhiyun 	memset(&image, 0, sizeof(image));
230*4882a593Smuzhiyun 	image.sid = res ? res->id : SVGA3D_INVALID_ID;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
233*4882a593Smuzhiyun 	if (unlikely(cmd == NULL))
234*4882a593Smuzhiyun 		return -ENOMEM;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	cmd->header.id   = SVGA_3D_CMD_BIND_GB_SCREENTARGET;
237*4882a593Smuzhiyun 	cmd->header.size = sizeof(cmd->body);
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	cmd->body.stid   = stdu->base.unit;
240*4882a593Smuzhiyun 	cmd->body.image  = image;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	vmw_fifo_commit(dev_priv, sizeof(*cmd));
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	return 0;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun /**
248*4882a593Smuzhiyun  * vmw_stdu_populate_update - populate an UPDATE_GB_SCREENTARGET command with a
249*4882a593Smuzhiyun  * bounding box.
250*4882a593Smuzhiyun  *
251*4882a593Smuzhiyun  * @cmd: Pointer to command stream.
252*4882a593Smuzhiyun  * @unit: Screen target unit.
253*4882a593Smuzhiyun  * @left: Left side of bounding box.
254*4882a593Smuzhiyun  * @right: Right side of bounding box.
255*4882a593Smuzhiyun  * @top: Top side of bounding box.
256*4882a593Smuzhiyun  * @bottom: Bottom side of bounding box.
257*4882a593Smuzhiyun  */
vmw_stdu_populate_update(void * cmd,int unit,s32 left,s32 right,s32 top,s32 bottom)258*4882a593Smuzhiyun static void vmw_stdu_populate_update(void *cmd, int unit,
259*4882a593Smuzhiyun 				     s32 left, s32 right, s32 top, s32 bottom)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	struct vmw_stdu_update *update = cmd;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	update->header.id   = SVGA_3D_CMD_UPDATE_GB_SCREENTARGET;
264*4882a593Smuzhiyun 	update->header.size = sizeof(update->body);
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	update->body.stid   = unit;
267*4882a593Smuzhiyun 	update->body.rect.x = left;
268*4882a593Smuzhiyun 	update->body.rect.y = top;
269*4882a593Smuzhiyun 	update->body.rect.w = right - left;
270*4882a593Smuzhiyun 	update->body.rect.h = bottom - top;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun /**
274*4882a593Smuzhiyun  * vmw_stdu_update_st - Full update of a Screen Target
275*4882a593Smuzhiyun  *
276*4882a593Smuzhiyun  * @dev_priv: VMW DRM device
277*4882a593Smuzhiyun  * @stdu: display unit affected
278*4882a593Smuzhiyun  *
279*4882a593Smuzhiyun  * This function needs to be called whenever the content of a screen
280*4882a593Smuzhiyun  * target has changed completely. Typically as a result of a backing
281*4882a593Smuzhiyun  * surface change.
282*4882a593Smuzhiyun  *
283*4882a593Smuzhiyun  * RETURNS:
284*4882a593Smuzhiyun  * 0 on success, error code on failure
285*4882a593Smuzhiyun  */
vmw_stdu_update_st(struct vmw_private * dev_priv,struct vmw_screen_target_display_unit * stdu)286*4882a593Smuzhiyun static int vmw_stdu_update_st(struct vmw_private *dev_priv,
287*4882a593Smuzhiyun 			      struct vmw_screen_target_display_unit *stdu)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun 	struct vmw_stdu_update *cmd;
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	if (!stdu->defined) {
292*4882a593Smuzhiyun 		DRM_ERROR("No screen target defined");
293*4882a593Smuzhiyun 		return -EINVAL;
294*4882a593Smuzhiyun 	}
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
297*4882a593Smuzhiyun 	if (unlikely(cmd == NULL))
298*4882a593Smuzhiyun 		return -ENOMEM;
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	vmw_stdu_populate_update(cmd, stdu->base.unit,
301*4882a593Smuzhiyun 				 0, stdu->display_width,
302*4882a593Smuzhiyun 				 0, stdu->display_height);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	vmw_fifo_commit(dev_priv, sizeof(*cmd));
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	return 0;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun /**
312*4882a593Smuzhiyun  * vmw_stdu_destroy_st - Destroy a Screen Target
313*4882a593Smuzhiyun  *
314*4882a593Smuzhiyun  * @dev_priv:  VMW DRM device
315*4882a593Smuzhiyun  * @stdu: display unit to destroy
316*4882a593Smuzhiyun  */
vmw_stdu_destroy_st(struct vmw_private * dev_priv,struct vmw_screen_target_display_unit * stdu)317*4882a593Smuzhiyun static int vmw_stdu_destroy_st(struct vmw_private *dev_priv,
318*4882a593Smuzhiyun 			       struct vmw_screen_target_display_unit *stdu)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun 	int    ret;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	struct {
323*4882a593Smuzhiyun 		SVGA3dCmdHeader header;
324*4882a593Smuzhiyun 		SVGA3dCmdDestroyGBScreenTarget body;
325*4882a593Smuzhiyun 	} *cmd;
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	/* Nothing to do if not successfully defined */
329*4882a593Smuzhiyun 	if (unlikely(!stdu->defined))
330*4882a593Smuzhiyun 		return 0;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
333*4882a593Smuzhiyun 	if (unlikely(cmd == NULL))
334*4882a593Smuzhiyun 		return -ENOMEM;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	cmd->header.id   = SVGA_3D_CMD_DESTROY_GB_SCREENTARGET;
337*4882a593Smuzhiyun 	cmd->header.size = sizeof(cmd->body);
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	cmd->body.stid   = stdu->base.unit;
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	vmw_fifo_commit(dev_priv, sizeof(*cmd));
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	/* Force sync */
344*4882a593Smuzhiyun 	ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
345*4882a593Smuzhiyun 	if (unlikely(ret != 0))
346*4882a593Smuzhiyun 		DRM_ERROR("Failed to sync with HW");
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	stdu->defined = false;
349*4882a593Smuzhiyun 	stdu->display_width  = 0;
350*4882a593Smuzhiyun 	stdu->display_height = 0;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	return ret;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun /**
357*4882a593Smuzhiyun  * vmw_stdu_crtc_mode_set_nofb - Updates screen target size
358*4882a593Smuzhiyun  *
359*4882a593Smuzhiyun  * @crtc: CRTC associated with the screen target
360*4882a593Smuzhiyun  *
361*4882a593Smuzhiyun  * This function defines/destroys a screen target
362*4882a593Smuzhiyun  *
363*4882a593Smuzhiyun  */
vmw_stdu_crtc_mode_set_nofb(struct drm_crtc * crtc)364*4882a593Smuzhiyun static void vmw_stdu_crtc_mode_set_nofb(struct drm_crtc *crtc)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun 	struct vmw_private *dev_priv;
367*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu;
368*4882a593Smuzhiyun 	struct drm_connector_state *conn_state;
369*4882a593Smuzhiyun 	struct vmw_connector_state *vmw_conn_state;
370*4882a593Smuzhiyun 	int x, y, ret;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	stdu = vmw_crtc_to_stdu(crtc);
373*4882a593Smuzhiyun 	dev_priv = vmw_priv(crtc->dev);
374*4882a593Smuzhiyun 	conn_state = stdu->base.connector.state;
375*4882a593Smuzhiyun 	vmw_conn_state = vmw_connector_state_to_vcs(conn_state);
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	if (stdu->defined) {
378*4882a593Smuzhiyun 		ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
379*4882a593Smuzhiyun 		if (ret)
380*4882a593Smuzhiyun 			DRM_ERROR("Failed to blank CRTC\n");
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 		(void) vmw_stdu_update_st(dev_priv, stdu);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 		ret = vmw_stdu_destroy_st(dev_priv, stdu);
385*4882a593Smuzhiyun 		if (ret)
386*4882a593Smuzhiyun 			DRM_ERROR("Failed to destroy Screen Target\n");
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 		stdu->content_fb_type = SAME_AS_DISPLAY;
389*4882a593Smuzhiyun 	}
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	if (!crtc->state->enable)
392*4882a593Smuzhiyun 		return;
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	x = vmw_conn_state->gui_x;
395*4882a593Smuzhiyun 	y = vmw_conn_state->gui_y;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	vmw_svga_enable(dev_priv);
398*4882a593Smuzhiyun 	ret = vmw_stdu_define_st(dev_priv, stdu, &crtc->mode, x, y);
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	if (ret)
401*4882a593Smuzhiyun 		DRM_ERROR("Failed to define Screen Target of size %dx%d\n",
402*4882a593Smuzhiyun 			  crtc->x, crtc->y);
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 
vmw_stdu_crtc_helper_prepare(struct drm_crtc * crtc)406*4882a593Smuzhiyun static void vmw_stdu_crtc_helper_prepare(struct drm_crtc *crtc)
407*4882a593Smuzhiyun {
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun 
vmw_stdu_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)410*4882a593Smuzhiyun static void vmw_stdu_crtc_atomic_enable(struct drm_crtc *crtc,
411*4882a593Smuzhiyun 					struct drm_crtc_state *old_state)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun 
vmw_stdu_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)415*4882a593Smuzhiyun static void vmw_stdu_crtc_atomic_disable(struct drm_crtc *crtc,
416*4882a593Smuzhiyun 					 struct drm_crtc_state *old_state)
417*4882a593Smuzhiyun {
418*4882a593Smuzhiyun 	struct vmw_private *dev_priv;
419*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu;
420*4882a593Smuzhiyun 	int ret;
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	if (!crtc) {
424*4882a593Smuzhiyun 		DRM_ERROR("CRTC is NULL\n");
425*4882a593Smuzhiyun 		return;
426*4882a593Smuzhiyun 	}
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	stdu     = vmw_crtc_to_stdu(crtc);
429*4882a593Smuzhiyun 	dev_priv = vmw_priv(crtc->dev);
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	if (stdu->defined) {
432*4882a593Smuzhiyun 		ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
433*4882a593Smuzhiyun 		if (ret)
434*4882a593Smuzhiyun 			DRM_ERROR("Failed to blank CRTC\n");
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 		(void) vmw_stdu_update_st(dev_priv, stdu);
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 		ret = vmw_stdu_destroy_st(dev_priv, stdu);
439*4882a593Smuzhiyun 		if (ret)
440*4882a593Smuzhiyun 			DRM_ERROR("Failed to destroy Screen Target\n");
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 		stdu->content_fb_type = SAME_AS_DISPLAY;
443*4882a593Smuzhiyun 	}
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun /**
447*4882a593Smuzhiyun  * vmw_stdu_bo_clip - Callback to encode a suface DMA command cliprect
448*4882a593Smuzhiyun  *
449*4882a593Smuzhiyun  * @dirty: The closure structure.
450*4882a593Smuzhiyun  *
451*4882a593Smuzhiyun  * Encodes a surface DMA command cliprect and updates the bounding box
452*4882a593Smuzhiyun  * for the DMA.
453*4882a593Smuzhiyun  */
vmw_stdu_bo_clip(struct vmw_kms_dirty * dirty)454*4882a593Smuzhiyun static void vmw_stdu_bo_clip(struct vmw_kms_dirty *dirty)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun 	struct vmw_stdu_dirty *ddirty =
457*4882a593Smuzhiyun 		container_of(dirty, struct vmw_stdu_dirty, base);
458*4882a593Smuzhiyun 	struct vmw_stdu_dma *cmd = dirty->cmd;
459*4882a593Smuzhiyun 	struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	blit += dirty->num_hits;
462*4882a593Smuzhiyun 	blit->srcx = dirty->fb_x;
463*4882a593Smuzhiyun 	blit->srcy = dirty->fb_y;
464*4882a593Smuzhiyun 	blit->x = dirty->unit_x1;
465*4882a593Smuzhiyun 	blit->y = dirty->unit_y1;
466*4882a593Smuzhiyun 	blit->d = 1;
467*4882a593Smuzhiyun 	blit->w = dirty->unit_x2 - dirty->unit_x1;
468*4882a593Smuzhiyun 	blit->h = dirty->unit_y2 - dirty->unit_y1;
469*4882a593Smuzhiyun 	dirty->num_hits++;
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM)
472*4882a593Smuzhiyun 		return;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	/* Destination bounding box */
475*4882a593Smuzhiyun 	ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1);
476*4882a593Smuzhiyun 	ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1);
477*4882a593Smuzhiyun 	ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2);
478*4882a593Smuzhiyun 	ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2);
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun /**
482*4882a593Smuzhiyun  * vmw_stdu_bo_fifo_commit - Callback to fill in and submit a DMA command.
483*4882a593Smuzhiyun  *
484*4882a593Smuzhiyun  * @dirty: The closure structure.
485*4882a593Smuzhiyun  *
486*4882a593Smuzhiyun  * Fills in the missing fields in a DMA command, and optionally encodes
487*4882a593Smuzhiyun  * a screen target update command, depending on transfer direction.
488*4882a593Smuzhiyun  */
vmw_stdu_bo_fifo_commit(struct vmw_kms_dirty * dirty)489*4882a593Smuzhiyun static void vmw_stdu_bo_fifo_commit(struct vmw_kms_dirty *dirty)
490*4882a593Smuzhiyun {
491*4882a593Smuzhiyun 	struct vmw_stdu_dirty *ddirty =
492*4882a593Smuzhiyun 		container_of(dirty, struct vmw_stdu_dirty, base);
493*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu =
494*4882a593Smuzhiyun 		container_of(dirty->unit, typeof(*stdu), base);
495*4882a593Smuzhiyun 	struct vmw_stdu_dma *cmd = dirty->cmd;
496*4882a593Smuzhiyun 	struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
497*4882a593Smuzhiyun 	SVGA3dCmdSurfaceDMASuffix *suffix =
498*4882a593Smuzhiyun 		(SVGA3dCmdSurfaceDMASuffix *) &blit[dirty->num_hits];
499*4882a593Smuzhiyun 	size_t blit_size = sizeof(*blit) * dirty->num_hits + sizeof(*suffix);
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	if (!dirty->num_hits) {
502*4882a593Smuzhiyun 		vmw_fifo_commit(dirty->dev_priv, 0);
503*4882a593Smuzhiyun 		return;
504*4882a593Smuzhiyun 	}
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 	cmd->header.id = SVGA_3D_CMD_SURFACE_DMA;
507*4882a593Smuzhiyun 	cmd->header.size = sizeof(cmd->body) + blit_size;
508*4882a593Smuzhiyun 	vmw_bo_get_guest_ptr(&ddirty->buf->base, &cmd->body.guest.ptr);
509*4882a593Smuzhiyun 	cmd->body.guest.pitch = ddirty->pitch;
510*4882a593Smuzhiyun 	cmd->body.host.sid = stdu->display_srf->res.id;
511*4882a593Smuzhiyun 	cmd->body.host.face = 0;
512*4882a593Smuzhiyun 	cmd->body.host.mipmap = 0;
513*4882a593Smuzhiyun 	cmd->body.transfer = ddirty->transfer;
514*4882a593Smuzhiyun 	suffix->suffixSize = sizeof(*suffix);
515*4882a593Smuzhiyun 	suffix->maximumOffset = ddirty->buf->base.num_pages * PAGE_SIZE;
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun 	if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM) {
518*4882a593Smuzhiyun 		blit_size += sizeof(struct vmw_stdu_update);
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 		vmw_stdu_populate_update(&suffix[1], stdu->base.unit,
521*4882a593Smuzhiyun 					 ddirty->left, ddirty->right,
522*4882a593Smuzhiyun 					 ddirty->top, ddirty->bottom);
523*4882a593Smuzhiyun 	}
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun 	vmw_fifo_commit(dirty->dev_priv, sizeof(*cmd) + blit_size);
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	stdu->display_srf->res.res_dirty = true;
528*4882a593Smuzhiyun 	ddirty->left = ddirty->top = S32_MAX;
529*4882a593Smuzhiyun 	ddirty->right = ddirty->bottom = S32_MIN;
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun /**
534*4882a593Smuzhiyun  * vmw_stdu_bo_cpu_clip - Callback to encode a CPU blit
535*4882a593Smuzhiyun  *
536*4882a593Smuzhiyun  * @dirty: The closure structure.
537*4882a593Smuzhiyun  *
538*4882a593Smuzhiyun  * This function calculates the bounding box for all the incoming clips.
539*4882a593Smuzhiyun  */
vmw_stdu_bo_cpu_clip(struct vmw_kms_dirty * dirty)540*4882a593Smuzhiyun static void vmw_stdu_bo_cpu_clip(struct vmw_kms_dirty *dirty)
541*4882a593Smuzhiyun {
542*4882a593Smuzhiyun 	struct vmw_stdu_dirty *ddirty =
543*4882a593Smuzhiyun 		container_of(dirty, struct vmw_stdu_dirty, base);
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 	dirty->num_hits = 1;
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun 	/* Calculate destination bounding box */
548*4882a593Smuzhiyun 	ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1);
549*4882a593Smuzhiyun 	ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1);
550*4882a593Smuzhiyun 	ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2);
551*4882a593Smuzhiyun 	ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2);
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	/*
554*4882a593Smuzhiyun 	 * Calculate content bounding box.  We only need the top-left
555*4882a593Smuzhiyun 	 * coordinate because width and height will be the same as the
556*4882a593Smuzhiyun 	 * destination bounding box above
557*4882a593Smuzhiyun 	 */
558*4882a593Smuzhiyun 	ddirty->fb_left = min_t(s32, ddirty->fb_left, dirty->fb_x);
559*4882a593Smuzhiyun 	ddirty->fb_top  = min_t(s32, ddirty->fb_top, dirty->fb_y);
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun /**
564*4882a593Smuzhiyun  * vmw_stdu_bo_cpu_commit - Callback to do a CPU blit from buffer object
565*4882a593Smuzhiyun  *
566*4882a593Smuzhiyun  * @dirty: The closure structure.
567*4882a593Smuzhiyun  *
568*4882a593Smuzhiyun  * For the special case when we cannot create a proxy surface in a
569*4882a593Smuzhiyun  * 2D VM, we have to do a CPU blit ourselves.
570*4882a593Smuzhiyun  */
vmw_stdu_bo_cpu_commit(struct vmw_kms_dirty * dirty)571*4882a593Smuzhiyun static void vmw_stdu_bo_cpu_commit(struct vmw_kms_dirty *dirty)
572*4882a593Smuzhiyun {
573*4882a593Smuzhiyun 	struct vmw_stdu_dirty *ddirty =
574*4882a593Smuzhiyun 		container_of(dirty, struct vmw_stdu_dirty, base);
575*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu =
576*4882a593Smuzhiyun 		container_of(dirty->unit, typeof(*stdu), base);
577*4882a593Smuzhiyun 	s32 width, height;
578*4882a593Smuzhiyun 	s32 src_pitch, dst_pitch;
579*4882a593Smuzhiyun 	struct ttm_buffer_object *src_bo, *dst_bo;
580*4882a593Smuzhiyun 	u32 src_offset, dst_offset;
581*4882a593Smuzhiyun 	struct vmw_diff_cpy diff = VMW_CPU_BLIT_DIFF_INITIALIZER(stdu->cpp);
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 	if (!dirty->num_hits)
584*4882a593Smuzhiyun 		return;
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	width = ddirty->right - ddirty->left;
587*4882a593Smuzhiyun 	height = ddirty->bottom - ddirty->top;
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	if (width == 0 || height == 0)
590*4882a593Smuzhiyun 		return;
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	/* Assume we are blitting from Guest (bo) to Host (display_srf) */
593*4882a593Smuzhiyun 	dst_pitch = stdu->display_srf->metadata.base_size.width * stdu->cpp;
594*4882a593Smuzhiyun 	dst_bo = &stdu->display_srf->res.backup->base;
595*4882a593Smuzhiyun 	dst_offset = ddirty->top * dst_pitch + ddirty->left * stdu->cpp;
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	src_pitch = ddirty->pitch;
598*4882a593Smuzhiyun 	src_bo = &ddirty->buf->base;
599*4882a593Smuzhiyun 	src_offset = ddirty->fb_top * src_pitch + ddirty->fb_left * stdu->cpp;
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	/* Swap src and dst if the assumption was wrong. */
602*4882a593Smuzhiyun 	if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM) {
603*4882a593Smuzhiyun 		swap(dst_pitch, src_pitch);
604*4882a593Smuzhiyun 		swap(dst_bo, src_bo);
605*4882a593Smuzhiyun 		swap(src_offset, dst_offset);
606*4882a593Smuzhiyun 	}
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	(void) vmw_bo_cpu_blit(dst_bo, dst_offset, dst_pitch,
609*4882a593Smuzhiyun 			       src_bo, src_offset, src_pitch,
610*4882a593Smuzhiyun 			       width * stdu->cpp, height, &diff);
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 	if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM &&
613*4882a593Smuzhiyun 	    drm_rect_visible(&diff.rect)) {
614*4882a593Smuzhiyun 		struct vmw_private *dev_priv;
615*4882a593Smuzhiyun 		struct vmw_stdu_update *cmd;
616*4882a593Smuzhiyun 		struct drm_clip_rect region;
617*4882a593Smuzhiyun 		int ret;
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun 		/* We are updating the actual surface, not a proxy */
620*4882a593Smuzhiyun 		region.x1 = diff.rect.x1;
621*4882a593Smuzhiyun 		region.x2 = diff.rect.x2;
622*4882a593Smuzhiyun 		region.y1 = diff.rect.y1;
623*4882a593Smuzhiyun 		region.y2 = diff.rect.y2;
624*4882a593Smuzhiyun 		ret = vmw_kms_update_proxy(&stdu->display_srf->res, &region,
625*4882a593Smuzhiyun 					   1, 1);
626*4882a593Smuzhiyun 		if (ret)
627*4882a593Smuzhiyun 			goto out_cleanup;
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 		dev_priv = vmw_priv(stdu->base.crtc.dev);
631*4882a593Smuzhiyun 		cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
632*4882a593Smuzhiyun 		if (!cmd)
633*4882a593Smuzhiyun 			goto out_cleanup;
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 		vmw_stdu_populate_update(cmd, stdu->base.unit,
636*4882a593Smuzhiyun 					 region.x1, region.x2,
637*4882a593Smuzhiyun 					 region.y1, region.y2);
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun 		vmw_fifo_commit(dev_priv, sizeof(*cmd));
640*4882a593Smuzhiyun 	}
641*4882a593Smuzhiyun 
642*4882a593Smuzhiyun out_cleanup:
643*4882a593Smuzhiyun 	ddirty->left = ddirty->top = ddirty->fb_left = ddirty->fb_top = S32_MAX;
644*4882a593Smuzhiyun 	ddirty->right = ddirty->bottom = S32_MIN;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun /**
648*4882a593Smuzhiyun  * vmw_kms_stdu_dma - Perform a DMA transfer between a buffer-object backed
649*4882a593Smuzhiyun  * framebuffer and the screen target system.
650*4882a593Smuzhiyun  *
651*4882a593Smuzhiyun  * @dev_priv: Pointer to the device private structure.
652*4882a593Smuzhiyun  * @file_priv: Pointer to a struct drm-file identifying the caller. May be
653*4882a593Smuzhiyun  * set to NULL, but then @user_fence_rep must also be set to NULL.
654*4882a593Smuzhiyun  * @vfb: Pointer to the buffer-object backed framebuffer.
655*4882a593Smuzhiyun  * @clips: Array of clip rects. Either @clips or @vclips must be NULL.
656*4882a593Smuzhiyun  * @vclips: Alternate array of clip rects. Either @clips or @vclips must
657*4882a593Smuzhiyun  * be NULL.
658*4882a593Smuzhiyun  * @num_clips: Number of clip rects in @clips or @vclips.
659*4882a593Smuzhiyun  * @increment: Increment to use when looping over @clips or @vclips.
660*4882a593Smuzhiyun  * @to_surface: Whether to DMA to the screen target system as opposed to
661*4882a593Smuzhiyun  * from the screen target system.
662*4882a593Smuzhiyun  * @interruptible: Whether to perform waits interruptible if possible.
663*4882a593Smuzhiyun  * @crtc: If crtc is passed, perform stdu dma on that crtc only.
664*4882a593Smuzhiyun  *
665*4882a593Smuzhiyun  * If DMA-ing till the screen target system, the function will also notify
666*4882a593Smuzhiyun  * the screen target system that a bounding box of the cliprects has been
667*4882a593Smuzhiyun  * updated.
668*4882a593Smuzhiyun  * Returns 0 on success, negative error code on failure. -ERESTARTSYS if
669*4882a593Smuzhiyun  * interrupted.
670*4882a593Smuzhiyun  */
vmw_kms_stdu_dma(struct vmw_private * dev_priv,struct drm_file * file_priv,struct vmw_framebuffer * vfb,struct drm_vmw_fence_rep __user * user_fence_rep,struct drm_clip_rect * clips,struct drm_vmw_rect * vclips,uint32_t num_clips,int increment,bool to_surface,bool interruptible,struct drm_crtc * crtc)671*4882a593Smuzhiyun int vmw_kms_stdu_dma(struct vmw_private *dev_priv,
672*4882a593Smuzhiyun 		     struct drm_file *file_priv,
673*4882a593Smuzhiyun 		     struct vmw_framebuffer *vfb,
674*4882a593Smuzhiyun 		     struct drm_vmw_fence_rep __user *user_fence_rep,
675*4882a593Smuzhiyun 		     struct drm_clip_rect *clips,
676*4882a593Smuzhiyun 		     struct drm_vmw_rect *vclips,
677*4882a593Smuzhiyun 		     uint32_t num_clips,
678*4882a593Smuzhiyun 		     int increment,
679*4882a593Smuzhiyun 		     bool to_surface,
680*4882a593Smuzhiyun 		     bool interruptible,
681*4882a593Smuzhiyun 		     struct drm_crtc *crtc)
682*4882a593Smuzhiyun {
683*4882a593Smuzhiyun 	struct vmw_buffer_object *buf =
684*4882a593Smuzhiyun 		container_of(vfb, struct vmw_framebuffer_bo, base)->buffer;
685*4882a593Smuzhiyun 	struct vmw_stdu_dirty ddirty;
686*4882a593Smuzhiyun 	int ret;
687*4882a593Smuzhiyun 	bool cpu_blit = !(dev_priv->capabilities & SVGA_CAP_3D);
688*4882a593Smuzhiyun 	DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun 	/*
691*4882a593Smuzhiyun 	 * VMs without 3D support don't have the surface DMA command and
692*4882a593Smuzhiyun 	 * we'll be using a CPU blit, and the framebuffer should be moved out
693*4882a593Smuzhiyun 	 * of VRAM.
694*4882a593Smuzhiyun 	 */
695*4882a593Smuzhiyun 	ret = vmw_validation_add_bo(&val_ctx, buf, false, cpu_blit);
696*4882a593Smuzhiyun 	if (ret)
697*4882a593Smuzhiyun 		return ret;
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun 	ret = vmw_validation_prepare(&val_ctx, NULL, interruptible);
700*4882a593Smuzhiyun 	if (ret)
701*4882a593Smuzhiyun 		goto out_unref;
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	ddirty.transfer = (to_surface) ? SVGA3D_WRITE_HOST_VRAM :
704*4882a593Smuzhiyun 		SVGA3D_READ_HOST_VRAM;
705*4882a593Smuzhiyun 	ddirty.left = ddirty.top = S32_MAX;
706*4882a593Smuzhiyun 	ddirty.right = ddirty.bottom = S32_MIN;
707*4882a593Smuzhiyun 	ddirty.fb_left = ddirty.fb_top = S32_MAX;
708*4882a593Smuzhiyun 	ddirty.pitch = vfb->base.pitches[0];
709*4882a593Smuzhiyun 	ddirty.buf = buf;
710*4882a593Smuzhiyun 	ddirty.base.fifo_commit = vmw_stdu_bo_fifo_commit;
711*4882a593Smuzhiyun 	ddirty.base.clip = vmw_stdu_bo_clip;
712*4882a593Smuzhiyun 	ddirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_dma) +
713*4882a593Smuzhiyun 		num_clips * sizeof(SVGA3dCopyBox) +
714*4882a593Smuzhiyun 		sizeof(SVGA3dCmdSurfaceDMASuffix);
715*4882a593Smuzhiyun 	if (to_surface)
716*4882a593Smuzhiyun 		ddirty.base.fifo_reserve_size += sizeof(struct vmw_stdu_update);
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun 	if (cpu_blit) {
720*4882a593Smuzhiyun 		ddirty.base.fifo_commit = vmw_stdu_bo_cpu_commit;
721*4882a593Smuzhiyun 		ddirty.base.clip = vmw_stdu_bo_cpu_clip;
722*4882a593Smuzhiyun 		ddirty.base.fifo_reserve_size = 0;
723*4882a593Smuzhiyun 	}
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	ddirty.base.crtc = crtc;
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	ret = vmw_kms_helper_dirty(dev_priv, vfb, clips, vclips,
728*4882a593Smuzhiyun 				   0, 0, num_clips, increment, &ddirty.base);
729*4882a593Smuzhiyun 
730*4882a593Smuzhiyun 	vmw_kms_helper_validation_finish(dev_priv, file_priv, &val_ctx, NULL,
731*4882a593Smuzhiyun 					 user_fence_rep);
732*4882a593Smuzhiyun 	return ret;
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun out_unref:
735*4882a593Smuzhiyun 	vmw_validation_unref_lists(&val_ctx);
736*4882a593Smuzhiyun 	return ret;
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun /**
740*4882a593Smuzhiyun  * vmw_stdu_surface_clip - Callback to encode a surface copy command cliprect
741*4882a593Smuzhiyun  *
742*4882a593Smuzhiyun  * @dirty: The closure structure.
743*4882a593Smuzhiyun  *
744*4882a593Smuzhiyun  * Encodes a surface copy command cliprect and updates the bounding box
745*4882a593Smuzhiyun  * for the copy.
746*4882a593Smuzhiyun  */
vmw_kms_stdu_surface_clip(struct vmw_kms_dirty * dirty)747*4882a593Smuzhiyun static void vmw_kms_stdu_surface_clip(struct vmw_kms_dirty *dirty)
748*4882a593Smuzhiyun {
749*4882a593Smuzhiyun 	struct vmw_stdu_dirty *sdirty =
750*4882a593Smuzhiyun 		container_of(dirty, struct vmw_stdu_dirty, base);
751*4882a593Smuzhiyun 	struct vmw_stdu_surface_copy *cmd = dirty->cmd;
752*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu =
753*4882a593Smuzhiyun 		container_of(dirty->unit, typeof(*stdu), base);
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 	if (sdirty->sid != stdu->display_srf->res.id) {
756*4882a593Smuzhiyun 		struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
757*4882a593Smuzhiyun 
758*4882a593Smuzhiyun 		blit += dirty->num_hits;
759*4882a593Smuzhiyun 		blit->srcx = dirty->fb_x;
760*4882a593Smuzhiyun 		blit->srcy = dirty->fb_y;
761*4882a593Smuzhiyun 		blit->x = dirty->unit_x1;
762*4882a593Smuzhiyun 		blit->y = dirty->unit_y1;
763*4882a593Smuzhiyun 		blit->d = 1;
764*4882a593Smuzhiyun 		blit->w = dirty->unit_x2 - dirty->unit_x1;
765*4882a593Smuzhiyun 		blit->h = dirty->unit_y2 - dirty->unit_y1;
766*4882a593Smuzhiyun 	}
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun 	dirty->num_hits++;
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	/* Destination bounding box */
771*4882a593Smuzhiyun 	sdirty->left = min_t(s32, sdirty->left, dirty->unit_x1);
772*4882a593Smuzhiyun 	sdirty->top = min_t(s32, sdirty->top, dirty->unit_y1);
773*4882a593Smuzhiyun 	sdirty->right = max_t(s32, sdirty->right, dirty->unit_x2);
774*4882a593Smuzhiyun 	sdirty->bottom = max_t(s32, sdirty->bottom, dirty->unit_y2);
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun /**
778*4882a593Smuzhiyun  * vmw_stdu_surface_fifo_commit - Callback to fill in and submit a surface
779*4882a593Smuzhiyun  * copy command.
780*4882a593Smuzhiyun  *
781*4882a593Smuzhiyun  * @dirty: The closure structure.
782*4882a593Smuzhiyun  *
783*4882a593Smuzhiyun  * Fills in the missing fields in a surface copy command, and encodes a screen
784*4882a593Smuzhiyun  * target update command.
785*4882a593Smuzhiyun  */
vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty * dirty)786*4882a593Smuzhiyun static void vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty *dirty)
787*4882a593Smuzhiyun {
788*4882a593Smuzhiyun 	struct vmw_stdu_dirty *sdirty =
789*4882a593Smuzhiyun 		container_of(dirty, struct vmw_stdu_dirty, base);
790*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu =
791*4882a593Smuzhiyun 		container_of(dirty->unit, typeof(*stdu), base);
792*4882a593Smuzhiyun 	struct vmw_stdu_surface_copy *cmd = dirty->cmd;
793*4882a593Smuzhiyun 	struct vmw_stdu_update *update;
794*4882a593Smuzhiyun 	size_t blit_size = sizeof(SVGA3dCopyBox) * dirty->num_hits;
795*4882a593Smuzhiyun 	size_t commit_size;
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun 	if (!dirty->num_hits) {
798*4882a593Smuzhiyun 		vmw_fifo_commit(dirty->dev_priv, 0);
799*4882a593Smuzhiyun 		return;
800*4882a593Smuzhiyun 	}
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun 	if (sdirty->sid != stdu->display_srf->res.id) {
803*4882a593Smuzhiyun 		struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun 		cmd->header.id = SVGA_3D_CMD_SURFACE_COPY;
806*4882a593Smuzhiyun 		cmd->header.size = sizeof(cmd->body) + blit_size;
807*4882a593Smuzhiyun 		cmd->body.src.sid = sdirty->sid;
808*4882a593Smuzhiyun 		cmd->body.dest.sid = stdu->display_srf->res.id;
809*4882a593Smuzhiyun 		update = (struct vmw_stdu_update *) &blit[dirty->num_hits];
810*4882a593Smuzhiyun 		commit_size = sizeof(*cmd) + blit_size + sizeof(*update);
811*4882a593Smuzhiyun 		stdu->display_srf->res.res_dirty = true;
812*4882a593Smuzhiyun 	} else {
813*4882a593Smuzhiyun 		update = dirty->cmd;
814*4882a593Smuzhiyun 		commit_size = sizeof(*update);
815*4882a593Smuzhiyun 	}
816*4882a593Smuzhiyun 
817*4882a593Smuzhiyun 	vmw_stdu_populate_update(update, stdu->base.unit, sdirty->left,
818*4882a593Smuzhiyun 				 sdirty->right, sdirty->top, sdirty->bottom);
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	vmw_fifo_commit(dirty->dev_priv, commit_size);
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	sdirty->left = sdirty->top = S32_MAX;
823*4882a593Smuzhiyun 	sdirty->right = sdirty->bottom = S32_MIN;
824*4882a593Smuzhiyun }
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun /**
827*4882a593Smuzhiyun  * vmw_kms_stdu_surface_dirty - Dirty part of a surface backed framebuffer
828*4882a593Smuzhiyun  *
829*4882a593Smuzhiyun  * @dev_priv: Pointer to the device private structure.
830*4882a593Smuzhiyun  * @framebuffer: Pointer to the surface-buffer backed framebuffer.
831*4882a593Smuzhiyun  * @clips: Array of clip rects. Either @clips or @vclips must be NULL.
832*4882a593Smuzhiyun  * @vclips: Alternate array of clip rects. Either @clips or @vclips must
833*4882a593Smuzhiyun  * be NULL.
834*4882a593Smuzhiyun  * @srf: Pointer to surface to blit from. If NULL, the surface attached
835*4882a593Smuzhiyun  * to @framebuffer will be used.
836*4882a593Smuzhiyun  * @dest_x: X coordinate offset to align @srf with framebuffer coordinates.
837*4882a593Smuzhiyun  * @dest_y: Y coordinate offset to align @srf with framebuffer coordinates.
838*4882a593Smuzhiyun  * @num_clips: Number of clip rects in @clips.
839*4882a593Smuzhiyun  * @inc: Increment to use when looping over @clips.
840*4882a593Smuzhiyun  * @out_fence: If non-NULL, will return a ref-counted pointer to a
841*4882a593Smuzhiyun  * struct vmw_fence_obj. The returned fence pointer may be NULL in which
842*4882a593Smuzhiyun  * case the device has already synchronized.
843*4882a593Smuzhiyun  * @crtc: If crtc is passed, perform surface dirty on that crtc only.
844*4882a593Smuzhiyun  *
845*4882a593Smuzhiyun  * Returns 0 on success, negative error code on failure. -ERESTARTSYS if
846*4882a593Smuzhiyun  * interrupted.
847*4882a593Smuzhiyun  */
vmw_kms_stdu_surface_dirty(struct vmw_private * dev_priv,struct vmw_framebuffer * framebuffer,struct drm_clip_rect * clips,struct drm_vmw_rect * vclips,struct vmw_resource * srf,s32 dest_x,s32 dest_y,unsigned num_clips,int inc,struct vmw_fence_obj ** out_fence,struct drm_crtc * crtc)848*4882a593Smuzhiyun int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv,
849*4882a593Smuzhiyun 			       struct vmw_framebuffer *framebuffer,
850*4882a593Smuzhiyun 			       struct drm_clip_rect *clips,
851*4882a593Smuzhiyun 			       struct drm_vmw_rect *vclips,
852*4882a593Smuzhiyun 			       struct vmw_resource *srf,
853*4882a593Smuzhiyun 			       s32 dest_x,
854*4882a593Smuzhiyun 			       s32 dest_y,
855*4882a593Smuzhiyun 			       unsigned num_clips, int inc,
856*4882a593Smuzhiyun 			       struct vmw_fence_obj **out_fence,
857*4882a593Smuzhiyun 			       struct drm_crtc *crtc)
858*4882a593Smuzhiyun {
859*4882a593Smuzhiyun 	struct vmw_framebuffer_surface *vfbs =
860*4882a593Smuzhiyun 		container_of(framebuffer, typeof(*vfbs), base);
861*4882a593Smuzhiyun 	struct vmw_stdu_dirty sdirty;
862*4882a593Smuzhiyun 	DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
863*4882a593Smuzhiyun 	int ret;
864*4882a593Smuzhiyun 
865*4882a593Smuzhiyun 	if (!srf)
866*4882a593Smuzhiyun 		srf = &vfbs->surface->res;
867*4882a593Smuzhiyun 
868*4882a593Smuzhiyun 	ret = vmw_validation_add_resource(&val_ctx, srf, 0, VMW_RES_DIRTY_NONE,
869*4882a593Smuzhiyun 					  NULL, NULL);
870*4882a593Smuzhiyun 	if (ret)
871*4882a593Smuzhiyun 		return ret;
872*4882a593Smuzhiyun 
873*4882a593Smuzhiyun 	ret = vmw_validation_prepare(&val_ctx, &dev_priv->cmdbuf_mutex, true);
874*4882a593Smuzhiyun 	if (ret)
875*4882a593Smuzhiyun 		goto out_unref;
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	if (vfbs->is_bo_proxy) {
878*4882a593Smuzhiyun 		ret = vmw_kms_update_proxy(srf, clips, num_clips, inc);
879*4882a593Smuzhiyun 		if (ret)
880*4882a593Smuzhiyun 			goto out_finish;
881*4882a593Smuzhiyun 	}
882*4882a593Smuzhiyun 
883*4882a593Smuzhiyun 	sdirty.base.fifo_commit = vmw_kms_stdu_surface_fifo_commit;
884*4882a593Smuzhiyun 	sdirty.base.clip = vmw_kms_stdu_surface_clip;
885*4882a593Smuzhiyun 	sdirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_surface_copy) +
886*4882a593Smuzhiyun 		sizeof(SVGA3dCopyBox) * num_clips +
887*4882a593Smuzhiyun 		sizeof(struct vmw_stdu_update);
888*4882a593Smuzhiyun 	sdirty.base.crtc = crtc;
889*4882a593Smuzhiyun 	sdirty.sid = srf->id;
890*4882a593Smuzhiyun 	sdirty.left = sdirty.top = S32_MAX;
891*4882a593Smuzhiyun 	sdirty.right = sdirty.bottom = S32_MIN;
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun 	ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
894*4882a593Smuzhiyun 				   dest_x, dest_y, num_clips, inc,
895*4882a593Smuzhiyun 				   &sdirty.base);
896*4882a593Smuzhiyun out_finish:
897*4882a593Smuzhiyun 	vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence,
898*4882a593Smuzhiyun 					 NULL);
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun 	return ret;
901*4882a593Smuzhiyun 
902*4882a593Smuzhiyun out_unref:
903*4882a593Smuzhiyun 	vmw_validation_unref_lists(&val_ctx);
904*4882a593Smuzhiyun 	return ret;
905*4882a593Smuzhiyun }
906*4882a593Smuzhiyun 
907*4882a593Smuzhiyun 
908*4882a593Smuzhiyun /*
909*4882a593Smuzhiyun  *  Screen Target CRTC dispatch table
910*4882a593Smuzhiyun  */
911*4882a593Smuzhiyun static const struct drm_crtc_funcs vmw_stdu_crtc_funcs = {
912*4882a593Smuzhiyun 	.gamma_set = vmw_du_crtc_gamma_set,
913*4882a593Smuzhiyun 	.destroy = vmw_stdu_crtc_destroy,
914*4882a593Smuzhiyun 	.reset = vmw_du_crtc_reset,
915*4882a593Smuzhiyun 	.atomic_duplicate_state = vmw_du_crtc_duplicate_state,
916*4882a593Smuzhiyun 	.atomic_destroy_state = vmw_du_crtc_destroy_state,
917*4882a593Smuzhiyun 	.set_config = drm_atomic_helper_set_config,
918*4882a593Smuzhiyun 	.page_flip = drm_atomic_helper_page_flip,
919*4882a593Smuzhiyun 	.get_vblank_counter = vmw_get_vblank_counter,
920*4882a593Smuzhiyun 	.enable_vblank = vmw_enable_vblank,
921*4882a593Smuzhiyun 	.disable_vblank = vmw_disable_vblank,
922*4882a593Smuzhiyun };
923*4882a593Smuzhiyun 
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 
926*4882a593Smuzhiyun /******************************************************************************
927*4882a593Smuzhiyun  * Screen Target Display Unit Encoder Functions
928*4882a593Smuzhiyun  *****************************************************************************/
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun /**
931*4882a593Smuzhiyun  * vmw_stdu_encoder_destroy - cleans up the STDU
932*4882a593Smuzhiyun  *
933*4882a593Smuzhiyun  * @encoder: used the get the containing STDU
934*4882a593Smuzhiyun  *
935*4882a593Smuzhiyun  * vmwgfx cleans up crtc/encoder/connector all at the same time so technically
936*4882a593Smuzhiyun  * this can be a no-op.  Nevertheless, it doesn't hurt of have this in case
937*4882a593Smuzhiyun  * the common KMS code changes and somehow vmw_stdu_crtc_destroy() doesn't
938*4882a593Smuzhiyun  * get called.
939*4882a593Smuzhiyun  */
vmw_stdu_encoder_destroy(struct drm_encoder * encoder)940*4882a593Smuzhiyun static void vmw_stdu_encoder_destroy(struct drm_encoder *encoder)
941*4882a593Smuzhiyun {
942*4882a593Smuzhiyun 	vmw_stdu_destroy(vmw_encoder_to_stdu(encoder));
943*4882a593Smuzhiyun }
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun static const struct drm_encoder_funcs vmw_stdu_encoder_funcs = {
946*4882a593Smuzhiyun 	.destroy = vmw_stdu_encoder_destroy,
947*4882a593Smuzhiyun };
948*4882a593Smuzhiyun 
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun 
951*4882a593Smuzhiyun /******************************************************************************
952*4882a593Smuzhiyun  * Screen Target Display Unit Connector Functions
953*4882a593Smuzhiyun  *****************************************************************************/
954*4882a593Smuzhiyun 
955*4882a593Smuzhiyun /**
956*4882a593Smuzhiyun  * vmw_stdu_connector_destroy - cleans up the STDU
957*4882a593Smuzhiyun  *
958*4882a593Smuzhiyun  * @connector: used to get the containing STDU
959*4882a593Smuzhiyun  *
960*4882a593Smuzhiyun  * vmwgfx cleans up crtc/encoder/connector all at the same time so technically
961*4882a593Smuzhiyun  * this can be a no-op.  Nevertheless, it doesn't hurt of have this in case
962*4882a593Smuzhiyun  * the common KMS code changes and somehow vmw_stdu_crtc_destroy() doesn't
963*4882a593Smuzhiyun  * get called.
964*4882a593Smuzhiyun  */
vmw_stdu_connector_destroy(struct drm_connector * connector)965*4882a593Smuzhiyun static void vmw_stdu_connector_destroy(struct drm_connector *connector)
966*4882a593Smuzhiyun {
967*4882a593Smuzhiyun 	vmw_stdu_destroy(vmw_connector_to_stdu(connector));
968*4882a593Smuzhiyun }
969*4882a593Smuzhiyun 
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun 
972*4882a593Smuzhiyun static const struct drm_connector_funcs vmw_stdu_connector_funcs = {
973*4882a593Smuzhiyun 	.dpms = vmw_du_connector_dpms,
974*4882a593Smuzhiyun 	.detect = vmw_du_connector_detect,
975*4882a593Smuzhiyun 	.fill_modes = vmw_du_connector_fill_modes,
976*4882a593Smuzhiyun 	.destroy = vmw_stdu_connector_destroy,
977*4882a593Smuzhiyun 	.reset = vmw_du_connector_reset,
978*4882a593Smuzhiyun 	.atomic_duplicate_state = vmw_du_connector_duplicate_state,
979*4882a593Smuzhiyun 	.atomic_destroy_state = vmw_du_connector_destroy_state,
980*4882a593Smuzhiyun };
981*4882a593Smuzhiyun 
982*4882a593Smuzhiyun 
983*4882a593Smuzhiyun static const struct
984*4882a593Smuzhiyun drm_connector_helper_funcs vmw_stdu_connector_helper_funcs = {
985*4882a593Smuzhiyun };
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun 
988*4882a593Smuzhiyun 
989*4882a593Smuzhiyun /******************************************************************************
990*4882a593Smuzhiyun  * Screen Target Display Plane Functions
991*4882a593Smuzhiyun  *****************************************************************************/
992*4882a593Smuzhiyun 
993*4882a593Smuzhiyun 
994*4882a593Smuzhiyun 
995*4882a593Smuzhiyun /**
996*4882a593Smuzhiyun  * vmw_stdu_primary_plane_cleanup_fb - Unpins the display surface
997*4882a593Smuzhiyun  *
998*4882a593Smuzhiyun  * @plane:  display plane
999*4882a593Smuzhiyun  * @old_state: Contains the FB to clean up
1000*4882a593Smuzhiyun  *
1001*4882a593Smuzhiyun  * Unpins the display surface
1002*4882a593Smuzhiyun  *
1003*4882a593Smuzhiyun  * Returns 0 on success
1004*4882a593Smuzhiyun  */
1005*4882a593Smuzhiyun static void
vmw_stdu_primary_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * old_state)1006*4882a593Smuzhiyun vmw_stdu_primary_plane_cleanup_fb(struct drm_plane *plane,
1007*4882a593Smuzhiyun 				  struct drm_plane_state *old_state)
1008*4882a593Smuzhiyun {
1009*4882a593Smuzhiyun 	struct vmw_plane_state *vps = vmw_plane_state_to_vps(old_state);
1010*4882a593Smuzhiyun 
1011*4882a593Smuzhiyun 	if (vps->surf)
1012*4882a593Smuzhiyun 		WARN_ON(!vps->pinned);
1013*4882a593Smuzhiyun 
1014*4882a593Smuzhiyun 	vmw_du_plane_cleanup_fb(plane, old_state);
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	vps->content_fb_type = SAME_AS_DISPLAY;
1017*4882a593Smuzhiyun 	vps->cpp = 0;
1018*4882a593Smuzhiyun }
1019*4882a593Smuzhiyun 
1020*4882a593Smuzhiyun 
1021*4882a593Smuzhiyun 
1022*4882a593Smuzhiyun /**
1023*4882a593Smuzhiyun  * vmw_stdu_primary_plane_prepare_fb - Readies the display surface
1024*4882a593Smuzhiyun  *
1025*4882a593Smuzhiyun  * @plane:  display plane
1026*4882a593Smuzhiyun  * @new_state: info on the new plane state, including the FB
1027*4882a593Smuzhiyun  *
1028*4882a593Smuzhiyun  * This function allocates a new display surface if the content is
1029*4882a593Smuzhiyun  * backed by a buffer object.  The display surface is pinned here, and it'll
1030*4882a593Smuzhiyun  * be unpinned in .cleanup_fb()
1031*4882a593Smuzhiyun  *
1032*4882a593Smuzhiyun  * Returns 0 on success
1033*4882a593Smuzhiyun  */
1034*4882a593Smuzhiyun static int
vmw_stdu_primary_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)1035*4882a593Smuzhiyun vmw_stdu_primary_plane_prepare_fb(struct drm_plane *plane,
1036*4882a593Smuzhiyun 				  struct drm_plane_state *new_state)
1037*4882a593Smuzhiyun {
1038*4882a593Smuzhiyun 	struct vmw_private *dev_priv = vmw_priv(plane->dev);
1039*4882a593Smuzhiyun 	struct drm_framebuffer *new_fb = new_state->fb;
1040*4882a593Smuzhiyun 	struct vmw_framebuffer *vfb;
1041*4882a593Smuzhiyun 	struct vmw_plane_state *vps = vmw_plane_state_to_vps(new_state);
1042*4882a593Smuzhiyun 	enum stdu_content_type new_content_type;
1043*4882a593Smuzhiyun 	struct vmw_framebuffer_surface *new_vfbs;
1044*4882a593Smuzhiyun 	uint32_t hdisplay = new_state->crtc_w, vdisplay = new_state->crtc_h;
1045*4882a593Smuzhiyun 	int ret;
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun 	/* No FB to prepare */
1048*4882a593Smuzhiyun 	if (!new_fb) {
1049*4882a593Smuzhiyun 		if (vps->surf) {
1050*4882a593Smuzhiyun 			WARN_ON(vps->pinned != 0);
1051*4882a593Smuzhiyun 			vmw_surface_unreference(&vps->surf);
1052*4882a593Smuzhiyun 		}
1053*4882a593Smuzhiyun 
1054*4882a593Smuzhiyun 		return 0;
1055*4882a593Smuzhiyun 	}
1056*4882a593Smuzhiyun 
1057*4882a593Smuzhiyun 	vfb = vmw_framebuffer_to_vfb(new_fb);
1058*4882a593Smuzhiyun 	new_vfbs = (vfb->bo) ? NULL : vmw_framebuffer_to_vfbs(new_fb);
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun 	if (new_vfbs &&
1061*4882a593Smuzhiyun 	    new_vfbs->surface->metadata.base_size.width == hdisplay &&
1062*4882a593Smuzhiyun 	    new_vfbs->surface->metadata.base_size.height == vdisplay)
1063*4882a593Smuzhiyun 		new_content_type = SAME_AS_DISPLAY;
1064*4882a593Smuzhiyun 	else if (vfb->bo)
1065*4882a593Smuzhiyun 		new_content_type = SEPARATE_BO;
1066*4882a593Smuzhiyun 	else
1067*4882a593Smuzhiyun 		new_content_type = SEPARATE_SURFACE;
1068*4882a593Smuzhiyun 
1069*4882a593Smuzhiyun 	if (new_content_type != SAME_AS_DISPLAY) {
1070*4882a593Smuzhiyun 		struct vmw_surface_metadata metadata = {0};
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 		/*
1073*4882a593Smuzhiyun 		 * If content buffer is a buffer object, then we have to
1074*4882a593Smuzhiyun 		 * construct surface info
1075*4882a593Smuzhiyun 		 */
1076*4882a593Smuzhiyun 		if (new_content_type == SEPARATE_BO) {
1077*4882a593Smuzhiyun 
1078*4882a593Smuzhiyun 			switch (new_fb->format->cpp[0]*8) {
1079*4882a593Smuzhiyun 			case 32:
1080*4882a593Smuzhiyun 				metadata.format = SVGA3D_X8R8G8B8;
1081*4882a593Smuzhiyun 				break;
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun 			case 16:
1084*4882a593Smuzhiyun 				metadata.format = SVGA3D_R5G6B5;
1085*4882a593Smuzhiyun 				break;
1086*4882a593Smuzhiyun 
1087*4882a593Smuzhiyun 			case 8:
1088*4882a593Smuzhiyun 				metadata.format = SVGA3D_P8;
1089*4882a593Smuzhiyun 				break;
1090*4882a593Smuzhiyun 
1091*4882a593Smuzhiyun 			default:
1092*4882a593Smuzhiyun 				DRM_ERROR("Invalid format\n");
1093*4882a593Smuzhiyun 				return -EINVAL;
1094*4882a593Smuzhiyun 			}
1095*4882a593Smuzhiyun 
1096*4882a593Smuzhiyun 			metadata.mip_levels[0] = 1;
1097*4882a593Smuzhiyun 			metadata.num_sizes = 1;
1098*4882a593Smuzhiyun 			metadata.scanout = true;
1099*4882a593Smuzhiyun 		} else {
1100*4882a593Smuzhiyun 			metadata = new_vfbs->surface->metadata;
1101*4882a593Smuzhiyun 		}
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun 		metadata.base_size.width = hdisplay;
1104*4882a593Smuzhiyun 		metadata.base_size.height = vdisplay;
1105*4882a593Smuzhiyun 		metadata.base_size.depth = 1;
1106*4882a593Smuzhiyun 
1107*4882a593Smuzhiyun 		if (vps->surf) {
1108*4882a593Smuzhiyun 			struct drm_vmw_size cur_base_size =
1109*4882a593Smuzhiyun 				vps->surf->metadata.base_size;
1110*4882a593Smuzhiyun 
1111*4882a593Smuzhiyun 			if (cur_base_size.width != metadata.base_size.width ||
1112*4882a593Smuzhiyun 			    cur_base_size.height != metadata.base_size.height ||
1113*4882a593Smuzhiyun 			    vps->surf->metadata.format != metadata.format) {
1114*4882a593Smuzhiyun 				WARN_ON(vps->pinned != 0);
1115*4882a593Smuzhiyun 				vmw_surface_unreference(&vps->surf);
1116*4882a593Smuzhiyun 			}
1117*4882a593Smuzhiyun 
1118*4882a593Smuzhiyun 		}
1119*4882a593Smuzhiyun 
1120*4882a593Smuzhiyun 		if (!vps->surf) {
1121*4882a593Smuzhiyun 			ret = vmw_gb_surface_define(dev_priv, 0, &metadata,
1122*4882a593Smuzhiyun 						    &vps->surf);
1123*4882a593Smuzhiyun 			if (ret != 0) {
1124*4882a593Smuzhiyun 				DRM_ERROR("Couldn't allocate STDU surface.\n");
1125*4882a593Smuzhiyun 				return ret;
1126*4882a593Smuzhiyun 			}
1127*4882a593Smuzhiyun 		}
1128*4882a593Smuzhiyun 	} else {
1129*4882a593Smuzhiyun 		/*
1130*4882a593Smuzhiyun 		 * prepare_fb and clean_fb should only take care of pinning
1131*4882a593Smuzhiyun 		 * and unpinning.  References are tracked by state objects.
1132*4882a593Smuzhiyun 		 * The only time we add a reference in prepare_fb is if the
1133*4882a593Smuzhiyun 		 * state object doesn't have a reference to begin with
1134*4882a593Smuzhiyun 		 */
1135*4882a593Smuzhiyun 		if (vps->surf) {
1136*4882a593Smuzhiyun 			WARN_ON(vps->pinned != 0);
1137*4882a593Smuzhiyun 			vmw_surface_unreference(&vps->surf);
1138*4882a593Smuzhiyun 		}
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun 		vps->surf = vmw_surface_reference(new_vfbs->surface);
1141*4882a593Smuzhiyun 	}
1142*4882a593Smuzhiyun 
1143*4882a593Smuzhiyun 	if (vps->surf) {
1144*4882a593Smuzhiyun 
1145*4882a593Smuzhiyun 		/* Pin new surface before flipping */
1146*4882a593Smuzhiyun 		ret = vmw_resource_pin(&vps->surf->res, false);
1147*4882a593Smuzhiyun 		if (ret)
1148*4882a593Smuzhiyun 			goto out_srf_unref;
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun 		vps->pinned++;
1151*4882a593Smuzhiyun 	}
1152*4882a593Smuzhiyun 
1153*4882a593Smuzhiyun 	vps->content_fb_type = new_content_type;
1154*4882a593Smuzhiyun 
1155*4882a593Smuzhiyun 	/*
1156*4882a593Smuzhiyun 	 * This should only happen if the buffer object is too large to create a
1157*4882a593Smuzhiyun 	 * proxy surface for.
1158*4882a593Smuzhiyun 	 * If we are a 2D VM with a buffer object then we have to use CPU blit
1159*4882a593Smuzhiyun 	 * so cache these mappings
1160*4882a593Smuzhiyun 	 */
1161*4882a593Smuzhiyun 	if (vps->content_fb_type == SEPARATE_BO &&
1162*4882a593Smuzhiyun 	    !(dev_priv->capabilities & SVGA_CAP_3D))
1163*4882a593Smuzhiyun 		vps->cpp = new_fb->pitches[0] / new_fb->width;
1164*4882a593Smuzhiyun 
1165*4882a593Smuzhiyun 	return 0;
1166*4882a593Smuzhiyun 
1167*4882a593Smuzhiyun out_srf_unref:
1168*4882a593Smuzhiyun 	vmw_surface_unreference(&vps->surf);
1169*4882a593Smuzhiyun 	return ret;
1170*4882a593Smuzhiyun }
1171*4882a593Smuzhiyun 
vmw_stdu_bo_fifo_size(struct vmw_du_update_plane * update,uint32_t num_hits)1172*4882a593Smuzhiyun static uint32_t vmw_stdu_bo_fifo_size(struct vmw_du_update_plane *update,
1173*4882a593Smuzhiyun 				      uint32_t num_hits)
1174*4882a593Smuzhiyun {
1175*4882a593Smuzhiyun 	return sizeof(struct vmw_stdu_dma) + sizeof(SVGA3dCopyBox) * num_hits +
1176*4882a593Smuzhiyun 		sizeof(SVGA3dCmdSurfaceDMASuffix) +
1177*4882a593Smuzhiyun 		sizeof(struct vmw_stdu_update);
1178*4882a593Smuzhiyun }
1179*4882a593Smuzhiyun 
vmw_stdu_bo_fifo_size_cpu(struct vmw_du_update_plane * update,uint32_t num_hits)1180*4882a593Smuzhiyun static uint32_t vmw_stdu_bo_fifo_size_cpu(struct vmw_du_update_plane *update,
1181*4882a593Smuzhiyun 					  uint32_t num_hits)
1182*4882a593Smuzhiyun {
1183*4882a593Smuzhiyun 	return sizeof(struct vmw_stdu_update_gb_image) +
1184*4882a593Smuzhiyun 		sizeof(struct vmw_stdu_update);
1185*4882a593Smuzhiyun }
1186*4882a593Smuzhiyun 
vmw_stdu_bo_populate_dma(struct vmw_du_update_plane * update,void * cmd,uint32_t num_hits)1187*4882a593Smuzhiyun static uint32_t vmw_stdu_bo_populate_dma(struct vmw_du_update_plane  *update,
1188*4882a593Smuzhiyun 					 void *cmd, uint32_t num_hits)
1189*4882a593Smuzhiyun {
1190*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu;
1191*4882a593Smuzhiyun 	struct vmw_framebuffer_bo *vfbbo;
1192*4882a593Smuzhiyun 	struct vmw_stdu_dma *cmd_dma = cmd;
1193*4882a593Smuzhiyun 
1194*4882a593Smuzhiyun 	stdu = container_of(update->du, typeof(*stdu), base);
1195*4882a593Smuzhiyun 	vfbbo = container_of(update->vfb, typeof(*vfbbo), base);
1196*4882a593Smuzhiyun 
1197*4882a593Smuzhiyun 	cmd_dma->header.id = SVGA_3D_CMD_SURFACE_DMA;
1198*4882a593Smuzhiyun 	cmd_dma->header.size = sizeof(cmd_dma->body) +
1199*4882a593Smuzhiyun 		sizeof(struct SVGA3dCopyBox) * num_hits +
1200*4882a593Smuzhiyun 		sizeof(SVGA3dCmdSurfaceDMASuffix);
1201*4882a593Smuzhiyun 	vmw_bo_get_guest_ptr(&vfbbo->buffer->base, &cmd_dma->body.guest.ptr);
1202*4882a593Smuzhiyun 	cmd_dma->body.guest.pitch = update->vfb->base.pitches[0];
1203*4882a593Smuzhiyun 	cmd_dma->body.host.sid = stdu->display_srf->res.id;
1204*4882a593Smuzhiyun 	cmd_dma->body.host.face = 0;
1205*4882a593Smuzhiyun 	cmd_dma->body.host.mipmap = 0;
1206*4882a593Smuzhiyun 	cmd_dma->body.transfer = SVGA3D_WRITE_HOST_VRAM;
1207*4882a593Smuzhiyun 
1208*4882a593Smuzhiyun 	return sizeof(*cmd_dma);
1209*4882a593Smuzhiyun }
1210*4882a593Smuzhiyun 
vmw_stdu_bo_populate_clip(struct vmw_du_update_plane * update,void * cmd,struct drm_rect * clip,uint32_t fb_x,uint32_t fb_y)1211*4882a593Smuzhiyun static uint32_t vmw_stdu_bo_populate_clip(struct vmw_du_update_plane  *update,
1212*4882a593Smuzhiyun 					  void *cmd, struct drm_rect *clip,
1213*4882a593Smuzhiyun 					  uint32_t fb_x, uint32_t fb_y)
1214*4882a593Smuzhiyun {
1215*4882a593Smuzhiyun 	struct SVGA3dCopyBox *box = cmd;
1216*4882a593Smuzhiyun 
1217*4882a593Smuzhiyun 	box->srcx = fb_x;
1218*4882a593Smuzhiyun 	box->srcy = fb_y;
1219*4882a593Smuzhiyun 	box->srcz = 0;
1220*4882a593Smuzhiyun 	box->x = clip->x1;
1221*4882a593Smuzhiyun 	box->y = clip->y1;
1222*4882a593Smuzhiyun 	box->z = 0;
1223*4882a593Smuzhiyun 	box->w = drm_rect_width(clip);
1224*4882a593Smuzhiyun 	box->h = drm_rect_height(clip);
1225*4882a593Smuzhiyun 	box->d = 1;
1226*4882a593Smuzhiyun 
1227*4882a593Smuzhiyun 	return sizeof(*box);
1228*4882a593Smuzhiyun }
1229*4882a593Smuzhiyun 
vmw_stdu_bo_populate_update(struct vmw_du_update_plane * update,void * cmd,struct drm_rect * bb)1230*4882a593Smuzhiyun static uint32_t vmw_stdu_bo_populate_update(struct vmw_du_update_plane  *update,
1231*4882a593Smuzhiyun 					    void *cmd, struct drm_rect *bb)
1232*4882a593Smuzhiyun {
1233*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu;
1234*4882a593Smuzhiyun 	struct vmw_framebuffer_bo *vfbbo;
1235*4882a593Smuzhiyun 	SVGA3dCmdSurfaceDMASuffix *suffix = cmd;
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	stdu = container_of(update->du, typeof(*stdu), base);
1238*4882a593Smuzhiyun 	vfbbo = container_of(update->vfb, typeof(*vfbbo), base);
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun 	suffix->suffixSize = sizeof(*suffix);
1241*4882a593Smuzhiyun 	suffix->maximumOffset = vfbbo->buffer->base.num_pages * PAGE_SIZE;
1242*4882a593Smuzhiyun 
1243*4882a593Smuzhiyun 	vmw_stdu_populate_update(&suffix[1], stdu->base.unit, bb->x1, bb->x2,
1244*4882a593Smuzhiyun 				 bb->y1, bb->y2);
1245*4882a593Smuzhiyun 
1246*4882a593Smuzhiyun 	return sizeof(*suffix) + sizeof(struct vmw_stdu_update);
1247*4882a593Smuzhiyun }
1248*4882a593Smuzhiyun 
vmw_stdu_bo_pre_clip_cpu(struct vmw_du_update_plane * update,void * cmd,uint32_t num_hits)1249*4882a593Smuzhiyun static uint32_t vmw_stdu_bo_pre_clip_cpu(struct vmw_du_update_plane  *update,
1250*4882a593Smuzhiyun 					 void *cmd, uint32_t num_hits)
1251*4882a593Smuzhiyun {
1252*4882a593Smuzhiyun 	struct vmw_du_update_plane_buffer *bo_update =
1253*4882a593Smuzhiyun 		container_of(update, typeof(*bo_update), base);
1254*4882a593Smuzhiyun 
1255*4882a593Smuzhiyun 	bo_update->fb_left = INT_MAX;
1256*4882a593Smuzhiyun 	bo_update->fb_top = INT_MAX;
1257*4882a593Smuzhiyun 
1258*4882a593Smuzhiyun 	return 0;
1259*4882a593Smuzhiyun }
1260*4882a593Smuzhiyun 
vmw_stdu_bo_clip_cpu(struct vmw_du_update_plane * update,void * cmd,struct drm_rect * clip,uint32_t fb_x,uint32_t fb_y)1261*4882a593Smuzhiyun static uint32_t vmw_stdu_bo_clip_cpu(struct vmw_du_update_plane  *update,
1262*4882a593Smuzhiyun 				     void *cmd, struct drm_rect *clip,
1263*4882a593Smuzhiyun 				     uint32_t fb_x, uint32_t fb_y)
1264*4882a593Smuzhiyun {
1265*4882a593Smuzhiyun 	struct vmw_du_update_plane_buffer *bo_update =
1266*4882a593Smuzhiyun 		container_of(update, typeof(*bo_update), base);
1267*4882a593Smuzhiyun 
1268*4882a593Smuzhiyun 	bo_update->fb_left = min_t(int, bo_update->fb_left, fb_x);
1269*4882a593Smuzhiyun 	bo_update->fb_top = min_t(int, bo_update->fb_top, fb_y);
1270*4882a593Smuzhiyun 
1271*4882a593Smuzhiyun 	return 0;
1272*4882a593Smuzhiyun }
1273*4882a593Smuzhiyun 
1274*4882a593Smuzhiyun static uint32_t
vmw_stdu_bo_populate_update_cpu(struct vmw_du_update_plane * update,void * cmd,struct drm_rect * bb)1275*4882a593Smuzhiyun vmw_stdu_bo_populate_update_cpu(struct vmw_du_update_plane  *update, void *cmd,
1276*4882a593Smuzhiyun 				struct drm_rect *bb)
1277*4882a593Smuzhiyun {
1278*4882a593Smuzhiyun 	struct vmw_du_update_plane_buffer *bo_update;
1279*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu;
1280*4882a593Smuzhiyun 	struct vmw_framebuffer_bo *vfbbo;
1281*4882a593Smuzhiyun 	struct vmw_diff_cpy diff = VMW_CPU_BLIT_DIFF_INITIALIZER(0);
1282*4882a593Smuzhiyun 	struct vmw_stdu_update_gb_image *cmd_img = cmd;
1283*4882a593Smuzhiyun 	struct vmw_stdu_update *cmd_update;
1284*4882a593Smuzhiyun 	struct ttm_buffer_object *src_bo, *dst_bo;
1285*4882a593Smuzhiyun 	u32 src_offset, dst_offset;
1286*4882a593Smuzhiyun 	s32 src_pitch, dst_pitch;
1287*4882a593Smuzhiyun 	s32 width, height;
1288*4882a593Smuzhiyun 
1289*4882a593Smuzhiyun 	bo_update = container_of(update, typeof(*bo_update), base);
1290*4882a593Smuzhiyun 	stdu = container_of(update->du, typeof(*stdu), base);
1291*4882a593Smuzhiyun 	vfbbo = container_of(update->vfb, typeof(*vfbbo), base);
1292*4882a593Smuzhiyun 
1293*4882a593Smuzhiyun 	width = bb->x2 - bb->x1;
1294*4882a593Smuzhiyun 	height = bb->y2 - bb->y1;
1295*4882a593Smuzhiyun 
1296*4882a593Smuzhiyun 	diff.cpp = stdu->cpp;
1297*4882a593Smuzhiyun 
1298*4882a593Smuzhiyun 	dst_bo = &stdu->display_srf->res.backup->base;
1299*4882a593Smuzhiyun 	dst_pitch = stdu->display_srf->metadata.base_size.width * stdu->cpp;
1300*4882a593Smuzhiyun 	dst_offset = bb->y1 * dst_pitch + bb->x1 * stdu->cpp;
1301*4882a593Smuzhiyun 
1302*4882a593Smuzhiyun 	src_bo = &vfbbo->buffer->base;
1303*4882a593Smuzhiyun 	src_pitch = update->vfb->base.pitches[0];
1304*4882a593Smuzhiyun 	src_offset = bo_update->fb_top * src_pitch + bo_update->fb_left *
1305*4882a593Smuzhiyun 		stdu->cpp;
1306*4882a593Smuzhiyun 
1307*4882a593Smuzhiyun 	(void) vmw_bo_cpu_blit(dst_bo, dst_offset, dst_pitch, src_bo,
1308*4882a593Smuzhiyun 			       src_offset, src_pitch, width * stdu->cpp, height,
1309*4882a593Smuzhiyun 			       &diff);
1310*4882a593Smuzhiyun 
1311*4882a593Smuzhiyun 	if (drm_rect_visible(&diff.rect)) {
1312*4882a593Smuzhiyun 		SVGA3dBox *box = &cmd_img->body.box;
1313*4882a593Smuzhiyun 
1314*4882a593Smuzhiyun 		cmd_img->header.id = SVGA_3D_CMD_UPDATE_GB_IMAGE;
1315*4882a593Smuzhiyun 		cmd_img->header.size = sizeof(cmd_img->body);
1316*4882a593Smuzhiyun 		cmd_img->body.image.sid = stdu->display_srf->res.id;
1317*4882a593Smuzhiyun 		cmd_img->body.image.face = 0;
1318*4882a593Smuzhiyun 		cmd_img->body.image.mipmap = 0;
1319*4882a593Smuzhiyun 
1320*4882a593Smuzhiyun 		box->x = diff.rect.x1;
1321*4882a593Smuzhiyun 		box->y = diff.rect.y1;
1322*4882a593Smuzhiyun 		box->z = 0;
1323*4882a593Smuzhiyun 		box->w = drm_rect_width(&diff.rect);
1324*4882a593Smuzhiyun 		box->h = drm_rect_height(&diff.rect);
1325*4882a593Smuzhiyun 		box->d = 1;
1326*4882a593Smuzhiyun 
1327*4882a593Smuzhiyun 		cmd_update = (struct vmw_stdu_update *)&cmd_img[1];
1328*4882a593Smuzhiyun 		vmw_stdu_populate_update(cmd_update, stdu->base.unit,
1329*4882a593Smuzhiyun 					 diff.rect.x1, diff.rect.x2,
1330*4882a593Smuzhiyun 					 diff.rect.y1, diff.rect.y2);
1331*4882a593Smuzhiyun 
1332*4882a593Smuzhiyun 		return sizeof(*cmd_img) + sizeof(*cmd_update);
1333*4882a593Smuzhiyun 	}
1334*4882a593Smuzhiyun 
1335*4882a593Smuzhiyun 	return 0;
1336*4882a593Smuzhiyun }
1337*4882a593Smuzhiyun 
1338*4882a593Smuzhiyun /**
1339*4882a593Smuzhiyun  * vmw_stdu_plane_update_bo - Update display unit for bo backed fb.
1340*4882a593Smuzhiyun  * @dev_priv: device private.
1341*4882a593Smuzhiyun  * @plane: plane state.
1342*4882a593Smuzhiyun  * @old_state: old plane state.
1343*4882a593Smuzhiyun  * @vfb: framebuffer which is blitted to display unit.
1344*4882a593Smuzhiyun  * @out_fence: If non-NULL, will return a ref-counted pointer to vmw_fence_obj.
1345*4882a593Smuzhiyun  *             The returned fence pointer may be NULL in which case the device
1346*4882a593Smuzhiyun  *             has already synchronized.
1347*4882a593Smuzhiyun  *
1348*4882a593Smuzhiyun  * Return: 0 on success or a negative error code on failure.
1349*4882a593Smuzhiyun  */
vmw_stdu_plane_update_bo(struct vmw_private * dev_priv,struct drm_plane * plane,struct drm_plane_state * old_state,struct vmw_framebuffer * vfb,struct vmw_fence_obj ** out_fence)1350*4882a593Smuzhiyun static int vmw_stdu_plane_update_bo(struct vmw_private *dev_priv,
1351*4882a593Smuzhiyun 				    struct drm_plane *plane,
1352*4882a593Smuzhiyun 				    struct drm_plane_state *old_state,
1353*4882a593Smuzhiyun 				    struct vmw_framebuffer *vfb,
1354*4882a593Smuzhiyun 				    struct vmw_fence_obj **out_fence)
1355*4882a593Smuzhiyun {
1356*4882a593Smuzhiyun 	struct vmw_du_update_plane_buffer bo_update;
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun 	memset(&bo_update, 0, sizeof(struct vmw_du_update_plane_buffer));
1359*4882a593Smuzhiyun 	bo_update.base.plane = plane;
1360*4882a593Smuzhiyun 	bo_update.base.old_state = old_state;
1361*4882a593Smuzhiyun 	bo_update.base.dev_priv = dev_priv;
1362*4882a593Smuzhiyun 	bo_update.base.du = vmw_crtc_to_du(plane->state->crtc);
1363*4882a593Smuzhiyun 	bo_update.base.vfb = vfb;
1364*4882a593Smuzhiyun 	bo_update.base.out_fence = out_fence;
1365*4882a593Smuzhiyun 	bo_update.base.mutex = NULL;
1366*4882a593Smuzhiyun 	bo_update.base.cpu_blit = !(dev_priv->capabilities & SVGA_CAP_3D);
1367*4882a593Smuzhiyun 	bo_update.base.intr = false;
1368*4882a593Smuzhiyun 
1369*4882a593Smuzhiyun 	/*
1370*4882a593Smuzhiyun 	 * VM without 3D support don't have surface DMA command and framebuffer
1371*4882a593Smuzhiyun 	 * should be moved out of VRAM.
1372*4882a593Smuzhiyun 	 */
1373*4882a593Smuzhiyun 	if (bo_update.base.cpu_blit) {
1374*4882a593Smuzhiyun 		bo_update.base.calc_fifo_size = vmw_stdu_bo_fifo_size_cpu;
1375*4882a593Smuzhiyun 		bo_update.base.pre_clip = vmw_stdu_bo_pre_clip_cpu;
1376*4882a593Smuzhiyun 		bo_update.base.clip = vmw_stdu_bo_clip_cpu;
1377*4882a593Smuzhiyun 		bo_update.base.post_clip = vmw_stdu_bo_populate_update_cpu;
1378*4882a593Smuzhiyun 	} else {
1379*4882a593Smuzhiyun 		bo_update.base.calc_fifo_size = vmw_stdu_bo_fifo_size;
1380*4882a593Smuzhiyun 		bo_update.base.pre_clip = vmw_stdu_bo_populate_dma;
1381*4882a593Smuzhiyun 		bo_update.base.clip = vmw_stdu_bo_populate_clip;
1382*4882a593Smuzhiyun 		bo_update.base.post_clip = vmw_stdu_bo_populate_update;
1383*4882a593Smuzhiyun 	}
1384*4882a593Smuzhiyun 
1385*4882a593Smuzhiyun 	return vmw_du_helper_plane_update(&bo_update.base);
1386*4882a593Smuzhiyun }
1387*4882a593Smuzhiyun 
1388*4882a593Smuzhiyun static uint32_t
vmw_stdu_surface_fifo_size_same_display(struct vmw_du_update_plane * update,uint32_t num_hits)1389*4882a593Smuzhiyun vmw_stdu_surface_fifo_size_same_display(struct vmw_du_update_plane *update,
1390*4882a593Smuzhiyun 					uint32_t num_hits)
1391*4882a593Smuzhiyun {
1392*4882a593Smuzhiyun 	struct vmw_framebuffer_surface *vfbs;
1393*4882a593Smuzhiyun 	uint32_t size = 0;
1394*4882a593Smuzhiyun 
1395*4882a593Smuzhiyun 	vfbs = container_of(update->vfb, typeof(*vfbs), base);
1396*4882a593Smuzhiyun 
1397*4882a593Smuzhiyun 	if (vfbs->is_bo_proxy)
1398*4882a593Smuzhiyun 		size += sizeof(struct vmw_stdu_update_gb_image) * num_hits;
1399*4882a593Smuzhiyun 
1400*4882a593Smuzhiyun 	size += sizeof(struct vmw_stdu_update);
1401*4882a593Smuzhiyun 
1402*4882a593Smuzhiyun 	return size;
1403*4882a593Smuzhiyun }
1404*4882a593Smuzhiyun 
vmw_stdu_surface_fifo_size(struct vmw_du_update_plane * update,uint32_t num_hits)1405*4882a593Smuzhiyun static uint32_t vmw_stdu_surface_fifo_size(struct vmw_du_update_plane *update,
1406*4882a593Smuzhiyun 					   uint32_t num_hits)
1407*4882a593Smuzhiyun {
1408*4882a593Smuzhiyun 	struct vmw_framebuffer_surface *vfbs;
1409*4882a593Smuzhiyun 	uint32_t size = 0;
1410*4882a593Smuzhiyun 
1411*4882a593Smuzhiyun 	vfbs = container_of(update->vfb, typeof(*vfbs), base);
1412*4882a593Smuzhiyun 
1413*4882a593Smuzhiyun 	if (vfbs->is_bo_proxy)
1414*4882a593Smuzhiyun 		size += sizeof(struct vmw_stdu_update_gb_image) * num_hits;
1415*4882a593Smuzhiyun 
1416*4882a593Smuzhiyun 	size += sizeof(struct vmw_stdu_surface_copy) + sizeof(SVGA3dCopyBox) *
1417*4882a593Smuzhiyun 		num_hits + sizeof(struct vmw_stdu_update);
1418*4882a593Smuzhiyun 
1419*4882a593Smuzhiyun 	return size;
1420*4882a593Smuzhiyun }
1421*4882a593Smuzhiyun 
1422*4882a593Smuzhiyun static uint32_t
vmw_stdu_surface_update_proxy(struct vmw_du_update_plane * update,void * cmd)1423*4882a593Smuzhiyun vmw_stdu_surface_update_proxy(struct vmw_du_update_plane *update, void *cmd)
1424*4882a593Smuzhiyun {
1425*4882a593Smuzhiyun 	struct vmw_framebuffer_surface *vfbs;
1426*4882a593Smuzhiyun 	struct drm_plane_state *state = update->plane->state;
1427*4882a593Smuzhiyun 	struct drm_plane_state *old_state = update->old_state;
1428*4882a593Smuzhiyun 	struct vmw_stdu_update_gb_image *cmd_update = cmd;
1429*4882a593Smuzhiyun 	struct drm_atomic_helper_damage_iter iter;
1430*4882a593Smuzhiyun 	struct drm_rect clip;
1431*4882a593Smuzhiyun 	uint32_t copy_size = 0;
1432*4882a593Smuzhiyun 
1433*4882a593Smuzhiyun 	vfbs = container_of(update->vfb, typeof(*vfbs), base);
1434*4882a593Smuzhiyun 
1435*4882a593Smuzhiyun 	/*
1436*4882a593Smuzhiyun 	 * proxy surface is special where a buffer object type fb is wrapped
1437*4882a593Smuzhiyun 	 * in a surface and need an update gb image command to sync with device.
1438*4882a593Smuzhiyun 	 */
1439*4882a593Smuzhiyun 	drm_atomic_helper_damage_iter_init(&iter, old_state, state);
1440*4882a593Smuzhiyun 	drm_atomic_for_each_plane_damage(&iter, &clip) {
1441*4882a593Smuzhiyun 		SVGA3dBox *box = &cmd_update->body.box;
1442*4882a593Smuzhiyun 
1443*4882a593Smuzhiyun 		cmd_update->header.id = SVGA_3D_CMD_UPDATE_GB_IMAGE;
1444*4882a593Smuzhiyun 		cmd_update->header.size = sizeof(cmd_update->body);
1445*4882a593Smuzhiyun 		cmd_update->body.image.sid = vfbs->surface->res.id;
1446*4882a593Smuzhiyun 		cmd_update->body.image.face = 0;
1447*4882a593Smuzhiyun 		cmd_update->body.image.mipmap = 0;
1448*4882a593Smuzhiyun 
1449*4882a593Smuzhiyun 		box->x = clip.x1;
1450*4882a593Smuzhiyun 		box->y = clip.y1;
1451*4882a593Smuzhiyun 		box->z = 0;
1452*4882a593Smuzhiyun 		box->w = drm_rect_width(&clip);
1453*4882a593Smuzhiyun 		box->h = drm_rect_height(&clip);
1454*4882a593Smuzhiyun 		box->d = 1;
1455*4882a593Smuzhiyun 
1456*4882a593Smuzhiyun 		copy_size += sizeof(*cmd_update);
1457*4882a593Smuzhiyun 		cmd_update++;
1458*4882a593Smuzhiyun 	}
1459*4882a593Smuzhiyun 
1460*4882a593Smuzhiyun 	return copy_size;
1461*4882a593Smuzhiyun }
1462*4882a593Smuzhiyun 
1463*4882a593Smuzhiyun static uint32_t
vmw_stdu_surface_populate_copy(struct vmw_du_update_plane * update,void * cmd,uint32_t num_hits)1464*4882a593Smuzhiyun vmw_stdu_surface_populate_copy(struct vmw_du_update_plane  *update, void *cmd,
1465*4882a593Smuzhiyun 			       uint32_t num_hits)
1466*4882a593Smuzhiyun {
1467*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu;
1468*4882a593Smuzhiyun 	struct vmw_framebuffer_surface *vfbs;
1469*4882a593Smuzhiyun 	struct vmw_stdu_surface_copy *cmd_copy = cmd;
1470*4882a593Smuzhiyun 
1471*4882a593Smuzhiyun 	stdu = container_of(update->du, typeof(*stdu), base);
1472*4882a593Smuzhiyun 	vfbs = container_of(update->vfb, typeof(*vfbs), base);
1473*4882a593Smuzhiyun 
1474*4882a593Smuzhiyun 	cmd_copy->header.id = SVGA_3D_CMD_SURFACE_COPY;
1475*4882a593Smuzhiyun 	cmd_copy->header.size = sizeof(cmd_copy->body) + sizeof(SVGA3dCopyBox) *
1476*4882a593Smuzhiyun 		num_hits;
1477*4882a593Smuzhiyun 	cmd_copy->body.src.sid = vfbs->surface->res.id;
1478*4882a593Smuzhiyun 	cmd_copy->body.dest.sid = stdu->display_srf->res.id;
1479*4882a593Smuzhiyun 
1480*4882a593Smuzhiyun 	return sizeof(*cmd_copy);
1481*4882a593Smuzhiyun }
1482*4882a593Smuzhiyun 
1483*4882a593Smuzhiyun static uint32_t
vmw_stdu_surface_populate_clip(struct vmw_du_update_plane * update,void * cmd,struct drm_rect * clip,uint32_t fb_x,uint32_t fb_y)1484*4882a593Smuzhiyun vmw_stdu_surface_populate_clip(struct vmw_du_update_plane  *update, void *cmd,
1485*4882a593Smuzhiyun 			       struct drm_rect *clip, uint32_t fb_x,
1486*4882a593Smuzhiyun 			       uint32_t fb_y)
1487*4882a593Smuzhiyun {
1488*4882a593Smuzhiyun 	struct SVGA3dCopyBox *box = cmd;
1489*4882a593Smuzhiyun 
1490*4882a593Smuzhiyun 	box->srcx = fb_x;
1491*4882a593Smuzhiyun 	box->srcy = fb_y;
1492*4882a593Smuzhiyun 	box->srcz = 0;
1493*4882a593Smuzhiyun 	box->x = clip->x1;
1494*4882a593Smuzhiyun 	box->y = clip->y1;
1495*4882a593Smuzhiyun 	box->z = 0;
1496*4882a593Smuzhiyun 	box->w = drm_rect_width(clip);
1497*4882a593Smuzhiyun 	box->h = drm_rect_height(clip);
1498*4882a593Smuzhiyun 	box->d = 1;
1499*4882a593Smuzhiyun 
1500*4882a593Smuzhiyun 	return sizeof(*box);
1501*4882a593Smuzhiyun }
1502*4882a593Smuzhiyun 
1503*4882a593Smuzhiyun static uint32_t
vmw_stdu_surface_populate_update(struct vmw_du_update_plane * update,void * cmd,struct drm_rect * bb)1504*4882a593Smuzhiyun vmw_stdu_surface_populate_update(struct vmw_du_update_plane  *update, void *cmd,
1505*4882a593Smuzhiyun 				 struct drm_rect *bb)
1506*4882a593Smuzhiyun {
1507*4882a593Smuzhiyun 	vmw_stdu_populate_update(cmd, update->du->unit, bb->x1, bb->x2, bb->y1,
1508*4882a593Smuzhiyun 				 bb->y2);
1509*4882a593Smuzhiyun 
1510*4882a593Smuzhiyun 	return sizeof(struct vmw_stdu_update);
1511*4882a593Smuzhiyun }
1512*4882a593Smuzhiyun 
1513*4882a593Smuzhiyun /**
1514*4882a593Smuzhiyun  * vmw_stdu_plane_update_surface - Update display unit for surface backed fb
1515*4882a593Smuzhiyun  * @dev_priv: Device private
1516*4882a593Smuzhiyun  * @plane: Plane state
1517*4882a593Smuzhiyun  * @old_state: Old plane state
1518*4882a593Smuzhiyun  * @vfb: Framebuffer which is blitted to display unit
1519*4882a593Smuzhiyun  * @out_fence: If non-NULL, will return a ref-counted pointer to vmw_fence_obj.
1520*4882a593Smuzhiyun  *             The returned fence pointer may be NULL in which case the device
1521*4882a593Smuzhiyun  *             has already synchronized.
1522*4882a593Smuzhiyun  *
1523*4882a593Smuzhiyun  * Return: 0 on success or a negative error code on failure.
1524*4882a593Smuzhiyun  */
vmw_stdu_plane_update_surface(struct vmw_private * dev_priv,struct drm_plane * plane,struct drm_plane_state * old_state,struct vmw_framebuffer * vfb,struct vmw_fence_obj ** out_fence)1525*4882a593Smuzhiyun static int vmw_stdu_plane_update_surface(struct vmw_private *dev_priv,
1526*4882a593Smuzhiyun 					 struct drm_plane *plane,
1527*4882a593Smuzhiyun 					 struct drm_plane_state *old_state,
1528*4882a593Smuzhiyun 					 struct vmw_framebuffer *vfb,
1529*4882a593Smuzhiyun 					 struct vmw_fence_obj **out_fence)
1530*4882a593Smuzhiyun {
1531*4882a593Smuzhiyun 	struct vmw_du_update_plane srf_update;
1532*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu;
1533*4882a593Smuzhiyun 	struct vmw_framebuffer_surface *vfbs;
1534*4882a593Smuzhiyun 
1535*4882a593Smuzhiyun 	stdu = vmw_crtc_to_stdu(plane->state->crtc);
1536*4882a593Smuzhiyun 	vfbs = container_of(vfb, typeof(*vfbs), base);
1537*4882a593Smuzhiyun 
1538*4882a593Smuzhiyun 	memset(&srf_update, 0, sizeof(struct vmw_du_update_plane));
1539*4882a593Smuzhiyun 	srf_update.plane = plane;
1540*4882a593Smuzhiyun 	srf_update.old_state = old_state;
1541*4882a593Smuzhiyun 	srf_update.dev_priv = dev_priv;
1542*4882a593Smuzhiyun 	srf_update.du = vmw_crtc_to_du(plane->state->crtc);
1543*4882a593Smuzhiyun 	srf_update.vfb = vfb;
1544*4882a593Smuzhiyun 	srf_update.out_fence = out_fence;
1545*4882a593Smuzhiyun 	srf_update.mutex = &dev_priv->cmdbuf_mutex;
1546*4882a593Smuzhiyun 	srf_update.cpu_blit = false;
1547*4882a593Smuzhiyun 	srf_update.intr = true;
1548*4882a593Smuzhiyun 
1549*4882a593Smuzhiyun 	if (vfbs->is_bo_proxy)
1550*4882a593Smuzhiyun 		srf_update.post_prepare = vmw_stdu_surface_update_proxy;
1551*4882a593Smuzhiyun 
1552*4882a593Smuzhiyun 	if (vfbs->surface->res.id != stdu->display_srf->res.id) {
1553*4882a593Smuzhiyun 		srf_update.calc_fifo_size = vmw_stdu_surface_fifo_size;
1554*4882a593Smuzhiyun 		srf_update.pre_clip = vmw_stdu_surface_populate_copy;
1555*4882a593Smuzhiyun 		srf_update.clip = vmw_stdu_surface_populate_clip;
1556*4882a593Smuzhiyun 	} else {
1557*4882a593Smuzhiyun 		srf_update.calc_fifo_size =
1558*4882a593Smuzhiyun 			vmw_stdu_surface_fifo_size_same_display;
1559*4882a593Smuzhiyun 	}
1560*4882a593Smuzhiyun 
1561*4882a593Smuzhiyun 	srf_update.post_clip = vmw_stdu_surface_populate_update;
1562*4882a593Smuzhiyun 
1563*4882a593Smuzhiyun 	return vmw_du_helper_plane_update(&srf_update);
1564*4882a593Smuzhiyun }
1565*4882a593Smuzhiyun 
1566*4882a593Smuzhiyun /**
1567*4882a593Smuzhiyun  * vmw_stdu_primary_plane_atomic_update - formally switches STDU to new plane
1568*4882a593Smuzhiyun  * @plane: display plane
1569*4882a593Smuzhiyun  * @old_state: Only used to get crtc info
1570*4882a593Smuzhiyun  *
1571*4882a593Smuzhiyun  * Formally update stdu->display_srf to the new plane, and bind the new
1572*4882a593Smuzhiyun  * plane STDU.  This function is called during the commit phase when
1573*4882a593Smuzhiyun  * all the preparation have been done and all the configurations have
1574*4882a593Smuzhiyun  * been checked.
1575*4882a593Smuzhiyun  */
1576*4882a593Smuzhiyun static void
vmw_stdu_primary_plane_atomic_update(struct drm_plane * plane,struct drm_plane_state * old_state)1577*4882a593Smuzhiyun vmw_stdu_primary_plane_atomic_update(struct drm_plane *plane,
1578*4882a593Smuzhiyun 				     struct drm_plane_state *old_state)
1579*4882a593Smuzhiyun {
1580*4882a593Smuzhiyun 	struct vmw_plane_state *vps = vmw_plane_state_to_vps(plane->state);
1581*4882a593Smuzhiyun 	struct drm_crtc *crtc = plane->state->crtc;
1582*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu;
1583*4882a593Smuzhiyun 	struct drm_pending_vblank_event *event;
1584*4882a593Smuzhiyun 	struct vmw_fence_obj *fence = NULL;
1585*4882a593Smuzhiyun 	struct vmw_private *dev_priv;
1586*4882a593Smuzhiyun 	int ret;
1587*4882a593Smuzhiyun 
1588*4882a593Smuzhiyun 	/* If case of device error, maintain consistent atomic state */
1589*4882a593Smuzhiyun 	if (crtc && plane->state->fb) {
1590*4882a593Smuzhiyun 		struct vmw_framebuffer *vfb =
1591*4882a593Smuzhiyun 			vmw_framebuffer_to_vfb(plane->state->fb);
1592*4882a593Smuzhiyun 		stdu = vmw_crtc_to_stdu(crtc);
1593*4882a593Smuzhiyun 		dev_priv = vmw_priv(crtc->dev);
1594*4882a593Smuzhiyun 
1595*4882a593Smuzhiyun 		stdu->display_srf = vps->surf;
1596*4882a593Smuzhiyun 		stdu->content_fb_type = vps->content_fb_type;
1597*4882a593Smuzhiyun 		stdu->cpp = vps->cpp;
1598*4882a593Smuzhiyun 
1599*4882a593Smuzhiyun 		ret = vmw_stdu_bind_st(dev_priv, stdu, &stdu->display_srf->res);
1600*4882a593Smuzhiyun 		if (ret)
1601*4882a593Smuzhiyun 			DRM_ERROR("Failed to bind surface to STDU.\n");
1602*4882a593Smuzhiyun 
1603*4882a593Smuzhiyun 		if (vfb->bo)
1604*4882a593Smuzhiyun 			ret = vmw_stdu_plane_update_bo(dev_priv, plane,
1605*4882a593Smuzhiyun 						       old_state, vfb, &fence);
1606*4882a593Smuzhiyun 		else
1607*4882a593Smuzhiyun 			ret = vmw_stdu_plane_update_surface(dev_priv, plane,
1608*4882a593Smuzhiyun 							    old_state, vfb,
1609*4882a593Smuzhiyun 							    &fence);
1610*4882a593Smuzhiyun 		if (ret)
1611*4882a593Smuzhiyun 			DRM_ERROR("Failed to update STDU.\n");
1612*4882a593Smuzhiyun 	} else {
1613*4882a593Smuzhiyun 		crtc = old_state->crtc;
1614*4882a593Smuzhiyun 		stdu = vmw_crtc_to_stdu(crtc);
1615*4882a593Smuzhiyun 		dev_priv = vmw_priv(crtc->dev);
1616*4882a593Smuzhiyun 
1617*4882a593Smuzhiyun 		/* Blank STDU when fb and crtc are NULL */
1618*4882a593Smuzhiyun 		if (!stdu->defined)
1619*4882a593Smuzhiyun 			return;
1620*4882a593Smuzhiyun 
1621*4882a593Smuzhiyun 		ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
1622*4882a593Smuzhiyun 		if (ret)
1623*4882a593Smuzhiyun 			DRM_ERROR("Failed to blank STDU\n");
1624*4882a593Smuzhiyun 
1625*4882a593Smuzhiyun 		ret = vmw_stdu_update_st(dev_priv, stdu);
1626*4882a593Smuzhiyun 		if (ret)
1627*4882a593Smuzhiyun 			DRM_ERROR("Failed to update STDU.\n");
1628*4882a593Smuzhiyun 
1629*4882a593Smuzhiyun 		return;
1630*4882a593Smuzhiyun 	}
1631*4882a593Smuzhiyun 
1632*4882a593Smuzhiyun 	/* In case of error, vblank event is send in vmw_du_crtc_atomic_flush */
1633*4882a593Smuzhiyun 	event = crtc->state->event;
1634*4882a593Smuzhiyun 	if (event && fence) {
1635*4882a593Smuzhiyun 		struct drm_file *file_priv = event->base.file_priv;
1636*4882a593Smuzhiyun 
1637*4882a593Smuzhiyun 		ret = vmw_event_fence_action_queue(file_priv,
1638*4882a593Smuzhiyun 						   fence,
1639*4882a593Smuzhiyun 						   &event->base,
1640*4882a593Smuzhiyun 						   &event->event.vbl.tv_sec,
1641*4882a593Smuzhiyun 						   &event->event.vbl.tv_usec,
1642*4882a593Smuzhiyun 						   true);
1643*4882a593Smuzhiyun 		if (ret)
1644*4882a593Smuzhiyun 			DRM_ERROR("Failed to queue event on fence.\n");
1645*4882a593Smuzhiyun 		else
1646*4882a593Smuzhiyun 			crtc->state->event = NULL;
1647*4882a593Smuzhiyun 	}
1648*4882a593Smuzhiyun 
1649*4882a593Smuzhiyun 	if (fence)
1650*4882a593Smuzhiyun 		vmw_fence_obj_unreference(&fence);
1651*4882a593Smuzhiyun }
1652*4882a593Smuzhiyun 
1653*4882a593Smuzhiyun 
1654*4882a593Smuzhiyun static const struct drm_plane_funcs vmw_stdu_plane_funcs = {
1655*4882a593Smuzhiyun 	.update_plane = drm_atomic_helper_update_plane,
1656*4882a593Smuzhiyun 	.disable_plane = drm_atomic_helper_disable_plane,
1657*4882a593Smuzhiyun 	.destroy = vmw_du_primary_plane_destroy,
1658*4882a593Smuzhiyun 	.reset = vmw_du_plane_reset,
1659*4882a593Smuzhiyun 	.atomic_duplicate_state = vmw_du_plane_duplicate_state,
1660*4882a593Smuzhiyun 	.atomic_destroy_state = vmw_du_plane_destroy_state,
1661*4882a593Smuzhiyun };
1662*4882a593Smuzhiyun 
1663*4882a593Smuzhiyun static const struct drm_plane_funcs vmw_stdu_cursor_funcs = {
1664*4882a593Smuzhiyun 	.update_plane = drm_atomic_helper_update_plane,
1665*4882a593Smuzhiyun 	.disable_plane = drm_atomic_helper_disable_plane,
1666*4882a593Smuzhiyun 	.destroy = vmw_du_cursor_plane_destroy,
1667*4882a593Smuzhiyun 	.reset = vmw_du_plane_reset,
1668*4882a593Smuzhiyun 	.atomic_duplicate_state = vmw_du_plane_duplicate_state,
1669*4882a593Smuzhiyun 	.atomic_destroy_state = vmw_du_plane_destroy_state,
1670*4882a593Smuzhiyun };
1671*4882a593Smuzhiyun 
1672*4882a593Smuzhiyun 
1673*4882a593Smuzhiyun /*
1674*4882a593Smuzhiyun  * Atomic Helpers
1675*4882a593Smuzhiyun  */
1676*4882a593Smuzhiyun static const struct
1677*4882a593Smuzhiyun drm_plane_helper_funcs vmw_stdu_cursor_plane_helper_funcs = {
1678*4882a593Smuzhiyun 	.atomic_check = vmw_du_cursor_plane_atomic_check,
1679*4882a593Smuzhiyun 	.atomic_update = vmw_du_cursor_plane_atomic_update,
1680*4882a593Smuzhiyun 	.prepare_fb = vmw_du_cursor_plane_prepare_fb,
1681*4882a593Smuzhiyun 	.cleanup_fb = vmw_du_plane_cleanup_fb,
1682*4882a593Smuzhiyun };
1683*4882a593Smuzhiyun 
1684*4882a593Smuzhiyun static const struct
1685*4882a593Smuzhiyun drm_plane_helper_funcs vmw_stdu_primary_plane_helper_funcs = {
1686*4882a593Smuzhiyun 	.atomic_check = vmw_du_primary_plane_atomic_check,
1687*4882a593Smuzhiyun 	.atomic_update = vmw_stdu_primary_plane_atomic_update,
1688*4882a593Smuzhiyun 	.prepare_fb = vmw_stdu_primary_plane_prepare_fb,
1689*4882a593Smuzhiyun 	.cleanup_fb = vmw_stdu_primary_plane_cleanup_fb,
1690*4882a593Smuzhiyun };
1691*4882a593Smuzhiyun 
1692*4882a593Smuzhiyun static const struct drm_crtc_helper_funcs vmw_stdu_crtc_helper_funcs = {
1693*4882a593Smuzhiyun 	.prepare = vmw_stdu_crtc_helper_prepare,
1694*4882a593Smuzhiyun 	.mode_set_nofb = vmw_stdu_crtc_mode_set_nofb,
1695*4882a593Smuzhiyun 	.atomic_check = vmw_du_crtc_atomic_check,
1696*4882a593Smuzhiyun 	.atomic_begin = vmw_du_crtc_atomic_begin,
1697*4882a593Smuzhiyun 	.atomic_flush = vmw_du_crtc_atomic_flush,
1698*4882a593Smuzhiyun 	.atomic_enable = vmw_stdu_crtc_atomic_enable,
1699*4882a593Smuzhiyun 	.atomic_disable = vmw_stdu_crtc_atomic_disable,
1700*4882a593Smuzhiyun };
1701*4882a593Smuzhiyun 
1702*4882a593Smuzhiyun 
1703*4882a593Smuzhiyun /**
1704*4882a593Smuzhiyun  * vmw_stdu_init - Sets up a Screen Target Display Unit
1705*4882a593Smuzhiyun  *
1706*4882a593Smuzhiyun  * @dev_priv: VMW DRM device
1707*4882a593Smuzhiyun  * @unit: unit number range from 0 to VMWGFX_NUM_DISPLAY_UNITS
1708*4882a593Smuzhiyun  *
1709*4882a593Smuzhiyun  * This function is called once per CRTC, and allocates one Screen Target
1710*4882a593Smuzhiyun  * display unit to represent that CRTC.  Since the SVGA device does not separate
1711*4882a593Smuzhiyun  * out encoder and connector, they are represented as part of the STDU as well.
1712*4882a593Smuzhiyun  */
vmw_stdu_init(struct vmw_private * dev_priv,unsigned unit)1713*4882a593Smuzhiyun static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit)
1714*4882a593Smuzhiyun {
1715*4882a593Smuzhiyun 	struct vmw_screen_target_display_unit *stdu;
1716*4882a593Smuzhiyun 	struct drm_device *dev = dev_priv->dev;
1717*4882a593Smuzhiyun 	struct drm_connector *connector;
1718*4882a593Smuzhiyun 	struct drm_encoder *encoder;
1719*4882a593Smuzhiyun 	struct drm_plane *primary, *cursor;
1720*4882a593Smuzhiyun 	struct drm_crtc *crtc;
1721*4882a593Smuzhiyun 	int    ret;
1722*4882a593Smuzhiyun 
1723*4882a593Smuzhiyun 
1724*4882a593Smuzhiyun 	stdu = kzalloc(sizeof(*stdu), GFP_KERNEL);
1725*4882a593Smuzhiyun 	if (!stdu)
1726*4882a593Smuzhiyun 		return -ENOMEM;
1727*4882a593Smuzhiyun 
1728*4882a593Smuzhiyun 	stdu->base.unit = unit;
1729*4882a593Smuzhiyun 	crtc = &stdu->base.crtc;
1730*4882a593Smuzhiyun 	encoder = &stdu->base.encoder;
1731*4882a593Smuzhiyun 	connector = &stdu->base.connector;
1732*4882a593Smuzhiyun 	primary = &stdu->base.primary;
1733*4882a593Smuzhiyun 	cursor = &stdu->base.cursor;
1734*4882a593Smuzhiyun 
1735*4882a593Smuzhiyun 	stdu->base.pref_active = (unit == 0);
1736*4882a593Smuzhiyun 	stdu->base.pref_width  = dev_priv->initial_width;
1737*4882a593Smuzhiyun 	stdu->base.pref_height = dev_priv->initial_height;
1738*4882a593Smuzhiyun 	stdu->base.is_implicit = false;
1739*4882a593Smuzhiyun 
1740*4882a593Smuzhiyun 	/* Initialize primary plane */
1741*4882a593Smuzhiyun 	ret = drm_universal_plane_init(dev, primary,
1742*4882a593Smuzhiyun 				       0, &vmw_stdu_plane_funcs,
1743*4882a593Smuzhiyun 				       vmw_primary_plane_formats,
1744*4882a593Smuzhiyun 				       ARRAY_SIZE(vmw_primary_plane_formats),
1745*4882a593Smuzhiyun 				       NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
1746*4882a593Smuzhiyun 	if (ret) {
1747*4882a593Smuzhiyun 		DRM_ERROR("Failed to initialize primary plane");
1748*4882a593Smuzhiyun 		goto err_free;
1749*4882a593Smuzhiyun 	}
1750*4882a593Smuzhiyun 
1751*4882a593Smuzhiyun 	drm_plane_helper_add(primary, &vmw_stdu_primary_plane_helper_funcs);
1752*4882a593Smuzhiyun 	drm_plane_enable_fb_damage_clips(primary);
1753*4882a593Smuzhiyun 
1754*4882a593Smuzhiyun 	/* Initialize cursor plane */
1755*4882a593Smuzhiyun 	ret = drm_universal_plane_init(dev, cursor,
1756*4882a593Smuzhiyun 			0, &vmw_stdu_cursor_funcs,
1757*4882a593Smuzhiyun 			vmw_cursor_plane_formats,
1758*4882a593Smuzhiyun 			ARRAY_SIZE(vmw_cursor_plane_formats),
1759*4882a593Smuzhiyun 			NULL, DRM_PLANE_TYPE_CURSOR, NULL);
1760*4882a593Smuzhiyun 	if (ret) {
1761*4882a593Smuzhiyun 		DRM_ERROR("Failed to initialize cursor plane");
1762*4882a593Smuzhiyun 		drm_plane_cleanup(&stdu->base.primary);
1763*4882a593Smuzhiyun 		goto err_free;
1764*4882a593Smuzhiyun 	}
1765*4882a593Smuzhiyun 
1766*4882a593Smuzhiyun 	drm_plane_helper_add(cursor, &vmw_stdu_cursor_plane_helper_funcs);
1767*4882a593Smuzhiyun 
1768*4882a593Smuzhiyun 	ret = drm_connector_init(dev, connector, &vmw_stdu_connector_funcs,
1769*4882a593Smuzhiyun 				 DRM_MODE_CONNECTOR_VIRTUAL);
1770*4882a593Smuzhiyun 	if (ret) {
1771*4882a593Smuzhiyun 		DRM_ERROR("Failed to initialize connector\n");
1772*4882a593Smuzhiyun 		goto err_free;
1773*4882a593Smuzhiyun 	}
1774*4882a593Smuzhiyun 
1775*4882a593Smuzhiyun 	drm_connector_helper_add(connector, &vmw_stdu_connector_helper_funcs);
1776*4882a593Smuzhiyun 	connector->status = vmw_du_connector_detect(connector, false);
1777*4882a593Smuzhiyun 
1778*4882a593Smuzhiyun 	ret = drm_encoder_init(dev, encoder, &vmw_stdu_encoder_funcs,
1779*4882a593Smuzhiyun 			       DRM_MODE_ENCODER_VIRTUAL, NULL);
1780*4882a593Smuzhiyun 	if (ret) {
1781*4882a593Smuzhiyun 		DRM_ERROR("Failed to initialize encoder\n");
1782*4882a593Smuzhiyun 		goto err_free_connector;
1783*4882a593Smuzhiyun 	}
1784*4882a593Smuzhiyun 
1785*4882a593Smuzhiyun 	(void) drm_connector_attach_encoder(connector, encoder);
1786*4882a593Smuzhiyun 	encoder->possible_crtcs = (1 << unit);
1787*4882a593Smuzhiyun 	encoder->possible_clones = 0;
1788*4882a593Smuzhiyun 
1789*4882a593Smuzhiyun 	ret = drm_connector_register(connector);
1790*4882a593Smuzhiyun 	if (ret) {
1791*4882a593Smuzhiyun 		DRM_ERROR("Failed to register connector\n");
1792*4882a593Smuzhiyun 		goto err_free_encoder;
1793*4882a593Smuzhiyun 	}
1794*4882a593Smuzhiyun 
1795*4882a593Smuzhiyun 	ret = drm_crtc_init_with_planes(dev, crtc, &stdu->base.primary,
1796*4882a593Smuzhiyun 					&stdu->base.cursor,
1797*4882a593Smuzhiyun 					&vmw_stdu_crtc_funcs, NULL);
1798*4882a593Smuzhiyun 	if (ret) {
1799*4882a593Smuzhiyun 		DRM_ERROR("Failed to initialize CRTC\n");
1800*4882a593Smuzhiyun 		goto err_free_unregister;
1801*4882a593Smuzhiyun 	}
1802*4882a593Smuzhiyun 
1803*4882a593Smuzhiyun 	drm_crtc_helper_add(crtc, &vmw_stdu_crtc_helper_funcs);
1804*4882a593Smuzhiyun 
1805*4882a593Smuzhiyun 	drm_mode_crtc_set_gamma_size(crtc, 256);
1806*4882a593Smuzhiyun 
1807*4882a593Smuzhiyun 	drm_object_attach_property(&connector->base,
1808*4882a593Smuzhiyun 				   dev_priv->hotplug_mode_update_property, 1);
1809*4882a593Smuzhiyun 	drm_object_attach_property(&connector->base,
1810*4882a593Smuzhiyun 				   dev->mode_config.suggested_x_property, 0);
1811*4882a593Smuzhiyun 	drm_object_attach_property(&connector->base,
1812*4882a593Smuzhiyun 				   dev->mode_config.suggested_y_property, 0);
1813*4882a593Smuzhiyun 	return 0;
1814*4882a593Smuzhiyun 
1815*4882a593Smuzhiyun err_free_unregister:
1816*4882a593Smuzhiyun 	drm_connector_unregister(connector);
1817*4882a593Smuzhiyun err_free_encoder:
1818*4882a593Smuzhiyun 	drm_encoder_cleanup(encoder);
1819*4882a593Smuzhiyun err_free_connector:
1820*4882a593Smuzhiyun 	drm_connector_cleanup(connector);
1821*4882a593Smuzhiyun err_free:
1822*4882a593Smuzhiyun 	kfree(stdu);
1823*4882a593Smuzhiyun 	return ret;
1824*4882a593Smuzhiyun }
1825*4882a593Smuzhiyun 
1826*4882a593Smuzhiyun 
1827*4882a593Smuzhiyun 
1828*4882a593Smuzhiyun /**
1829*4882a593Smuzhiyun  *  vmw_stdu_destroy - Cleans up a vmw_screen_target_display_unit
1830*4882a593Smuzhiyun  *
1831*4882a593Smuzhiyun  *  @stdu:  Screen Target Display Unit to be destroyed
1832*4882a593Smuzhiyun  *
1833*4882a593Smuzhiyun  *  Clean up after vmw_stdu_init
1834*4882a593Smuzhiyun  */
vmw_stdu_destroy(struct vmw_screen_target_display_unit * stdu)1835*4882a593Smuzhiyun static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu)
1836*4882a593Smuzhiyun {
1837*4882a593Smuzhiyun 	vmw_du_cleanup(&stdu->base);
1838*4882a593Smuzhiyun 	kfree(stdu);
1839*4882a593Smuzhiyun }
1840*4882a593Smuzhiyun 
1841*4882a593Smuzhiyun 
1842*4882a593Smuzhiyun 
1843*4882a593Smuzhiyun /******************************************************************************
1844*4882a593Smuzhiyun  * Screen Target Display KMS Functions
1845*4882a593Smuzhiyun  *
1846*4882a593Smuzhiyun  * These functions are called by the common KMS code in vmwgfx_kms.c
1847*4882a593Smuzhiyun  *****************************************************************************/
1848*4882a593Smuzhiyun 
1849*4882a593Smuzhiyun /**
1850*4882a593Smuzhiyun  * vmw_kms_stdu_init_display - Initializes a Screen Target based display
1851*4882a593Smuzhiyun  *
1852*4882a593Smuzhiyun  * @dev_priv: VMW DRM device
1853*4882a593Smuzhiyun  *
1854*4882a593Smuzhiyun  * This function initialize a Screen Target based display device.  It checks
1855*4882a593Smuzhiyun  * the capability bits to make sure the underlying hardware can support
1856*4882a593Smuzhiyun  * screen targets, and then creates the maximum number of CRTCs, a.k.a Display
1857*4882a593Smuzhiyun  * Units, as supported by the display hardware.
1858*4882a593Smuzhiyun  *
1859*4882a593Smuzhiyun  * RETURNS:
1860*4882a593Smuzhiyun  * 0 on success, error code otherwise
1861*4882a593Smuzhiyun  */
vmw_kms_stdu_init_display(struct vmw_private * dev_priv)1862*4882a593Smuzhiyun int vmw_kms_stdu_init_display(struct vmw_private *dev_priv)
1863*4882a593Smuzhiyun {
1864*4882a593Smuzhiyun 	struct drm_device *dev = dev_priv->dev;
1865*4882a593Smuzhiyun 	int i, ret;
1866*4882a593Smuzhiyun 
1867*4882a593Smuzhiyun 
1868*4882a593Smuzhiyun 	/* Do nothing if Screen Target support is turned off */
1869*4882a593Smuzhiyun 	if (!VMWGFX_ENABLE_SCREEN_TARGET_OTABLE || !dev_priv->has_mob)
1870*4882a593Smuzhiyun 		return -ENOSYS;
1871*4882a593Smuzhiyun 
1872*4882a593Smuzhiyun 	if (!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS))
1873*4882a593Smuzhiyun 		return -ENOSYS;
1874*4882a593Smuzhiyun 
1875*4882a593Smuzhiyun 	ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS);
1876*4882a593Smuzhiyun 	if (unlikely(ret != 0))
1877*4882a593Smuzhiyun 		return ret;
1878*4882a593Smuzhiyun 
1879*4882a593Smuzhiyun 	dev_priv->active_display_unit = vmw_du_screen_target;
1880*4882a593Smuzhiyun 
1881*4882a593Smuzhiyun 	for (i = 0; i < VMWGFX_NUM_DISPLAY_UNITS; ++i) {
1882*4882a593Smuzhiyun 		ret = vmw_stdu_init(dev_priv, i);
1883*4882a593Smuzhiyun 
1884*4882a593Smuzhiyun 		if (unlikely(ret != 0)) {
1885*4882a593Smuzhiyun 			DRM_ERROR("Failed to initialize STDU %d", i);
1886*4882a593Smuzhiyun 			return ret;
1887*4882a593Smuzhiyun 		}
1888*4882a593Smuzhiyun 	}
1889*4882a593Smuzhiyun 
1890*4882a593Smuzhiyun 	drm_mode_config_reset(dev);
1891*4882a593Smuzhiyun 
1892*4882a593Smuzhiyun 	DRM_INFO("Screen Target Display device initialized\n");
1893*4882a593Smuzhiyun 
1894*4882a593Smuzhiyun 	return 0;
1895*4882a593Smuzhiyun }
1896