1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 OR MIT
2*4882a593Smuzhiyun /**************************************************************************
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright 2011-2015 VMware, Inc., Palo Alto, CA., USA
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
7*4882a593Smuzhiyun * copy of this software and associated documentation files (the
8*4882a593Smuzhiyun * "Software"), to deal in the Software without restriction, including
9*4882a593Smuzhiyun * without limitation the rights to use, copy, modify, merge, publish,
10*4882a593Smuzhiyun * distribute, sub license, and/or sell copies of the Software, and to
11*4882a593Smuzhiyun * permit persons to whom the Software is furnished to do so, subject to
12*4882a593Smuzhiyun * the following conditions:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the
15*4882a593Smuzhiyun * next paragraph) shall be included in all copies or substantial portions
16*4882a593Smuzhiyun * of the Software.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21*4882a593Smuzhiyun * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22*4882a593Smuzhiyun * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23*4882a593Smuzhiyun * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24*4882a593Smuzhiyun * USE OR OTHER DEALINGS IN THE SOFTWARE.
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun **************************************************************************/
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <drm/drm_atomic.h>
29*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
30*4882a593Smuzhiyun #include <drm/drm_damage_helper.h>
31*4882a593Smuzhiyun #include <drm/drm_fourcc.h>
32*4882a593Smuzhiyun #include <drm/drm_plane_helper.h>
33*4882a593Smuzhiyun #include <drm/drm_vblank.h>
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #include "vmwgfx_kms.h"
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define vmw_crtc_to_sou(x) \
38*4882a593Smuzhiyun container_of(x, struct vmw_screen_object_unit, base.crtc)
39*4882a593Smuzhiyun #define vmw_encoder_to_sou(x) \
40*4882a593Smuzhiyun container_of(x, struct vmw_screen_object_unit, base.encoder)
41*4882a593Smuzhiyun #define vmw_connector_to_sou(x) \
42*4882a593Smuzhiyun container_of(x, struct vmw_screen_object_unit, base.connector)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /**
45*4882a593Smuzhiyun * struct vmw_kms_sou_surface_dirty - Closure structure for
46*4882a593Smuzhiyun * blit surface to screen command.
47*4882a593Smuzhiyun * @base: The base type we derive from. Used by vmw_kms_helper_dirty().
48*4882a593Smuzhiyun * @left: Left side of bounding box.
49*4882a593Smuzhiyun * @right: Right side of bounding box.
50*4882a593Smuzhiyun * @top: Top side of bounding box.
51*4882a593Smuzhiyun * @bottom: Bottom side of bounding box.
52*4882a593Smuzhiyun * @dst_x: Difference between source clip rects and framebuffer coordinates.
53*4882a593Smuzhiyun * @dst_y: Difference between source clip rects and framebuffer coordinates.
54*4882a593Smuzhiyun * @sid: Surface id of surface to copy from.
55*4882a593Smuzhiyun */
56*4882a593Smuzhiyun struct vmw_kms_sou_surface_dirty {
57*4882a593Smuzhiyun struct vmw_kms_dirty base;
58*4882a593Smuzhiyun s32 left, right, top, bottom;
59*4882a593Smuzhiyun s32 dst_x, dst_y;
60*4882a593Smuzhiyun u32 sid;
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * SVGA commands that are used by this code. Please see the device headers
65*4882a593Smuzhiyun * for explanation.
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun struct vmw_kms_sou_readback_blit {
68*4882a593Smuzhiyun uint32 header;
69*4882a593Smuzhiyun SVGAFifoCmdBlitScreenToGMRFB body;
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun struct vmw_kms_sou_bo_blit {
73*4882a593Smuzhiyun uint32 header;
74*4882a593Smuzhiyun SVGAFifoCmdBlitGMRFBToScreen body;
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun struct vmw_kms_sou_dirty_cmd {
78*4882a593Smuzhiyun SVGA3dCmdHeader header;
79*4882a593Smuzhiyun SVGA3dCmdBlitSurfaceToScreen body;
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun struct vmw_kms_sou_define_gmrfb {
83*4882a593Smuzhiyun uint32_t header;
84*4882a593Smuzhiyun SVGAFifoCmdDefineGMRFB body;
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /**
88*4882a593Smuzhiyun * Display unit using screen objects.
89*4882a593Smuzhiyun */
90*4882a593Smuzhiyun struct vmw_screen_object_unit {
91*4882a593Smuzhiyun struct vmw_display_unit base;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun unsigned long buffer_size; /**< Size of allocated buffer */
94*4882a593Smuzhiyun struct vmw_buffer_object *buffer; /**< Backing store buffer */
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun bool defined;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
vmw_sou_destroy(struct vmw_screen_object_unit * sou)99*4882a593Smuzhiyun static void vmw_sou_destroy(struct vmw_screen_object_unit *sou)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun vmw_du_cleanup(&sou->base);
102*4882a593Smuzhiyun kfree(sou);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /*
107*4882a593Smuzhiyun * Screen Object Display Unit CRTC functions
108*4882a593Smuzhiyun */
109*4882a593Smuzhiyun
vmw_sou_crtc_destroy(struct drm_crtc * crtc)110*4882a593Smuzhiyun static void vmw_sou_crtc_destroy(struct drm_crtc *crtc)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun vmw_sou_destroy(vmw_crtc_to_sou(crtc));
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /**
116*4882a593Smuzhiyun * Send the fifo command to create a screen.
117*4882a593Smuzhiyun */
vmw_sou_fifo_create(struct vmw_private * dev_priv,struct vmw_screen_object_unit * sou,int x,int y,struct drm_display_mode * mode)118*4882a593Smuzhiyun static int vmw_sou_fifo_create(struct vmw_private *dev_priv,
119*4882a593Smuzhiyun struct vmw_screen_object_unit *sou,
120*4882a593Smuzhiyun int x, int y,
121*4882a593Smuzhiyun struct drm_display_mode *mode)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun size_t fifo_size;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun struct {
126*4882a593Smuzhiyun struct {
127*4882a593Smuzhiyun uint32_t cmdType;
128*4882a593Smuzhiyun } header;
129*4882a593Smuzhiyun SVGAScreenObject obj;
130*4882a593Smuzhiyun } *cmd;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun BUG_ON(!sou->buffer);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun fifo_size = sizeof(*cmd);
135*4882a593Smuzhiyun cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size);
136*4882a593Smuzhiyun if (unlikely(cmd == NULL))
137*4882a593Smuzhiyun return -ENOMEM;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun memset(cmd, 0, fifo_size);
140*4882a593Smuzhiyun cmd->header.cmdType = SVGA_CMD_DEFINE_SCREEN;
141*4882a593Smuzhiyun cmd->obj.structSize = sizeof(SVGAScreenObject);
142*4882a593Smuzhiyun cmd->obj.id = sou->base.unit;
143*4882a593Smuzhiyun cmd->obj.flags = SVGA_SCREEN_HAS_ROOT |
144*4882a593Smuzhiyun (sou->base.unit == 0 ? SVGA_SCREEN_IS_PRIMARY : 0);
145*4882a593Smuzhiyun cmd->obj.size.width = mode->hdisplay;
146*4882a593Smuzhiyun cmd->obj.size.height = mode->vdisplay;
147*4882a593Smuzhiyun cmd->obj.root.x = x;
148*4882a593Smuzhiyun cmd->obj.root.y = y;
149*4882a593Smuzhiyun sou->base.set_gui_x = cmd->obj.root.x;
150*4882a593Smuzhiyun sou->base.set_gui_y = cmd->obj.root.y;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun /* Ok to assume that buffer is pinned in vram */
153*4882a593Smuzhiyun vmw_bo_get_guest_ptr(&sou->buffer->base, &cmd->obj.backingStore.ptr);
154*4882a593Smuzhiyun cmd->obj.backingStore.pitch = mode->hdisplay * 4;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun vmw_fifo_commit(dev_priv, fifo_size);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun sou->defined = true;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun return 0;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun /**
164*4882a593Smuzhiyun * Send the fifo command to destroy a screen.
165*4882a593Smuzhiyun */
vmw_sou_fifo_destroy(struct vmw_private * dev_priv,struct vmw_screen_object_unit * sou)166*4882a593Smuzhiyun static int vmw_sou_fifo_destroy(struct vmw_private *dev_priv,
167*4882a593Smuzhiyun struct vmw_screen_object_unit *sou)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun size_t fifo_size;
170*4882a593Smuzhiyun int ret;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun struct {
173*4882a593Smuzhiyun struct {
174*4882a593Smuzhiyun uint32_t cmdType;
175*4882a593Smuzhiyun } header;
176*4882a593Smuzhiyun SVGAFifoCmdDestroyScreen body;
177*4882a593Smuzhiyun } *cmd;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /* no need to do anything */
180*4882a593Smuzhiyun if (unlikely(!sou->defined))
181*4882a593Smuzhiyun return 0;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun fifo_size = sizeof(*cmd);
184*4882a593Smuzhiyun cmd = VMW_FIFO_RESERVE(dev_priv, fifo_size);
185*4882a593Smuzhiyun if (unlikely(cmd == NULL))
186*4882a593Smuzhiyun return -ENOMEM;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun memset(cmd, 0, fifo_size);
189*4882a593Smuzhiyun cmd->header.cmdType = SVGA_CMD_DESTROY_SCREEN;
190*4882a593Smuzhiyun cmd->body.screenId = sou->base.unit;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun vmw_fifo_commit(dev_priv, fifo_size);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* Force sync */
195*4882a593Smuzhiyun ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
196*4882a593Smuzhiyun if (unlikely(ret != 0))
197*4882a593Smuzhiyun DRM_ERROR("Failed to sync with HW");
198*4882a593Smuzhiyun else
199*4882a593Smuzhiyun sou->defined = false;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun return ret;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /**
205*4882a593Smuzhiyun * vmw_sou_crtc_mode_set_nofb - Create new screen
206*4882a593Smuzhiyun *
207*4882a593Smuzhiyun * @crtc: CRTC associated with the new screen
208*4882a593Smuzhiyun *
209*4882a593Smuzhiyun * This function creates/destroys a screen. This function cannot fail, so if
210*4882a593Smuzhiyun * somehow we run into a failure, just do the best we can to get out.
211*4882a593Smuzhiyun */
vmw_sou_crtc_mode_set_nofb(struct drm_crtc * crtc)212*4882a593Smuzhiyun static void vmw_sou_crtc_mode_set_nofb(struct drm_crtc *crtc)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun struct vmw_private *dev_priv;
215*4882a593Smuzhiyun struct vmw_screen_object_unit *sou;
216*4882a593Smuzhiyun struct vmw_framebuffer *vfb;
217*4882a593Smuzhiyun struct drm_framebuffer *fb;
218*4882a593Smuzhiyun struct drm_plane_state *ps;
219*4882a593Smuzhiyun struct vmw_plane_state *vps;
220*4882a593Smuzhiyun int ret;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun sou = vmw_crtc_to_sou(crtc);
223*4882a593Smuzhiyun dev_priv = vmw_priv(crtc->dev);
224*4882a593Smuzhiyun ps = crtc->primary->state;
225*4882a593Smuzhiyun fb = ps->fb;
226*4882a593Smuzhiyun vps = vmw_plane_state_to_vps(ps);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun vfb = (fb) ? vmw_framebuffer_to_vfb(fb) : NULL;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun if (sou->defined) {
231*4882a593Smuzhiyun ret = vmw_sou_fifo_destroy(dev_priv, sou);
232*4882a593Smuzhiyun if (ret) {
233*4882a593Smuzhiyun DRM_ERROR("Failed to destroy Screen Object\n");
234*4882a593Smuzhiyun return;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun if (vfb) {
239*4882a593Smuzhiyun struct drm_connector_state *conn_state;
240*4882a593Smuzhiyun struct vmw_connector_state *vmw_conn_state;
241*4882a593Smuzhiyun int x, y;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun sou->buffer = vps->bo;
244*4882a593Smuzhiyun sou->buffer_size = vps->bo_size;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun conn_state = sou->base.connector.state;
247*4882a593Smuzhiyun vmw_conn_state = vmw_connector_state_to_vcs(conn_state);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun x = vmw_conn_state->gui_x;
250*4882a593Smuzhiyun y = vmw_conn_state->gui_y;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun ret = vmw_sou_fifo_create(dev_priv, sou, x, y, &crtc->mode);
253*4882a593Smuzhiyun if (ret)
254*4882a593Smuzhiyun DRM_ERROR("Failed to define Screen Object %dx%d\n",
255*4882a593Smuzhiyun crtc->x, crtc->y);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun } else {
258*4882a593Smuzhiyun sou->buffer = NULL;
259*4882a593Smuzhiyun sou->buffer_size = 0;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /**
264*4882a593Smuzhiyun * vmw_sou_crtc_helper_prepare - Noop
265*4882a593Smuzhiyun *
266*4882a593Smuzhiyun * @crtc: CRTC associated with the new screen
267*4882a593Smuzhiyun *
268*4882a593Smuzhiyun * Prepares the CRTC for a mode set, but we don't need to do anything here.
269*4882a593Smuzhiyun */
vmw_sou_crtc_helper_prepare(struct drm_crtc * crtc)270*4882a593Smuzhiyun static void vmw_sou_crtc_helper_prepare(struct drm_crtc *crtc)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun /**
275*4882a593Smuzhiyun * vmw_sou_crtc_atomic_enable - Noop
276*4882a593Smuzhiyun *
277*4882a593Smuzhiyun * @crtc: CRTC associated with the new screen
278*4882a593Smuzhiyun *
279*4882a593Smuzhiyun * This is called after a mode set has been completed.
280*4882a593Smuzhiyun */
vmw_sou_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)281*4882a593Smuzhiyun static void vmw_sou_crtc_atomic_enable(struct drm_crtc *crtc,
282*4882a593Smuzhiyun struct drm_crtc_state *old_state)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun /**
287*4882a593Smuzhiyun * vmw_sou_crtc_atomic_disable - Turns off CRTC
288*4882a593Smuzhiyun *
289*4882a593Smuzhiyun * @crtc: CRTC to be turned off
290*4882a593Smuzhiyun */
vmw_sou_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)291*4882a593Smuzhiyun static void vmw_sou_crtc_atomic_disable(struct drm_crtc *crtc,
292*4882a593Smuzhiyun struct drm_crtc_state *old_state)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun struct vmw_private *dev_priv;
295*4882a593Smuzhiyun struct vmw_screen_object_unit *sou;
296*4882a593Smuzhiyun int ret;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun if (!crtc) {
300*4882a593Smuzhiyun DRM_ERROR("CRTC is NULL\n");
301*4882a593Smuzhiyun return;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun sou = vmw_crtc_to_sou(crtc);
305*4882a593Smuzhiyun dev_priv = vmw_priv(crtc->dev);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun if (sou->defined) {
308*4882a593Smuzhiyun ret = vmw_sou_fifo_destroy(dev_priv, sou);
309*4882a593Smuzhiyun if (ret)
310*4882a593Smuzhiyun DRM_ERROR("Failed to destroy Screen Object\n");
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun static const struct drm_crtc_funcs vmw_screen_object_crtc_funcs = {
315*4882a593Smuzhiyun .gamma_set = vmw_du_crtc_gamma_set,
316*4882a593Smuzhiyun .destroy = vmw_sou_crtc_destroy,
317*4882a593Smuzhiyun .reset = vmw_du_crtc_reset,
318*4882a593Smuzhiyun .atomic_duplicate_state = vmw_du_crtc_duplicate_state,
319*4882a593Smuzhiyun .atomic_destroy_state = vmw_du_crtc_destroy_state,
320*4882a593Smuzhiyun .set_config = drm_atomic_helper_set_config,
321*4882a593Smuzhiyun .page_flip = drm_atomic_helper_page_flip,
322*4882a593Smuzhiyun .get_vblank_counter = vmw_get_vblank_counter,
323*4882a593Smuzhiyun .enable_vblank = vmw_enable_vblank,
324*4882a593Smuzhiyun .disable_vblank = vmw_disable_vblank,
325*4882a593Smuzhiyun };
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /*
328*4882a593Smuzhiyun * Screen Object Display Unit encoder functions
329*4882a593Smuzhiyun */
330*4882a593Smuzhiyun
vmw_sou_encoder_destroy(struct drm_encoder * encoder)331*4882a593Smuzhiyun static void vmw_sou_encoder_destroy(struct drm_encoder *encoder)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun vmw_sou_destroy(vmw_encoder_to_sou(encoder));
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun static const struct drm_encoder_funcs vmw_screen_object_encoder_funcs = {
337*4882a593Smuzhiyun .destroy = vmw_sou_encoder_destroy,
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun /*
341*4882a593Smuzhiyun * Screen Object Display Unit connector functions
342*4882a593Smuzhiyun */
343*4882a593Smuzhiyun
vmw_sou_connector_destroy(struct drm_connector * connector)344*4882a593Smuzhiyun static void vmw_sou_connector_destroy(struct drm_connector *connector)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun vmw_sou_destroy(vmw_connector_to_sou(connector));
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun static const struct drm_connector_funcs vmw_sou_connector_funcs = {
350*4882a593Smuzhiyun .dpms = vmw_du_connector_dpms,
351*4882a593Smuzhiyun .detect = vmw_du_connector_detect,
352*4882a593Smuzhiyun .fill_modes = vmw_du_connector_fill_modes,
353*4882a593Smuzhiyun .destroy = vmw_sou_connector_destroy,
354*4882a593Smuzhiyun .reset = vmw_du_connector_reset,
355*4882a593Smuzhiyun .atomic_duplicate_state = vmw_du_connector_duplicate_state,
356*4882a593Smuzhiyun .atomic_destroy_state = vmw_du_connector_destroy_state,
357*4882a593Smuzhiyun };
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun static const struct
361*4882a593Smuzhiyun drm_connector_helper_funcs vmw_sou_connector_helper_funcs = {
362*4882a593Smuzhiyun };
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /*
367*4882a593Smuzhiyun * Screen Object Display Plane Functions
368*4882a593Smuzhiyun */
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun /**
371*4882a593Smuzhiyun * vmw_sou_primary_plane_cleanup_fb - Frees sou backing buffer
372*4882a593Smuzhiyun *
373*4882a593Smuzhiyun * @plane: display plane
374*4882a593Smuzhiyun * @old_state: Contains the FB to clean up
375*4882a593Smuzhiyun *
376*4882a593Smuzhiyun * Unpins the display surface
377*4882a593Smuzhiyun *
378*4882a593Smuzhiyun * Returns 0 on success
379*4882a593Smuzhiyun */
380*4882a593Smuzhiyun static void
vmw_sou_primary_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * old_state)381*4882a593Smuzhiyun vmw_sou_primary_plane_cleanup_fb(struct drm_plane *plane,
382*4882a593Smuzhiyun struct drm_plane_state *old_state)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun struct vmw_plane_state *vps = vmw_plane_state_to_vps(old_state);
385*4882a593Smuzhiyun struct drm_crtc *crtc = plane->state->crtc ?
386*4882a593Smuzhiyun plane->state->crtc : old_state->crtc;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun if (vps->bo)
389*4882a593Smuzhiyun vmw_bo_unpin(vmw_priv(crtc->dev), vps->bo, false);
390*4882a593Smuzhiyun vmw_bo_unreference(&vps->bo);
391*4882a593Smuzhiyun vps->bo_size = 0;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun vmw_du_plane_cleanup_fb(plane, old_state);
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun /**
398*4882a593Smuzhiyun * vmw_sou_primary_plane_prepare_fb - allocate backing buffer
399*4882a593Smuzhiyun *
400*4882a593Smuzhiyun * @plane: display plane
401*4882a593Smuzhiyun * @new_state: info on the new plane state, including the FB
402*4882a593Smuzhiyun *
403*4882a593Smuzhiyun * The SOU backing buffer is our equivalent of the display plane.
404*4882a593Smuzhiyun *
405*4882a593Smuzhiyun * Returns 0 on success
406*4882a593Smuzhiyun */
407*4882a593Smuzhiyun static int
vmw_sou_primary_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)408*4882a593Smuzhiyun vmw_sou_primary_plane_prepare_fb(struct drm_plane *plane,
409*4882a593Smuzhiyun struct drm_plane_state *new_state)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun struct drm_framebuffer *new_fb = new_state->fb;
412*4882a593Smuzhiyun struct drm_crtc *crtc = plane->state->crtc ?: new_state->crtc;
413*4882a593Smuzhiyun struct vmw_plane_state *vps = vmw_plane_state_to_vps(new_state);
414*4882a593Smuzhiyun struct vmw_private *dev_priv;
415*4882a593Smuzhiyun size_t size;
416*4882a593Smuzhiyun int ret;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun if (!new_fb) {
420*4882a593Smuzhiyun vmw_bo_unreference(&vps->bo);
421*4882a593Smuzhiyun vps->bo_size = 0;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun return 0;
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun size = new_state->crtc_w * new_state->crtc_h * 4;
427*4882a593Smuzhiyun dev_priv = vmw_priv(crtc->dev);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun if (vps->bo) {
430*4882a593Smuzhiyun if (vps->bo_size == size) {
431*4882a593Smuzhiyun /*
432*4882a593Smuzhiyun * Note that this might temporarily up the pin-count
433*4882a593Smuzhiyun * to 2, until cleanup_fb() is called.
434*4882a593Smuzhiyun */
435*4882a593Smuzhiyun return vmw_bo_pin_in_vram(dev_priv, vps->bo,
436*4882a593Smuzhiyun true);
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun vmw_bo_unreference(&vps->bo);
440*4882a593Smuzhiyun vps->bo_size = 0;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun vps->bo = kzalloc(sizeof(*vps->bo), GFP_KERNEL);
444*4882a593Smuzhiyun if (!vps->bo)
445*4882a593Smuzhiyun return -ENOMEM;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun vmw_svga_enable(dev_priv);
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun /* After we have alloced the backing store might not be able to
450*4882a593Smuzhiyun * resume the overlays, this is preferred to failing to alloc.
451*4882a593Smuzhiyun */
452*4882a593Smuzhiyun vmw_overlay_pause_all(dev_priv);
453*4882a593Smuzhiyun ret = vmw_bo_init(dev_priv, vps->bo, size,
454*4882a593Smuzhiyun &vmw_vram_ne_placement,
455*4882a593Smuzhiyun false, &vmw_bo_bo_free);
456*4882a593Smuzhiyun vmw_overlay_resume_all(dev_priv);
457*4882a593Smuzhiyun if (ret) {
458*4882a593Smuzhiyun vps->bo = NULL; /* vmw_bo_init frees on error */
459*4882a593Smuzhiyun return ret;
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun vps->bo_size = size;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun /*
465*4882a593Smuzhiyun * TTM already thinks the buffer is pinned, but make sure the
466*4882a593Smuzhiyun * pin_count is upped.
467*4882a593Smuzhiyun */
468*4882a593Smuzhiyun return vmw_bo_pin_in_vram(dev_priv, vps->bo, true);
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun
vmw_sou_bo_fifo_size(struct vmw_du_update_plane * update,uint32_t num_hits)471*4882a593Smuzhiyun static uint32_t vmw_sou_bo_fifo_size(struct vmw_du_update_plane *update,
472*4882a593Smuzhiyun uint32_t num_hits)
473*4882a593Smuzhiyun {
474*4882a593Smuzhiyun return sizeof(struct vmw_kms_sou_define_gmrfb) +
475*4882a593Smuzhiyun sizeof(struct vmw_kms_sou_bo_blit) * num_hits;
476*4882a593Smuzhiyun }
477*4882a593Smuzhiyun
vmw_sou_bo_define_gmrfb(struct vmw_du_update_plane * update,void * cmd)478*4882a593Smuzhiyun static uint32_t vmw_sou_bo_define_gmrfb(struct vmw_du_update_plane *update,
479*4882a593Smuzhiyun void *cmd)
480*4882a593Smuzhiyun {
481*4882a593Smuzhiyun struct vmw_framebuffer_bo *vfbbo =
482*4882a593Smuzhiyun container_of(update->vfb, typeof(*vfbbo), base);
483*4882a593Smuzhiyun struct vmw_kms_sou_define_gmrfb *gmr = cmd;
484*4882a593Smuzhiyun int depth = update->vfb->base.format->depth;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun /* Emulate RGBA support, contrary to svga_reg.h this is not
487*4882a593Smuzhiyun * supported by hosts. This is only a problem if we are reading
488*4882a593Smuzhiyun * this value later and expecting what we uploaded back.
489*4882a593Smuzhiyun */
490*4882a593Smuzhiyun if (depth == 32)
491*4882a593Smuzhiyun depth = 24;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun gmr->header = SVGA_CMD_DEFINE_GMRFB;
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun gmr->body.format.bitsPerPixel = update->vfb->base.format->cpp[0] * 8;
496*4882a593Smuzhiyun gmr->body.format.colorDepth = depth;
497*4882a593Smuzhiyun gmr->body.format.reserved = 0;
498*4882a593Smuzhiyun gmr->body.bytesPerLine = update->vfb->base.pitches[0];
499*4882a593Smuzhiyun vmw_bo_get_guest_ptr(&vfbbo->buffer->base, &gmr->body.ptr);
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun return sizeof(*gmr);
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun
vmw_sou_bo_populate_clip(struct vmw_du_update_plane * update,void * cmd,struct drm_rect * clip,uint32_t fb_x,uint32_t fb_y)504*4882a593Smuzhiyun static uint32_t vmw_sou_bo_populate_clip(struct vmw_du_update_plane *update,
505*4882a593Smuzhiyun void *cmd, struct drm_rect *clip,
506*4882a593Smuzhiyun uint32_t fb_x, uint32_t fb_y)
507*4882a593Smuzhiyun {
508*4882a593Smuzhiyun struct vmw_kms_sou_bo_blit *blit = cmd;
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun blit->header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
511*4882a593Smuzhiyun blit->body.destScreenId = update->du->unit;
512*4882a593Smuzhiyun blit->body.srcOrigin.x = fb_x;
513*4882a593Smuzhiyun blit->body.srcOrigin.y = fb_y;
514*4882a593Smuzhiyun blit->body.destRect.left = clip->x1;
515*4882a593Smuzhiyun blit->body.destRect.top = clip->y1;
516*4882a593Smuzhiyun blit->body.destRect.right = clip->x2;
517*4882a593Smuzhiyun blit->body.destRect.bottom = clip->y2;
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun return sizeof(*blit);
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
vmw_stud_bo_post_clip(struct vmw_du_update_plane * update,void * cmd,struct drm_rect * bb)522*4882a593Smuzhiyun static uint32_t vmw_stud_bo_post_clip(struct vmw_du_update_plane *update,
523*4882a593Smuzhiyun void *cmd, struct drm_rect *bb)
524*4882a593Smuzhiyun {
525*4882a593Smuzhiyun return 0;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun /**
529*4882a593Smuzhiyun * vmw_sou_plane_update_bo - Update display unit for bo backed fb.
530*4882a593Smuzhiyun * @dev_priv: Device private.
531*4882a593Smuzhiyun * @plane: Plane state.
532*4882a593Smuzhiyun * @old_state: Old plane state.
533*4882a593Smuzhiyun * @vfb: Framebuffer which is blitted to display unit.
534*4882a593Smuzhiyun * @out_fence: If non-NULL, will return a ref-counted pointer to vmw_fence_obj.
535*4882a593Smuzhiyun * The returned fence pointer may be NULL in which case the device
536*4882a593Smuzhiyun * has already synchronized.
537*4882a593Smuzhiyun *
538*4882a593Smuzhiyun * Return: 0 on success or a negative error code on failure.
539*4882a593Smuzhiyun */
vmw_sou_plane_update_bo(struct vmw_private * dev_priv,struct drm_plane * plane,struct drm_plane_state * old_state,struct vmw_framebuffer * vfb,struct vmw_fence_obj ** out_fence)540*4882a593Smuzhiyun static int vmw_sou_plane_update_bo(struct vmw_private *dev_priv,
541*4882a593Smuzhiyun struct drm_plane *plane,
542*4882a593Smuzhiyun struct drm_plane_state *old_state,
543*4882a593Smuzhiyun struct vmw_framebuffer *vfb,
544*4882a593Smuzhiyun struct vmw_fence_obj **out_fence)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun struct vmw_du_update_plane_buffer bo_update;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun memset(&bo_update, 0, sizeof(struct vmw_du_update_plane_buffer));
549*4882a593Smuzhiyun bo_update.base.plane = plane;
550*4882a593Smuzhiyun bo_update.base.old_state = old_state;
551*4882a593Smuzhiyun bo_update.base.dev_priv = dev_priv;
552*4882a593Smuzhiyun bo_update.base.du = vmw_crtc_to_du(plane->state->crtc);
553*4882a593Smuzhiyun bo_update.base.vfb = vfb;
554*4882a593Smuzhiyun bo_update.base.out_fence = out_fence;
555*4882a593Smuzhiyun bo_update.base.mutex = NULL;
556*4882a593Smuzhiyun bo_update.base.cpu_blit = false;
557*4882a593Smuzhiyun bo_update.base.intr = true;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun bo_update.base.calc_fifo_size = vmw_sou_bo_fifo_size;
560*4882a593Smuzhiyun bo_update.base.post_prepare = vmw_sou_bo_define_gmrfb;
561*4882a593Smuzhiyun bo_update.base.clip = vmw_sou_bo_populate_clip;
562*4882a593Smuzhiyun bo_update.base.post_clip = vmw_stud_bo_post_clip;
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun return vmw_du_helper_plane_update(&bo_update.base);
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun
vmw_sou_surface_fifo_size(struct vmw_du_update_plane * update,uint32_t num_hits)567*4882a593Smuzhiyun static uint32_t vmw_sou_surface_fifo_size(struct vmw_du_update_plane *update,
568*4882a593Smuzhiyun uint32_t num_hits)
569*4882a593Smuzhiyun {
570*4882a593Smuzhiyun return sizeof(struct vmw_kms_sou_dirty_cmd) + sizeof(SVGASignedRect) *
571*4882a593Smuzhiyun num_hits;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun
vmw_sou_surface_post_prepare(struct vmw_du_update_plane * update,void * cmd)574*4882a593Smuzhiyun static uint32_t vmw_sou_surface_post_prepare(struct vmw_du_update_plane *update,
575*4882a593Smuzhiyun void *cmd)
576*4882a593Smuzhiyun {
577*4882a593Smuzhiyun struct vmw_du_update_plane_surface *srf_update;
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun srf_update = container_of(update, typeof(*srf_update), base);
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun /*
582*4882a593Smuzhiyun * SOU SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN is special in the sense that
583*4882a593Smuzhiyun * its bounding box is filled before iterating over all the clips. So
584*4882a593Smuzhiyun * store the FIFO start address and revisit to fill the details.
585*4882a593Smuzhiyun */
586*4882a593Smuzhiyun srf_update->cmd_start = cmd;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun return 0;
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun
vmw_sou_surface_pre_clip(struct vmw_du_update_plane * update,void * cmd,uint32_t num_hits)591*4882a593Smuzhiyun static uint32_t vmw_sou_surface_pre_clip(struct vmw_du_update_plane *update,
592*4882a593Smuzhiyun void *cmd, uint32_t num_hits)
593*4882a593Smuzhiyun {
594*4882a593Smuzhiyun struct vmw_kms_sou_dirty_cmd *blit = cmd;
595*4882a593Smuzhiyun struct vmw_framebuffer_surface *vfbs;
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun vfbs = container_of(update->vfb, typeof(*vfbs), base);
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun blit->header.id = SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN;
600*4882a593Smuzhiyun blit->header.size = sizeof(blit->body) + sizeof(SVGASignedRect) *
601*4882a593Smuzhiyun num_hits;
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun blit->body.srcImage.sid = vfbs->surface->res.id;
604*4882a593Smuzhiyun blit->body.destScreenId = update->du->unit;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun /* Update the source and destination bounding box later in post_clip */
607*4882a593Smuzhiyun blit->body.srcRect.left = 0;
608*4882a593Smuzhiyun blit->body.srcRect.top = 0;
609*4882a593Smuzhiyun blit->body.srcRect.right = 0;
610*4882a593Smuzhiyun blit->body.srcRect.bottom = 0;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun blit->body.destRect.left = 0;
613*4882a593Smuzhiyun blit->body.destRect.top = 0;
614*4882a593Smuzhiyun blit->body.destRect.right = 0;
615*4882a593Smuzhiyun blit->body.destRect.bottom = 0;
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun return sizeof(*blit);
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
vmw_sou_surface_clip_rect(struct vmw_du_update_plane * update,void * cmd,struct drm_rect * clip,uint32_t src_x,uint32_t src_y)620*4882a593Smuzhiyun static uint32_t vmw_sou_surface_clip_rect(struct vmw_du_update_plane *update,
621*4882a593Smuzhiyun void *cmd, struct drm_rect *clip,
622*4882a593Smuzhiyun uint32_t src_x, uint32_t src_y)
623*4882a593Smuzhiyun {
624*4882a593Smuzhiyun SVGASignedRect *rect = cmd;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun /*
627*4882a593Smuzhiyun * rects are relative to dest bounding box rect on screen object, so
628*4882a593Smuzhiyun * translate to it later in post_clip
629*4882a593Smuzhiyun */
630*4882a593Smuzhiyun rect->left = clip->x1;
631*4882a593Smuzhiyun rect->top = clip->y1;
632*4882a593Smuzhiyun rect->right = clip->x2;
633*4882a593Smuzhiyun rect->bottom = clip->y2;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun return sizeof(*rect);
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun
vmw_sou_surface_post_clip(struct vmw_du_update_plane * update,void * cmd,struct drm_rect * bb)638*4882a593Smuzhiyun static uint32_t vmw_sou_surface_post_clip(struct vmw_du_update_plane *update,
639*4882a593Smuzhiyun void *cmd, struct drm_rect *bb)
640*4882a593Smuzhiyun {
641*4882a593Smuzhiyun struct vmw_du_update_plane_surface *srf_update;
642*4882a593Smuzhiyun struct drm_plane_state *state = update->plane->state;
643*4882a593Smuzhiyun struct drm_rect src_bb;
644*4882a593Smuzhiyun struct vmw_kms_sou_dirty_cmd *blit;
645*4882a593Smuzhiyun SVGASignedRect *rect;
646*4882a593Smuzhiyun uint32_t num_hits;
647*4882a593Smuzhiyun int translate_src_x;
648*4882a593Smuzhiyun int translate_src_y;
649*4882a593Smuzhiyun int i;
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun srf_update = container_of(update, typeof(*srf_update), base);
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun blit = srf_update->cmd_start;
654*4882a593Smuzhiyun rect = (SVGASignedRect *)&blit[1];
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun num_hits = (blit->header.size - sizeof(blit->body))/
657*4882a593Smuzhiyun sizeof(SVGASignedRect);
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun src_bb = *bb;
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun /* To translate bb back to fb src coord */
662*4882a593Smuzhiyun translate_src_x = (state->src_x >> 16) - state->crtc_x;
663*4882a593Smuzhiyun translate_src_y = (state->src_y >> 16) - state->crtc_y;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun drm_rect_translate(&src_bb, translate_src_x, translate_src_y);
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun blit->body.srcRect.left = src_bb.x1;
668*4882a593Smuzhiyun blit->body.srcRect.top = src_bb.y1;
669*4882a593Smuzhiyun blit->body.srcRect.right = src_bb.x2;
670*4882a593Smuzhiyun blit->body.srcRect.bottom = src_bb.y2;
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun blit->body.destRect.left = bb->x1;
673*4882a593Smuzhiyun blit->body.destRect.top = bb->y1;
674*4882a593Smuzhiyun blit->body.destRect.right = bb->x2;
675*4882a593Smuzhiyun blit->body.destRect.bottom = bb->y2;
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun /* rects are relative to dest bb rect */
678*4882a593Smuzhiyun for (i = 0; i < num_hits; i++) {
679*4882a593Smuzhiyun rect->left -= bb->x1;
680*4882a593Smuzhiyun rect->top -= bb->y1;
681*4882a593Smuzhiyun rect->right -= bb->x1;
682*4882a593Smuzhiyun rect->bottom -= bb->y1;
683*4882a593Smuzhiyun rect++;
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun return 0;
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun /**
690*4882a593Smuzhiyun * vmw_sou_plane_update_surface - Update display unit for surface backed fb.
691*4882a593Smuzhiyun * @dev_priv: Device private.
692*4882a593Smuzhiyun * @plane: Plane state.
693*4882a593Smuzhiyun * @old_state: Old plane state.
694*4882a593Smuzhiyun * @vfb: Framebuffer which is blitted to display unit
695*4882a593Smuzhiyun * @out_fence: If non-NULL, will return a ref-counted pointer to vmw_fence_obj.
696*4882a593Smuzhiyun * The returned fence pointer may be NULL in which case the device
697*4882a593Smuzhiyun * has already synchronized.
698*4882a593Smuzhiyun *
699*4882a593Smuzhiyun * Return: 0 on success or a negative error code on failure.
700*4882a593Smuzhiyun */
vmw_sou_plane_update_surface(struct vmw_private * dev_priv,struct drm_plane * plane,struct drm_plane_state * old_state,struct vmw_framebuffer * vfb,struct vmw_fence_obj ** out_fence)701*4882a593Smuzhiyun static int vmw_sou_plane_update_surface(struct vmw_private *dev_priv,
702*4882a593Smuzhiyun struct drm_plane *plane,
703*4882a593Smuzhiyun struct drm_plane_state *old_state,
704*4882a593Smuzhiyun struct vmw_framebuffer *vfb,
705*4882a593Smuzhiyun struct vmw_fence_obj **out_fence)
706*4882a593Smuzhiyun {
707*4882a593Smuzhiyun struct vmw_du_update_plane_surface srf_update;
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun memset(&srf_update, 0, sizeof(struct vmw_du_update_plane_surface));
710*4882a593Smuzhiyun srf_update.base.plane = plane;
711*4882a593Smuzhiyun srf_update.base.old_state = old_state;
712*4882a593Smuzhiyun srf_update.base.dev_priv = dev_priv;
713*4882a593Smuzhiyun srf_update.base.du = vmw_crtc_to_du(plane->state->crtc);
714*4882a593Smuzhiyun srf_update.base.vfb = vfb;
715*4882a593Smuzhiyun srf_update.base.out_fence = out_fence;
716*4882a593Smuzhiyun srf_update.base.mutex = &dev_priv->cmdbuf_mutex;
717*4882a593Smuzhiyun srf_update.base.cpu_blit = false;
718*4882a593Smuzhiyun srf_update.base.intr = true;
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun srf_update.base.calc_fifo_size = vmw_sou_surface_fifo_size;
721*4882a593Smuzhiyun srf_update.base.post_prepare = vmw_sou_surface_post_prepare;
722*4882a593Smuzhiyun srf_update.base.pre_clip = vmw_sou_surface_pre_clip;
723*4882a593Smuzhiyun srf_update.base.clip = vmw_sou_surface_clip_rect;
724*4882a593Smuzhiyun srf_update.base.post_clip = vmw_sou_surface_post_clip;
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun return vmw_du_helper_plane_update(&srf_update.base);
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun static void
vmw_sou_primary_plane_atomic_update(struct drm_plane * plane,struct drm_plane_state * old_state)730*4882a593Smuzhiyun vmw_sou_primary_plane_atomic_update(struct drm_plane *plane,
731*4882a593Smuzhiyun struct drm_plane_state *old_state)
732*4882a593Smuzhiyun {
733*4882a593Smuzhiyun struct drm_crtc *crtc = plane->state->crtc;
734*4882a593Smuzhiyun struct drm_pending_vblank_event *event = NULL;
735*4882a593Smuzhiyun struct vmw_fence_obj *fence = NULL;
736*4882a593Smuzhiyun int ret;
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun /* In case of device error, maintain consistent atomic state */
739*4882a593Smuzhiyun if (crtc && plane->state->fb) {
740*4882a593Smuzhiyun struct vmw_private *dev_priv = vmw_priv(crtc->dev);
741*4882a593Smuzhiyun struct vmw_framebuffer *vfb =
742*4882a593Smuzhiyun vmw_framebuffer_to_vfb(plane->state->fb);
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun if (vfb->bo)
745*4882a593Smuzhiyun ret = vmw_sou_plane_update_bo(dev_priv, plane,
746*4882a593Smuzhiyun old_state, vfb, &fence);
747*4882a593Smuzhiyun else
748*4882a593Smuzhiyun ret = vmw_sou_plane_update_surface(dev_priv, plane,
749*4882a593Smuzhiyun old_state, vfb,
750*4882a593Smuzhiyun &fence);
751*4882a593Smuzhiyun if (ret != 0)
752*4882a593Smuzhiyun DRM_ERROR("Failed to update screen.\n");
753*4882a593Smuzhiyun } else {
754*4882a593Smuzhiyun /* Do nothing when fb and crtc is NULL (blank crtc) */
755*4882a593Smuzhiyun return;
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun /* For error case vblank event is send from vmw_du_crtc_atomic_flush */
759*4882a593Smuzhiyun event = crtc->state->event;
760*4882a593Smuzhiyun if (event && fence) {
761*4882a593Smuzhiyun struct drm_file *file_priv = event->base.file_priv;
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun ret = vmw_event_fence_action_queue(file_priv,
764*4882a593Smuzhiyun fence,
765*4882a593Smuzhiyun &event->base,
766*4882a593Smuzhiyun &event->event.vbl.tv_sec,
767*4882a593Smuzhiyun &event->event.vbl.tv_usec,
768*4882a593Smuzhiyun true);
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun if (unlikely(ret != 0))
771*4882a593Smuzhiyun DRM_ERROR("Failed to queue event on fence.\n");
772*4882a593Smuzhiyun else
773*4882a593Smuzhiyun crtc->state->event = NULL;
774*4882a593Smuzhiyun }
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun if (fence)
777*4882a593Smuzhiyun vmw_fence_obj_unreference(&fence);
778*4882a593Smuzhiyun }
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun static const struct drm_plane_funcs vmw_sou_plane_funcs = {
782*4882a593Smuzhiyun .update_plane = drm_atomic_helper_update_plane,
783*4882a593Smuzhiyun .disable_plane = drm_atomic_helper_disable_plane,
784*4882a593Smuzhiyun .destroy = vmw_du_primary_plane_destroy,
785*4882a593Smuzhiyun .reset = vmw_du_plane_reset,
786*4882a593Smuzhiyun .atomic_duplicate_state = vmw_du_plane_duplicate_state,
787*4882a593Smuzhiyun .atomic_destroy_state = vmw_du_plane_destroy_state,
788*4882a593Smuzhiyun };
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun static const struct drm_plane_funcs vmw_sou_cursor_funcs = {
791*4882a593Smuzhiyun .update_plane = drm_atomic_helper_update_plane,
792*4882a593Smuzhiyun .disable_plane = drm_atomic_helper_disable_plane,
793*4882a593Smuzhiyun .destroy = vmw_du_cursor_plane_destroy,
794*4882a593Smuzhiyun .reset = vmw_du_plane_reset,
795*4882a593Smuzhiyun .atomic_duplicate_state = vmw_du_plane_duplicate_state,
796*4882a593Smuzhiyun .atomic_destroy_state = vmw_du_plane_destroy_state,
797*4882a593Smuzhiyun };
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun /*
800*4882a593Smuzhiyun * Atomic Helpers
801*4882a593Smuzhiyun */
802*4882a593Smuzhiyun static const struct
803*4882a593Smuzhiyun drm_plane_helper_funcs vmw_sou_cursor_plane_helper_funcs = {
804*4882a593Smuzhiyun .atomic_check = vmw_du_cursor_plane_atomic_check,
805*4882a593Smuzhiyun .atomic_update = vmw_du_cursor_plane_atomic_update,
806*4882a593Smuzhiyun .prepare_fb = vmw_du_cursor_plane_prepare_fb,
807*4882a593Smuzhiyun .cleanup_fb = vmw_du_plane_cleanup_fb,
808*4882a593Smuzhiyun };
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun static const struct
811*4882a593Smuzhiyun drm_plane_helper_funcs vmw_sou_primary_plane_helper_funcs = {
812*4882a593Smuzhiyun .atomic_check = vmw_du_primary_plane_atomic_check,
813*4882a593Smuzhiyun .atomic_update = vmw_sou_primary_plane_atomic_update,
814*4882a593Smuzhiyun .prepare_fb = vmw_sou_primary_plane_prepare_fb,
815*4882a593Smuzhiyun .cleanup_fb = vmw_sou_primary_plane_cleanup_fb,
816*4882a593Smuzhiyun };
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun static const struct drm_crtc_helper_funcs vmw_sou_crtc_helper_funcs = {
819*4882a593Smuzhiyun .prepare = vmw_sou_crtc_helper_prepare,
820*4882a593Smuzhiyun .mode_set_nofb = vmw_sou_crtc_mode_set_nofb,
821*4882a593Smuzhiyun .atomic_check = vmw_du_crtc_atomic_check,
822*4882a593Smuzhiyun .atomic_begin = vmw_du_crtc_atomic_begin,
823*4882a593Smuzhiyun .atomic_flush = vmw_du_crtc_atomic_flush,
824*4882a593Smuzhiyun .atomic_enable = vmw_sou_crtc_atomic_enable,
825*4882a593Smuzhiyun .atomic_disable = vmw_sou_crtc_atomic_disable,
826*4882a593Smuzhiyun };
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun
vmw_sou_init(struct vmw_private * dev_priv,unsigned unit)829*4882a593Smuzhiyun static int vmw_sou_init(struct vmw_private *dev_priv, unsigned unit)
830*4882a593Smuzhiyun {
831*4882a593Smuzhiyun struct vmw_screen_object_unit *sou;
832*4882a593Smuzhiyun struct drm_device *dev = dev_priv->dev;
833*4882a593Smuzhiyun struct drm_connector *connector;
834*4882a593Smuzhiyun struct drm_encoder *encoder;
835*4882a593Smuzhiyun struct drm_plane *primary, *cursor;
836*4882a593Smuzhiyun struct drm_crtc *crtc;
837*4882a593Smuzhiyun int ret;
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun sou = kzalloc(sizeof(*sou), GFP_KERNEL);
840*4882a593Smuzhiyun if (!sou)
841*4882a593Smuzhiyun return -ENOMEM;
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun sou->base.unit = unit;
844*4882a593Smuzhiyun crtc = &sou->base.crtc;
845*4882a593Smuzhiyun encoder = &sou->base.encoder;
846*4882a593Smuzhiyun connector = &sou->base.connector;
847*4882a593Smuzhiyun primary = &sou->base.primary;
848*4882a593Smuzhiyun cursor = &sou->base.cursor;
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun sou->base.pref_active = (unit == 0);
851*4882a593Smuzhiyun sou->base.pref_width = dev_priv->initial_width;
852*4882a593Smuzhiyun sou->base.pref_height = dev_priv->initial_height;
853*4882a593Smuzhiyun sou->base.pref_mode = NULL;
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun /*
856*4882a593Smuzhiyun * Remove this after enabling atomic because property values can
857*4882a593Smuzhiyun * only exist in a state object
858*4882a593Smuzhiyun */
859*4882a593Smuzhiyun sou->base.is_implicit = false;
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun /* Initialize primary plane */
862*4882a593Smuzhiyun ret = drm_universal_plane_init(dev, &sou->base.primary,
863*4882a593Smuzhiyun 0, &vmw_sou_plane_funcs,
864*4882a593Smuzhiyun vmw_primary_plane_formats,
865*4882a593Smuzhiyun ARRAY_SIZE(vmw_primary_plane_formats),
866*4882a593Smuzhiyun NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
867*4882a593Smuzhiyun if (ret) {
868*4882a593Smuzhiyun DRM_ERROR("Failed to initialize primary plane");
869*4882a593Smuzhiyun goto err_free;
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun drm_plane_helper_add(primary, &vmw_sou_primary_plane_helper_funcs);
873*4882a593Smuzhiyun drm_plane_enable_fb_damage_clips(primary);
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun /* Initialize cursor plane */
876*4882a593Smuzhiyun ret = drm_universal_plane_init(dev, &sou->base.cursor,
877*4882a593Smuzhiyun 0, &vmw_sou_cursor_funcs,
878*4882a593Smuzhiyun vmw_cursor_plane_formats,
879*4882a593Smuzhiyun ARRAY_SIZE(vmw_cursor_plane_formats),
880*4882a593Smuzhiyun NULL, DRM_PLANE_TYPE_CURSOR, NULL);
881*4882a593Smuzhiyun if (ret) {
882*4882a593Smuzhiyun DRM_ERROR("Failed to initialize cursor plane");
883*4882a593Smuzhiyun drm_plane_cleanup(&sou->base.primary);
884*4882a593Smuzhiyun goto err_free;
885*4882a593Smuzhiyun }
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun drm_plane_helper_add(cursor, &vmw_sou_cursor_plane_helper_funcs);
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun ret = drm_connector_init(dev, connector, &vmw_sou_connector_funcs,
890*4882a593Smuzhiyun DRM_MODE_CONNECTOR_VIRTUAL);
891*4882a593Smuzhiyun if (ret) {
892*4882a593Smuzhiyun DRM_ERROR("Failed to initialize connector\n");
893*4882a593Smuzhiyun goto err_free;
894*4882a593Smuzhiyun }
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun drm_connector_helper_add(connector, &vmw_sou_connector_helper_funcs);
897*4882a593Smuzhiyun connector->status = vmw_du_connector_detect(connector, true);
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun ret = drm_encoder_init(dev, encoder, &vmw_screen_object_encoder_funcs,
900*4882a593Smuzhiyun DRM_MODE_ENCODER_VIRTUAL, NULL);
901*4882a593Smuzhiyun if (ret) {
902*4882a593Smuzhiyun DRM_ERROR("Failed to initialize encoder\n");
903*4882a593Smuzhiyun goto err_free_connector;
904*4882a593Smuzhiyun }
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun (void) drm_connector_attach_encoder(connector, encoder);
907*4882a593Smuzhiyun encoder->possible_crtcs = (1 << unit);
908*4882a593Smuzhiyun encoder->possible_clones = 0;
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun ret = drm_connector_register(connector);
911*4882a593Smuzhiyun if (ret) {
912*4882a593Smuzhiyun DRM_ERROR("Failed to register connector\n");
913*4882a593Smuzhiyun goto err_free_encoder;
914*4882a593Smuzhiyun }
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun ret = drm_crtc_init_with_planes(dev, crtc, &sou->base.primary,
917*4882a593Smuzhiyun &sou->base.cursor,
918*4882a593Smuzhiyun &vmw_screen_object_crtc_funcs, NULL);
919*4882a593Smuzhiyun if (ret) {
920*4882a593Smuzhiyun DRM_ERROR("Failed to initialize CRTC\n");
921*4882a593Smuzhiyun goto err_free_unregister;
922*4882a593Smuzhiyun }
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun drm_crtc_helper_add(crtc, &vmw_sou_crtc_helper_funcs);
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun drm_mode_crtc_set_gamma_size(crtc, 256);
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun drm_object_attach_property(&connector->base,
929*4882a593Smuzhiyun dev_priv->hotplug_mode_update_property, 1);
930*4882a593Smuzhiyun drm_object_attach_property(&connector->base,
931*4882a593Smuzhiyun dev->mode_config.suggested_x_property, 0);
932*4882a593Smuzhiyun drm_object_attach_property(&connector->base,
933*4882a593Smuzhiyun dev->mode_config.suggested_y_property, 0);
934*4882a593Smuzhiyun return 0;
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun err_free_unregister:
937*4882a593Smuzhiyun drm_connector_unregister(connector);
938*4882a593Smuzhiyun err_free_encoder:
939*4882a593Smuzhiyun drm_encoder_cleanup(encoder);
940*4882a593Smuzhiyun err_free_connector:
941*4882a593Smuzhiyun drm_connector_cleanup(connector);
942*4882a593Smuzhiyun err_free:
943*4882a593Smuzhiyun kfree(sou);
944*4882a593Smuzhiyun return ret;
945*4882a593Smuzhiyun }
946*4882a593Smuzhiyun
vmw_kms_sou_init_display(struct vmw_private * dev_priv)947*4882a593Smuzhiyun int vmw_kms_sou_init_display(struct vmw_private *dev_priv)
948*4882a593Smuzhiyun {
949*4882a593Smuzhiyun struct drm_device *dev = dev_priv->dev;
950*4882a593Smuzhiyun int i, ret;
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun /* Screen objects won't work if GMR's aren't available */
953*4882a593Smuzhiyun if (!dev_priv->has_gmr)
954*4882a593Smuzhiyun return -ENOSYS;
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun if (!(dev_priv->capabilities & SVGA_CAP_SCREEN_OBJECT_2)) {
957*4882a593Smuzhiyun DRM_INFO("Not using screen objects,"
958*4882a593Smuzhiyun " missing cap SCREEN_OBJECT_2\n");
959*4882a593Smuzhiyun return -ENOSYS;
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun ret = -ENOMEM;
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS);
965*4882a593Smuzhiyun if (unlikely(ret != 0))
966*4882a593Smuzhiyun return ret;
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun for (i = 0; i < VMWGFX_NUM_DISPLAY_UNITS; ++i)
969*4882a593Smuzhiyun vmw_sou_init(dev_priv, i);
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun dev_priv->active_display_unit = vmw_du_screen_object;
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun drm_mode_config_reset(dev);
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun DRM_INFO("Screen Objects Display Unit initialized\n");
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun return 0;
978*4882a593Smuzhiyun }
979*4882a593Smuzhiyun
do_bo_define_gmrfb(struct vmw_private * dev_priv,struct vmw_framebuffer * framebuffer)980*4882a593Smuzhiyun static int do_bo_define_gmrfb(struct vmw_private *dev_priv,
981*4882a593Smuzhiyun struct vmw_framebuffer *framebuffer)
982*4882a593Smuzhiyun {
983*4882a593Smuzhiyun struct vmw_buffer_object *buf =
984*4882a593Smuzhiyun container_of(framebuffer, struct vmw_framebuffer_bo,
985*4882a593Smuzhiyun base)->buffer;
986*4882a593Smuzhiyun int depth = framebuffer->base.format->depth;
987*4882a593Smuzhiyun struct {
988*4882a593Smuzhiyun uint32_t header;
989*4882a593Smuzhiyun SVGAFifoCmdDefineGMRFB body;
990*4882a593Smuzhiyun } *cmd;
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun /* Emulate RGBA support, contrary to svga_reg.h this is not
993*4882a593Smuzhiyun * supported by hosts. This is only a problem if we are reading
994*4882a593Smuzhiyun * this value later and expecting what we uploaded back.
995*4882a593Smuzhiyun */
996*4882a593Smuzhiyun if (depth == 32)
997*4882a593Smuzhiyun depth = 24;
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
1000*4882a593Smuzhiyun if (!cmd)
1001*4882a593Smuzhiyun return -ENOMEM;
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun cmd->header = SVGA_CMD_DEFINE_GMRFB;
1004*4882a593Smuzhiyun cmd->body.format.bitsPerPixel = framebuffer->base.format->cpp[0] * 8;
1005*4882a593Smuzhiyun cmd->body.format.colorDepth = depth;
1006*4882a593Smuzhiyun cmd->body.format.reserved = 0;
1007*4882a593Smuzhiyun cmd->body.bytesPerLine = framebuffer->base.pitches[0];
1008*4882a593Smuzhiyun /* Buffer is reserved in vram or GMR */
1009*4882a593Smuzhiyun vmw_bo_get_guest_ptr(&buf->base, &cmd->body.ptr);
1010*4882a593Smuzhiyun vmw_fifo_commit(dev_priv, sizeof(*cmd));
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun return 0;
1013*4882a593Smuzhiyun }
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun /**
1016*4882a593Smuzhiyun * vmw_sou_surface_fifo_commit - Callback to fill in and submit a
1017*4882a593Smuzhiyun * blit surface to screen command.
1018*4882a593Smuzhiyun *
1019*4882a593Smuzhiyun * @dirty: The closure structure.
1020*4882a593Smuzhiyun *
1021*4882a593Smuzhiyun * Fills in the missing fields in the command, and translates the cliprects
1022*4882a593Smuzhiyun * to match the destination bounding box encoded.
1023*4882a593Smuzhiyun */
vmw_sou_surface_fifo_commit(struct vmw_kms_dirty * dirty)1024*4882a593Smuzhiyun static void vmw_sou_surface_fifo_commit(struct vmw_kms_dirty *dirty)
1025*4882a593Smuzhiyun {
1026*4882a593Smuzhiyun struct vmw_kms_sou_surface_dirty *sdirty =
1027*4882a593Smuzhiyun container_of(dirty, typeof(*sdirty), base);
1028*4882a593Smuzhiyun struct vmw_kms_sou_dirty_cmd *cmd = dirty->cmd;
1029*4882a593Smuzhiyun s32 trans_x = dirty->unit->crtc.x - sdirty->dst_x;
1030*4882a593Smuzhiyun s32 trans_y = dirty->unit->crtc.y - sdirty->dst_y;
1031*4882a593Smuzhiyun size_t region_size = dirty->num_hits * sizeof(SVGASignedRect);
1032*4882a593Smuzhiyun SVGASignedRect *blit = (SVGASignedRect *) &cmd[1];
1033*4882a593Smuzhiyun int i;
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun if (!dirty->num_hits) {
1036*4882a593Smuzhiyun vmw_fifo_commit(dirty->dev_priv, 0);
1037*4882a593Smuzhiyun return;
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun
1040*4882a593Smuzhiyun cmd->header.id = SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN;
1041*4882a593Smuzhiyun cmd->header.size = sizeof(cmd->body) + region_size;
1042*4882a593Smuzhiyun
1043*4882a593Smuzhiyun /*
1044*4882a593Smuzhiyun * Use the destination bounding box to specify destination - and
1045*4882a593Smuzhiyun * source bounding regions.
1046*4882a593Smuzhiyun */
1047*4882a593Smuzhiyun cmd->body.destRect.left = sdirty->left;
1048*4882a593Smuzhiyun cmd->body.destRect.right = sdirty->right;
1049*4882a593Smuzhiyun cmd->body.destRect.top = sdirty->top;
1050*4882a593Smuzhiyun cmd->body.destRect.bottom = sdirty->bottom;
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun cmd->body.srcRect.left = sdirty->left + trans_x;
1053*4882a593Smuzhiyun cmd->body.srcRect.right = sdirty->right + trans_x;
1054*4882a593Smuzhiyun cmd->body.srcRect.top = sdirty->top + trans_y;
1055*4882a593Smuzhiyun cmd->body.srcRect.bottom = sdirty->bottom + trans_y;
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun cmd->body.srcImage.sid = sdirty->sid;
1058*4882a593Smuzhiyun cmd->body.destScreenId = dirty->unit->unit;
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun /* Blits are relative to the destination rect. Translate. */
1061*4882a593Smuzhiyun for (i = 0; i < dirty->num_hits; ++i, ++blit) {
1062*4882a593Smuzhiyun blit->left -= sdirty->left;
1063*4882a593Smuzhiyun blit->right -= sdirty->left;
1064*4882a593Smuzhiyun blit->top -= sdirty->top;
1065*4882a593Smuzhiyun blit->bottom -= sdirty->top;
1066*4882a593Smuzhiyun }
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun vmw_fifo_commit(dirty->dev_priv, region_size + sizeof(*cmd));
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun sdirty->left = sdirty->top = S32_MAX;
1071*4882a593Smuzhiyun sdirty->right = sdirty->bottom = S32_MIN;
1072*4882a593Smuzhiyun }
1073*4882a593Smuzhiyun
1074*4882a593Smuzhiyun /**
1075*4882a593Smuzhiyun * vmw_sou_surface_clip - Callback to encode a blit surface to screen cliprect.
1076*4882a593Smuzhiyun *
1077*4882a593Smuzhiyun * @dirty: The closure structure
1078*4882a593Smuzhiyun *
1079*4882a593Smuzhiyun * Encodes a SVGASignedRect cliprect and updates the bounding box of the
1080*4882a593Smuzhiyun * BLIT_SURFACE_TO_SCREEN command.
1081*4882a593Smuzhiyun */
vmw_sou_surface_clip(struct vmw_kms_dirty * dirty)1082*4882a593Smuzhiyun static void vmw_sou_surface_clip(struct vmw_kms_dirty *dirty)
1083*4882a593Smuzhiyun {
1084*4882a593Smuzhiyun struct vmw_kms_sou_surface_dirty *sdirty =
1085*4882a593Smuzhiyun container_of(dirty, typeof(*sdirty), base);
1086*4882a593Smuzhiyun struct vmw_kms_sou_dirty_cmd *cmd = dirty->cmd;
1087*4882a593Smuzhiyun SVGASignedRect *blit = (SVGASignedRect *) &cmd[1];
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun /* Destination rect. */
1090*4882a593Smuzhiyun blit += dirty->num_hits;
1091*4882a593Smuzhiyun blit->left = dirty->unit_x1;
1092*4882a593Smuzhiyun blit->top = dirty->unit_y1;
1093*4882a593Smuzhiyun blit->right = dirty->unit_x2;
1094*4882a593Smuzhiyun blit->bottom = dirty->unit_y2;
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun /* Destination bounding box */
1097*4882a593Smuzhiyun sdirty->left = min_t(s32, sdirty->left, dirty->unit_x1);
1098*4882a593Smuzhiyun sdirty->top = min_t(s32, sdirty->top, dirty->unit_y1);
1099*4882a593Smuzhiyun sdirty->right = max_t(s32, sdirty->right, dirty->unit_x2);
1100*4882a593Smuzhiyun sdirty->bottom = max_t(s32, sdirty->bottom, dirty->unit_y2);
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun dirty->num_hits++;
1103*4882a593Smuzhiyun }
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun /**
1106*4882a593Smuzhiyun * vmw_kms_sou_do_surface_dirty - Dirty part of a surface backed framebuffer
1107*4882a593Smuzhiyun *
1108*4882a593Smuzhiyun * @dev_priv: Pointer to the device private structure.
1109*4882a593Smuzhiyun * @framebuffer: Pointer to the surface-buffer backed framebuffer.
1110*4882a593Smuzhiyun * @clips: Array of clip rects. Either @clips or @vclips must be NULL.
1111*4882a593Smuzhiyun * @vclips: Alternate array of clip rects. Either @clips or @vclips must
1112*4882a593Smuzhiyun * be NULL.
1113*4882a593Smuzhiyun * @srf: Pointer to surface to blit from. If NULL, the surface attached
1114*4882a593Smuzhiyun * to @framebuffer will be used.
1115*4882a593Smuzhiyun * @dest_x: X coordinate offset to align @srf with framebuffer coordinates.
1116*4882a593Smuzhiyun * @dest_y: Y coordinate offset to align @srf with framebuffer coordinates.
1117*4882a593Smuzhiyun * @num_clips: Number of clip rects in @clips.
1118*4882a593Smuzhiyun * @inc: Increment to use when looping over @clips.
1119*4882a593Smuzhiyun * @out_fence: If non-NULL, will return a ref-counted pointer to a
1120*4882a593Smuzhiyun * struct vmw_fence_obj. The returned fence pointer may be NULL in which
1121*4882a593Smuzhiyun * case the device has already synchronized.
1122*4882a593Smuzhiyun * @crtc: If crtc is passed, perform surface dirty on that crtc only.
1123*4882a593Smuzhiyun *
1124*4882a593Smuzhiyun * Returns 0 on success, negative error code on failure. -ERESTARTSYS if
1125*4882a593Smuzhiyun * interrupted.
1126*4882a593Smuzhiyun */
vmw_kms_sou_do_surface_dirty(struct vmw_private * dev_priv,struct vmw_framebuffer * framebuffer,struct drm_clip_rect * clips,struct drm_vmw_rect * vclips,struct vmw_resource * srf,s32 dest_x,s32 dest_y,unsigned num_clips,int inc,struct vmw_fence_obj ** out_fence,struct drm_crtc * crtc)1127*4882a593Smuzhiyun int vmw_kms_sou_do_surface_dirty(struct vmw_private *dev_priv,
1128*4882a593Smuzhiyun struct vmw_framebuffer *framebuffer,
1129*4882a593Smuzhiyun struct drm_clip_rect *clips,
1130*4882a593Smuzhiyun struct drm_vmw_rect *vclips,
1131*4882a593Smuzhiyun struct vmw_resource *srf,
1132*4882a593Smuzhiyun s32 dest_x,
1133*4882a593Smuzhiyun s32 dest_y,
1134*4882a593Smuzhiyun unsigned num_clips, int inc,
1135*4882a593Smuzhiyun struct vmw_fence_obj **out_fence,
1136*4882a593Smuzhiyun struct drm_crtc *crtc)
1137*4882a593Smuzhiyun {
1138*4882a593Smuzhiyun struct vmw_framebuffer_surface *vfbs =
1139*4882a593Smuzhiyun container_of(framebuffer, typeof(*vfbs), base);
1140*4882a593Smuzhiyun struct vmw_kms_sou_surface_dirty sdirty;
1141*4882a593Smuzhiyun DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
1142*4882a593Smuzhiyun int ret;
1143*4882a593Smuzhiyun
1144*4882a593Smuzhiyun if (!srf)
1145*4882a593Smuzhiyun srf = &vfbs->surface->res;
1146*4882a593Smuzhiyun
1147*4882a593Smuzhiyun ret = vmw_validation_add_resource(&val_ctx, srf, 0, VMW_RES_DIRTY_NONE,
1148*4882a593Smuzhiyun NULL, NULL);
1149*4882a593Smuzhiyun if (ret)
1150*4882a593Smuzhiyun return ret;
1151*4882a593Smuzhiyun
1152*4882a593Smuzhiyun ret = vmw_validation_prepare(&val_ctx, &dev_priv->cmdbuf_mutex, true);
1153*4882a593Smuzhiyun if (ret)
1154*4882a593Smuzhiyun goto out_unref;
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun sdirty.base.fifo_commit = vmw_sou_surface_fifo_commit;
1157*4882a593Smuzhiyun sdirty.base.clip = vmw_sou_surface_clip;
1158*4882a593Smuzhiyun sdirty.base.dev_priv = dev_priv;
1159*4882a593Smuzhiyun sdirty.base.fifo_reserve_size = sizeof(struct vmw_kms_sou_dirty_cmd) +
1160*4882a593Smuzhiyun sizeof(SVGASignedRect) * num_clips;
1161*4882a593Smuzhiyun sdirty.base.crtc = crtc;
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun sdirty.sid = srf->id;
1164*4882a593Smuzhiyun sdirty.left = sdirty.top = S32_MAX;
1165*4882a593Smuzhiyun sdirty.right = sdirty.bottom = S32_MIN;
1166*4882a593Smuzhiyun sdirty.dst_x = dest_x;
1167*4882a593Smuzhiyun sdirty.dst_y = dest_y;
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
1170*4882a593Smuzhiyun dest_x, dest_y, num_clips, inc,
1171*4882a593Smuzhiyun &sdirty.base);
1172*4882a593Smuzhiyun vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence,
1173*4882a593Smuzhiyun NULL);
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun return ret;
1176*4882a593Smuzhiyun
1177*4882a593Smuzhiyun out_unref:
1178*4882a593Smuzhiyun vmw_validation_unref_lists(&val_ctx);
1179*4882a593Smuzhiyun return ret;
1180*4882a593Smuzhiyun }
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun /**
1183*4882a593Smuzhiyun * vmw_sou_bo_fifo_commit - Callback to submit a set of readback clips.
1184*4882a593Smuzhiyun *
1185*4882a593Smuzhiyun * @dirty: The closure structure.
1186*4882a593Smuzhiyun *
1187*4882a593Smuzhiyun * Commits a previously built command buffer of readback clips.
1188*4882a593Smuzhiyun */
vmw_sou_bo_fifo_commit(struct vmw_kms_dirty * dirty)1189*4882a593Smuzhiyun static void vmw_sou_bo_fifo_commit(struct vmw_kms_dirty *dirty)
1190*4882a593Smuzhiyun {
1191*4882a593Smuzhiyun if (!dirty->num_hits) {
1192*4882a593Smuzhiyun vmw_fifo_commit(dirty->dev_priv, 0);
1193*4882a593Smuzhiyun return;
1194*4882a593Smuzhiyun }
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun vmw_fifo_commit(dirty->dev_priv,
1197*4882a593Smuzhiyun sizeof(struct vmw_kms_sou_bo_blit) *
1198*4882a593Smuzhiyun dirty->num_hits);
1199*4882a593Smuzhiyun }
1200*4882a593Smuzhiyun
1201*4882a593Smuzhiyun /**
1202*4882a593Smuzhiyun * vmw_sou_bo_clip - Callback to encode a readback cliprect.
1203*4882a593Smuzhiyun *
1204*4882a593Smuzhiyun * @dirty: The closure structure
1205*4882a593Smuzhiyun *
1206*4882a593Smuzhiyun * Encodes a BLIT_GMRFB_TO_SCREEN cliprect.
1207*4882a593Smuzhiyun */
vmw_sou_bo_clip(struct vmw_kms_dirty * dirty)1208*4882a593Smuzhiyun static void vmw_sou_bo_clip(struct vmw_kms_dirty *dirty)
1209*4882a593Smuzhiyun {
1210*4882a593Smuzhiyun struct vmw_kms_sou_bo_blit *blit = dirty->cmd;
1211*4882a593Smuzhiyun
1212*4882a593Smuzhiyun blit += dirty->num_hits;
1213*4882a593Smuzhiyun blit->header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
1214*4882a593Smuzhiyun blit->body.destScreenId = dirty->unit->unit;
1215*4882a593Smuzhiyun blit->body.srcOrigin.x = dirty->fb_x;
1216*4882a593Smuzhiyun blit->body.srcOrigin.y = dirty->fb_y;
1217*4882a593Smuzhiyun blit->body.destRect.left = dirty->unit_x1;
1218*4882a593Smuzhiyun blit->body.destRect.top = dirty->unit_y1;
1219*4882a593Smuzhiyun blit->body.destRect.right = dirty->unit_x2;
1220*4882a593Smuzhiyun blit->body.destRect.bottom = dirty->unit_y2;
1221*4882a593Smuzhiyun dirty->num_hits++;
1222*4882a593Smuzhiyun }
1223*4882a593Smuzhiyun
1224*4882a593Smuzhiyun /**
1225*4882a593Smuzhiyun * vmw_kms_do_bo_dirty - Dirty part of a buffer-object backed framebuffer
1226*4882a593Smuzhiyun *
1227*4882a593Smuzhiyun * @dev_priv: Pointer to the device private structure.
1228*4882a593Smuzhiyun * @framebuffer: Pointer to the buffer-object backed framebuffer.
1229*4882a593Smuzhiyun * @clips: Array of clip rects.
1230*4882a593Smuzhiyun * @vclips: Alternate array of clip rects. Either @clips or @vclips must
1231*4882a593Smuzhiyun * be NULL.
1232*4882a593Smuzhiyun * @num_clips: Number of clip rects in @clips.
1233*4882a593Smuzhiyun * @increment: Increment to use when looping over @clips.
1234*4882a593Smuzhiyun * @interruptible: Whether to perform waits interruptible if possible.
1235*4882a593Smuzhiyun * @out_fence: If non-NULL, will return a ref-counted pointer to a
1236*4882a593Smuzhiyun * struct vmw_fence_obj. The returned fence pointer may be NULL in which
1237*4882a593Smuzhiyun * case the device has already synchronized.
1238*4882a593Smuzhiyun * @crtc: If crtc is passed, perform bo dirty on that crtc only.
1239*4882a593Smuzhiyun *
1240*4882a593Smuzhiyun * Returns 0 on success, negative error code on failure. -ERESTARTSYS if
1241*4882a593Smuzhiyun * interrupted.
1242*4882a593Smuzhiyun */
vmw_kms_sou_do_bo_dirty(struct vmw_private * dev_priv,struct vmw_framebuffer * framebuffer,struct drm_clip_rect * clips,struct drm_vmw_rect * vclips,unsigned num_clips,int increment,bool interruptible,struct vmw_fence_obj ** out_fence,struct drm_crtc * crtc)1243*4882a593Smuzhiyun int vmw_kms_sou_do_bo_dirty(struct vmw_private *dev_priv,
1244*4882a593Smuzhiyun struct vmw_framebuffer *framebuffer,
1245*4882a593Smuzhiyun struct drm_clip_rect *clips,
1246*4882a593Smuzhiyun struct drm_vmw_rect *vclips,
1247*4882a593Smuzhiyun unsigned num_clips, int increment,
1248*4882a593Smuzhiyun bool interruptible,
1249*4882a593Smuzhiyun struct vmw_fence_obj **out_fence,
1250*4882a593Smuzhiyun struct drm_crtc *crtc)
1251*4882a593Smuzhiyun {
1252*4882a593Smuzhiyun struct vmw_buffer_object *buf =
1253*4882a593Smuzhiyun container_of(framebuffer, struct vmw_framebuffer_bo,
1254*4882a593Smuzhiyun base)->buffer;
1255*4882a593Smuzhiyun struct vmw_kms_dirty dirty;
1256*4882a593Smuzhiyun DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
1257*4882a593Smuzhiyun int ret;
1258*4882a593Smuzhiyun
1259*4882a593Smuzhiyun ret = vmw_validation_add_bo(&val_ctx, buf, false, false);
1260*4882a593Smuzhiyun if (ret)
1261*4882a593Smuzhiyun return ret;
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun ret = vmw_validation_prepare(&val_ctx, NULL, interruptible);
1264*4882a593Smuzhiyun if (ret)
1265*4882a593Smuzhiyun goto out_unref;
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun ret = do_bo_define_gmrfb(dev_priv, framebuffer);
1268*4882a593Smuzhiyun if (unlikely(ret != 0))
1269*4882a593Smuzhiyun goto out_revert;
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun dirty.crtc = crtc;
1272*4882a593Smuzhiyun dirty.fifo_commit = vmw_sou_bo_fifo_commit;
1273*4882a593Smuzhiyun dirty.clip = vmw_sou_bo_clip;
1274*4882a593Smuzhiyun dirty.fifo_reserve_size = sizeof(struct vmw_kms_sou_bo_blit) *
1275*4882a593Smuzhiyun num_clips;
1276*4882a593Smuzhiyun ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
1277*4882a593Smuzhiyun 0, 0, num_clips, increment, &dirty);
1278*4882a593Smuzhiyun vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence,
1279*4882a593Smuzhiyun NULL);
1280*4882a593Smuzhiyun
1281*4882a593Smuzhiyun return ret;
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun out_revert:
1284*4882a593Smuzhiyun vmw_validation_revert(&val_ctx);
1285*4882a593Smuzhiyun out_unref:
1286*4882a593Smuzhiyun vmw_validation_unref_lists(&val_ctx);
1287*4882a593Smuzhiyun
1288*4882a593Smuzhiyun return ret;
1289*4882a593Smuzhiyun }
1290*4882a593Smuzhiyun
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun /**
1293*4882a593Smuzhiyun * vmw_sou_readback_fifo_commit - Callback to submit a set of readback clips.
1294*4882a593Smuzhiyun *
1295*4882a593Smuzhiyun * @dirty: The closure structure.
1296*4882a593Smuzhiyun *
1297*4882a593Smuzhiyun * Commits a previously built command buffer of readback clips.
1298*4882a593Smuzhiyun */
vmw_sou_readback_fifo_commit(struct vmw_kms_dirty * dirty)1299*4882a593Smuzhiyun static void vmw_sou_readback_fifo_commit(struct vmw_kms_dirty *dirty)
1300*4882a593Smuzhiyun {
1301*4882a593Smuzhiyun if (!dirty->num_hits) {
1302*4882a593Smuzhiyun vmw_fifo_commit(dirty->dev_priv, 0);
1303*4882a593Smuzhiyun return;
1304*4882a593Smuzhiyun }
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun vmw_fifo_commit(dirty->dev_priv,
1307*4882a593Smuzhiyun sizeof(struct vmw_kms_sou_readback_blit) *
1308*4882a593Smuzhiyun dirty->num_hits);
1309*4882a593Smuzhiyun }
1310*4882a593Smuzhiyun
1311*4882a593Smuzhiyun /**
1312*4882a593Smuzhiyun * vmw_sou_readback_clip - Callback to encode a readback cliprect.
1313*4882a593Smuzhiyun *
1314*4882a593Smuzhiyun * @dirty: The closure structure
1315*4882a593Smuzhiyun *
1316*4882a593Smuzhiyun * Encodes a BLIT_SCREEN_TO_GMRFB cliprect.
1317*4882a593Smuzhiyun */
vmw_sou_readback_clip(struct vmw_kms_dirty * dirty)1318*4882a593Smuzhiyun static void vmw_sou_readback_clip(struct vmw_kms_dirty *dirty)
1319*4882a593Smuzhiyun {
1320*4882a593Smuzhiyun struct vmw_kms_sou_readback_blit *blit = dirty->cmd;
1321*4882a593Smuzhiyun
1322*4882a593Smuzhiyun blit += dirty->num_hits;
1323*4882a593Smuzhiyun blit->header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
1324*4882a593Smuzhiyun blit->body.srcScreenId = dirty->unit->unit;
1325*4882a593Smuzhiyun blit->body.destOrigin.x = dirty->fb_x;
1326*4882a593Smuzhiyun blit->body.destOrigin.y = dirty->fb_y;
1327*4882a593Smuzhiyun blit->body.srcRect.left = dirty->unit_x1;
1328*4882a593Smuzhiyun blit->body.srcRect.top = dirty->unit_y1;
1329*4882a593Smuzhiyun blit->body.srcRect.right = dirty->unit_x2;
1330*4882a593Smuzhiyun blit->body.srcRect.bottom = dirty->unit_y2;
1331*4882a593Smuzhiyun dirty->num_hits++;
1332*4882a593Smuzhiyun }
1333*4882a593Smuzhiyun
1334*4882a593Smuzhiyun /**
1335*4882a593Smuzhiyun * vmw_kms_sou_readback - Perform a readback from the screen object system to
1336*4882a593Smuzhiyun * a buffer-object backed framebuffer.
1337*4882a593Smuzhiyun *
1338*4882a593Smuzhiyun * @dev_priv: Pointer to the device private structure.
1339*4882a593Smuzhiyun * @file_priv: Pointer to a struct drm_file identifying the caller.
1340*4882a593Smuzhiyun * Must be set to NULL if @user_fence_rep is NULL.
1341*4882a593Smuzhiyun * @vfb: Pointer to the buffer-object backed framebuffer.
1342*4882a593Smuzhiyun * @user_fence_rep: User-space provided structure for fence information.
1343*4882a593Smuzhiyun * Must be set to non-NULL if @file_priv is non-NULL.
1344*4882a593Smuzhiyun * @vclips: Array of clip rects.
1345*4882a593Smuzhiyun * @num_clips: Number of clip rects in @vclips.
1346*4882a593Smuzhiyun * @crtc: If crtc is passed, readback on that crtc only.
1347*4882a593Smuzhiyun *
1348*4882a593Smuzhiyun * Returns 0 on success, negative error code on failure. -ERESTARTSYS if
1349*4882a593Smuzhiyun * interrupted.
1350*4882a593Smuzhiyun */
vmw_kms_sou_readback(struct vmw_private * dev_priv,struct drm_file * file_priv,struct vmw_framebuffer * vfb,struct drm_vmw_fence_rep __user * user_fence_rep,struct drm_vmw_rect * vclips,uint32_t num_clips,struct drm_crtc * crtc)1351*4882a593Smuzhiyun int vmw_kms_sou_readback(struct vmw_private *dev_priv,
1352*4882a593Smuzhiyun struct drm_file *file_priv,
1353*4882a593Smuzhiyun struct vmw_framebuffer *vfb,
1354*4882a593Smuzhiyun struct drm_vmw_fence_rep __user *user_fence_rep,
1355*4882a593Smuzhiyun struct drm_vmw_rect *vclips,
1356*4882a593Smuzhiyun uint32_t num_clips,
1357*4882a593Smuzhiyun struct drm_crtc *crtc)
1358*4882a593Smuzhiyun {
1359*4882a593Smuzhiyun struct vmw_buffer_object *buf =
1360*4882a593Smuzhiyun container_of(vfb, struct vmw_framebuffer_bo, base)->buffer;
1361*4882a593Smuzhiyun struct vmw_kms_dirty dirty;
1362*4882a593Smuzhiyun DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
1363*4882a593Smuzhiyun int ret;
1364*4882a593Smuzhiyun
1365*4882a593Smuzhiyun ret = vmw_validation_add_bo(&val_ctx, buf, false, false);
1366*4882a593Smuzhiyun if (ret)
1367*4882a593Smuzhiyun return ret;
1368*4882a593Smuzhiyun
1369*4882a593Smuzhiyun ret = vmw_validation_prepare(&val_ctx, NULL, true);
1370*4882a593Smuzhiyun if (ret)
1371*4882a593Smuzhiyun goto out_unref;
1372*4882a593Smuzhiyun
1373*4882a593Smuzhiyun ret = do_bo_define_gmrfb(dev_priv, vfb);
1374*4882a593Smuzhiyun if (unlikely(ret != 0))
1375*4882a593Smuzhiyun goto out_revert;
1376*4882a593Smuzhiyun
1377*4882a593Smuzhiyun dirty.crtc = crtc;
1378*4882a593Smuzhiyun dirty.fifo_commit = vmw_sou_readback_fifo_commit;
1379*4882a593Smuzhiyun dirty.clip = vmw_sou_readback_clip;
1380*4882a593Smuzhiyun dirty.fifo_reserve_size = sizeof(struct vmw_kms_sou_readback_blit) *
1381*4882a593Smuzhiyun num_clips;
1382*4882a593Smuzhiyun ret = vmw_kms_helper_dirty(dev_priv, vfb, NULL, vclips,
1383*4882a593Smuzhiyun 0, 0, num_clips, 1, &dirty);
1384*4882a593Smuzhiyun vmw_kms_helper_validation_finish(dev_priv, file_priv, &val_ctx, NULL,
1385*4882a593Smuzhiyun user_fence_rep);
1386*4882a593Smuzhiyun
1387*4882a593Smuzhiyun return ret;
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun out_revert:
1390*4882a593Smuzhiyun vmw_validation_revert(&val_ctx);
1391*4882a593Smuzhiyun out_unref:
1392*4882a593Smuzhiyun vmw_validation_unref_lists(&val_ctx);
1393*4882a593Smuzhiyun
1394*4882a593Smuzhiyun return ret;
1395*4882a593Smuzhiyun }
1396