1 /*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_damage_helper.h>
28 #include <drm/drm_fourcc.h>
29 #include <drm/drm_plane_helper.h>
30
31 #include "virtgpu_drv.h"
32
33 static const uint32_t virtio_gpu_formats[] = {
34 DRM_FORMAT_XRGB8888,
35 DRM_FORMAT_ARGB8888,
36 DRM_FORMAT_BGRX8888,
37 DRM_FORMAT_BGRA8888,
38 DRM_FORMAT_RGBX8888,
39 DRM_FORMAT_RGBA8888,
40 DRM_FORMAT_XBGR8888,
41 DRM_FORMAT_ABGR8888,
42 };
43
44 static const uint32_t virtio_gpu_cursor_formats[] = {
45 DRM_FORMAT_HOST_ARGB8888,
46 };
47
virtio_gpu_translate_format(uint32_t drm_fourcc)48 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
49 {
50 uint32_t format;
51
52 switch (drm_fourcc) {
53 #ifdef __BIG_ENDIAN
54 case DRM_FORMAT_XRGB8888:
55 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
56 break;
57 case DRM_FORMAT_ARGB8888:
58 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
59 break;
60 case DRM_FORMAT_BGRX8888:
61 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
62 break;
63 case DRM_FORMAT_BGRA8888:
64 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
65 break;
66 case DRM_FORMAT_RGBX8888:
67 format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM;
68 break;
69 case DRM_FORMAT_RGBA8888:
70 format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM;
71 break;
72 case DRM_FORMAT_XBGR8888:
73 format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM;
74 break;
75 case DRM_FORMAT_ABGR8888:
76 format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM;
77 break;
78 #else
79 case DRM_FORMAT_XRGB8888:
80 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
81 break;
82 case DRM_FORMAT_ARGB8888:
83 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
84 break;
85 case DRM_FORMAT_BGRX8888:
86 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
87 break;
88 case DRM_FORMAT_BGRA8888:
89 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
90 break;
91 case DRM_FORMAT_RGBX8888:
92 format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM;
93 break;
94 case DRM_FORMAT_RGBA8888:
95 format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM;
96 break;
97 case DRM_FORMAT_XBGR8888:
98 format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM;
99 break;
100 case DRM_FORMAT_ABGR8888:
101 format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM;
102 break;
103 #endif
104 default:
105 /*
106 * This should not happen, we handle everything listed
107 * in virtio_gpu_formats[].
108 */
109 format = 0;
110 break;
111 }
112 WARN_ON(format == 0);
113 return format;
114 }
115
virtio_gpu_plane_destroy(struct drm_plane * plane)116 static void virtio_gpu_plane_destroy(struct drm_plane *plane)
117 {
118 drm_plane_cleanup(plane);
119 kfree(plane);
120 }
121
122 static const struct drm_plane_funcs virtio_gpu_plane_funcs = {
123 .update_plane = drm_atomic_helper_update_plane,
124 .disable_plane = drm_atomic_helper_disable_plane,
125 .destroy = virtio_gpu_plane_destroy,
126 .reset = drm_atomic_helper_plane_reset,
127 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
128 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
129 };
130
virtio_gpu_plane_atomic_check(struct drm_plane * plane,struct drm_plane_state * state)131 static int virtio_gpu_plane_atomic_check(struct drm_plane *plane,
132 struct drm_plane_state *state)
133 {
134 bool is_cursor = plane->type == DRM_PLANE_TYPE_CURSOR;
135 struct drm_crtc_state *crtc_state;
136 int ret;
137
138 if (!state->fb || WARN_ON(!state->crtc))
139 return 0;
140
141 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
142 if (IS_ERR(crtc_state))
143 return PTR_ERR(crtc_state);
144
145 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
146 DRM_PLANE_HELPER_NO_SCALING,
147 DRM_PLANE_HELPER_NO_SCALING,
148 is_cursor, true);
149 return ret;
150 }
151
virtio_gpu_update_dumb_bo(struct virtio_gpu_device * vgdev,struct drm_plane_state * state,struct drm_rect * rect)152 static void virtio_gpu_update_dumb_bo(struct virtio_gpu_device *vgdev,
153 struct drm_plane_state *state,
154 struct drm_rect *rect)
155 {
156 struct virtio_gpu_object *bo =
157 gem_to_virtio_gpu_obj(state->fb->obj[0]);
158 struct virtio_gpu_object_array *objs;
159 uint32_t w = rect->x2 - rect->x1;
160 uint32_t h = rect->y2 - rect->y1;
161 uint32_t x = rect->x1;
162 uint32_t y = rect->y1;
163 uint32_t off = x * state->fb->format->cpp[0] +
164 y * state->fb->pitches[0];
165
166 objs = virtio_gpu_array_alloc(1);
167 if (!objs)
168 return;
169 virtio_gpu_array_add_obj(objs, &bo->base.base);
170
171 virtio_gpu_cmd_transfer_to_host_2d(vgdev, off, w, h, x, y,
172 objs, NULL);
173 }
174
virtio_gpu_primary_plane_update(struct drm_plane * plane,struct drm_plane_state * old_state)175 static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
176 struct drm_plane_state *old_state)
177 {
178 struct drm_device *dev = plane->dev;
179 struct virtio_gpu_device *vgdev = dev->dev_private;
180 struct virtio_gpu_output *output = NULL;
181 struct virtio_gpu_object *bo;
182 struct drm_rect rect;
183
184 if (plane->state->crtc)
185 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
186 if (old_state->crtc)
187 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
188 if (WARN_ON(!output))
189 return;
190
191 if (!plane->state->fb || !output->crtc.state->active) {
192 DRM_DEBUG("nofb\n");
193 virtio_gpu_cmd_set_scanout(vgdev, output->index, 0,
194 plane->state->src_w >> 16,
195 plane->state->src_h >> 16,
196 0, 0);
197 virtio_gpu_notify(vgdev);
198 return;
199 }
200
201 if (!drm_atomic_helper_damage_merged(old_state, plane->state, &rect))
202 return;
203
204 bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]);
205 if (bo->dumb)
206 virtio_gpu_update_dumb_bo(vgdev, plane->state, &rect);
207
208 if (plane->state->fb != old_state->fb ||
209 plane->state->src_w != old_state->src_w ||
210 plane->state->src_h != old_state->src_h ||
211 plane->state->src_x != old_state->src_x ||
212 plane->state->src_y != old_state->src_y ||
213 output->needs_modeset) {
214 output->needs_modeset = false;
215 DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n",
216 bo->hw_res_handle,
217 plane->state->crtc_w, plane->state->crtc_h,
218 plane->state->crtc_x, plane->state->crtc_y,
219 plane->state->src_w >> 16,
220 plane->state->src_h >> 16,
221 plane->state->src_x >> 16,
222 plane->state->src_y >> 16);
223 virtio_gpu_cmd_set_scanout(vgdev, output->index,
224 bo->hw_res_handle,
225 plane->state->src_w >> 16,
226 plane->state->src_h >> 16,
227 plane->state->src_x >> 16,
228 plane->state->src_y >> 16);
229 }
230
231 virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle,
232 rect.x1,
233 rect.y1,
234 rect.x2 - rect.x1,
235 rect.y2 - rect.y1);
236 virtio_gpu_notify(vgdev);
237 }
238
virtio_gpu_cursor_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)239 static int virtio_gpu_cursor_prepare_fb(struct drm_plane *plane,
240 struct drm_plane_state *new_state)
241 {
242 struct drm_device *dev = plane->dev;
243 struct virtio_gpu_device *vgdev = dev->dev_private;
244 struct virtio_gpu_framebuffer *vgfb;
245 struct virtio_gpu_object *bo;
246
247 if (!new_state->fb)
248 return 0;
249
250 vgfb = to_virtio_gpu_framebuffer(new_state->fb);
251 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
252 if (bo && bo->dumb && (plane->state->fb != new_state->fb)) {
253 vgfb->fence = virtio_gpu_fence_alloc(vgdev);
254 if (!vgfb->fence)
255 return -ENOMEM;
256 }
257
258 return 0;
259 }
260
virtio_gpu_cursor_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * state)261 static void virtio_gpu_cursor_cleanup_fb(struct drm_plane *plane,
262 struct drm_plane_state *state)
263 {
264 struct virtio_gpu_framebuffer *vgfb;
265
266 if (!state->fb)
267 return;
268
269 vgfb = to_virtio_gpu_framebuffer(state->fb);
270 if (vgfb->fence) {
271 dma_fence_put(&vgfb->fence->f);
272 vgfb->fence = NULL;
273 }
274 }
275
virtio_gpu_cursor_plane_update(struct drm_plane * plane,struct drm_plane_state * old_state)276 static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
277 struct drm_plane_state *old_state)
278 {
279 struct drm_device *dev = plane->dev;
280 struct virtio_gpu_device *vgdev = dev->dev_private;
281 struct virtio_gpu_output *output = NULL;
282 struct virtio_gpu_framebuffer *vgfb;
283 struct virtio_gpu_object *bo = NULL;
284 uint32_t handle;
285
286 if (plane->state->crtc)
287 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
288 if (old_state->crtc)
289 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
290 if (WARN_ON(!output))
291 return;
292
293 if (plane->state->fb) {
294 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
295 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
296 handle = bo->hw_res_handle;
297 } else {
298 handle = 0;
299 }
300
301 if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
302 /* new cursor -- update & wait */
303 struct virtio_gpu_object_array *objs;
304
305 objs = virtio_gpu_array_alloc(1);
306 if (!objs)
307 return;
308 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
309 virtio_gpu_array_lock_resv(objs);
310 virtio_gpu_cmd_transfer_to_host_2d
311 (vgdev, 0,
312 plane->state->crtc_w,
313 plane->state->crtc_h,
314 0, 0, objs, vgfb->fence);
315 virtio_gpu_notify(vgdev);
316 dma_fence_wait(&vgfb->fence->f, true);
317 dma_fence_put(&vgfb->fence->f);
318 vgfb->fence = NULL;
319 }
320
321 if (plane->state->fb != old_state->fb) {
322 DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle,
323 plane->state->crtc_x,
324 plane->state->crtc_y,
325 plane->state->fb ? plane->state->fb->hot_x : 0,
326 plane->state->fb ? plane->state->fb->hot_y : 0);
327 output->cursor.hdr.type =
328 cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR);
329 output->cursor.resource_id = cpu_to_le32(handle);
330 if (plane->state->fb) {
331 output->cursor.hot_x =
332 cpu_to_le32(plane->state->fb->hot_x);
333 output->cursor.hot_y =
334 cpu_to_le32(plane->state->fb->hot_y);
335 } else {
336 output->cursor.hot_x = cpu_to_le32(0);
337 output->cursor.hot_y = cpu_to_le32(0);
338 }
339 } else {
340 DRM_DEBUG("move +%d+%d\n",
341 plane->state->crtc_x,
342 plane->state->crtc_y);
343 output->cursor.hdr.type =
344 cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR);
345 }
346 output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x);
347 output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y);
348 virtio_gpu_cursor_ping(vgdev, output);
349 }
350
351 static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = {
352 .atomic_check = virtio_gpu_plane_atomic_check,
353 .atomic_update = virtio_gpu_primary_plane_update,
354 };
355
356 static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = {
357 .prepare_fb = virtio_gpu_cursor_prepare_fb,
358 .cleanup_fb = virtio_gpu_cursor_cleanup_fb,
359 .atomic_check = virtio_gpu_plane_atomic_check,
360 .atomic_update = virtio_gpu_cursor_plane_update,
361 };
362
virtio_gpu_plane_init(struct virtio_gpu_device * vgdev,enum drm_plane_type type,int index)363 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
364 enum drm_plane_type type,
365 int index)
366 {
367 struct drm_device *dev = vgdev->ddev;
368 const struct drm_plane_helper_funcs *funcs;
369 struct drm_plane *plane;
370 const uint32_t *formats;
371 int ret, nformats;
372
373 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
374 if (!plane)
375 return ERR_PTR(-ENOMEM);
376
377 if (type == DRM_PLANE_TYPE_CURSOR) {
378 formats = virtio_gpu_cursor_formats;
379 nformats = ARRAY_SIZE(virtio_gpu_cursor_formats);
380 funcs = &virtio_gpu_cursor_helper_funcs;
381 } else {
382 formats = virtio_gpu_formats;
383 nformats = ARRAY_SIZE(virtio_gpu_formats);
384 funcs = &virtio_gpu_primary_helper_funcs;
385 }
386 ret = drm_universal_plane_init(dev, plane, 1 << index,
387 &virtio_gpu_plane_funcs,
388 formats, nformats,
389 NULL, type, NULL);
390 if (ret)
391 goto err_plane_init;
392
393 drm_plane_helper_add(plane, funcs);
394 return plane;
395
396 err_plane_init:
397 kfree(plane);
398 return ERR_PTR(ret);
399 }
400