1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015 Red Hat, Inc.
3*4882a593Smuzhiyun * All Rights Reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors:
6*4882a593Smuzhiyun * Dave Airlie
7*4882a593Smuzhiyun * Alon Levy
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
10*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
11*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
12*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
14*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
17*4882a593Smuzhiyun * all copies or substantial portions of the Software.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <linux/file.h>
29*4882a593Smuzhiyun #include <linux/sync_file.h>
30*4882a593Smuzhiyun #include <linux/uaccess.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #include <drm/drm_file.h>
33*4882a593Smuzhiyun #include <drm/virtgpu_drm.h>
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #include "virtgpu_drv.h"
36*4882a593Smuzhiyun
virtio_gpu_create_context(struct drm_device * dev,struct drm_file * file)37*4882a593Smuzhiyun void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct virtio_gpu_device *vgdev = dev->dev_private;
40*4882a593Smuzhiyun struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
41*4882a593Smuzhiyun char dbgname[TASK_COMM_LEN];
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun mutex_lock(&vfpriv->context_lock);
44*4882a593Smuzhiyun if (vfpriv->context_created)
45*4882a593Smuzhiyun goto out_unlock;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun get_task_comm(dbgname, current);
48*4882a593Smuzhiyun virtio_gpu_cmd_context_create(vgdev, vfpriv->ctx_id,
49*4882a593Smuzhiyun strlen(dbgname), dbgname);
50*4882a593Smuzhiyun vfpriv->context_created = true;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun out_unlock:
53*4882a593Smuzhiyun mutex_unlock(&vfpriv->context_lock);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
virtio_gpu_map_ioctl(struct drm_device * dev,void * data,struct drm_file * file)56*4882a593Smuzhiyun static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
57*4882a593Smuzhiyun struct drm_file *file)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct virtio_gpu_device *vgdev = dev->dev_private;
60*4882a593Smuzhiyun struct drm_virtgpu_map *virtio_gpu_map = data;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun return virtio_gpu_mode_dumb_mmap(file, vgdev->ddev,
63*4882a593Smuzhiyun virtio_gpu_map->handle,
64*4882a593Smuzhiyun &virtio_gpu_map->offset);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /*
68*4882a593Smuzhiyun * Usage of execbuffer:
69*4882a593Smuzhiyun * Relocations need to take into account the full VIRTIO_GPUDrawable size.
70*4882a593Smuzhiyun * However, the command as passed from user space must *not* contain the initial
71*4882a593Smuzhiyun * VIRTIO_GPUReleaseInfo struct (first XXX bytes)
72*4882a593Smuzhiyun */
virtio_gpu_execbuffer_ioctl(struct drm_device * dev,void * data,struct drm_file * file)73*4882a593Smuzhiyun static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
74*4882a593Smuzhiyun struct drm_file *file)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct drm_virtgpu_execbuffer *exbuf = data;
77*4882a593Smuzhiyun struct virtio_gpu_device *vgdev = dev->dev_private;
78*4882a593Smuzhiyun struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
79*4882a593Smuzhiyun struct virtio_gpu_fence *out_fence;
80*4882a593Smuzhiyun int ret;
81*4882a593Smuzhiyun uint32_t *bo_handles = NULL;
82*4882a593Smuzhiyun void __user *user_bo_handles = NULL;
83*4882a593Smuzhiyun struct virtio_gpu_object_array *buflist = NULL;
84*4882a593Smuzhiyun struct sync_file *sync_file;
85*4882a593Smuzhiyun int in_fence_fd = exbuf->fence_fd;
86*4882a593Smuzhiyun int out_fence_fd = -1;
87*4882a593Smuzhiyun void *buf;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (vgdev->has_virgl_3d == false)
90*4882a593Smuzhiyun return -ENOSYS;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if ((exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS))
93*4882a593Smuzhiyun return -EINVAL;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun exbuf->fence_fd = -1;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun virtio_gpu_create_context(dev, file);
98*4882a593Smuzhiyun if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) {
99*4882a593Smuzhiyun struct dma_fence *in_fence;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun in_fence = sync_file_get_fence(in_fence_fd);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (!in_fence)
104*4882a593Smuzhiyun return -EINVAL;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /*
107*4882a593Smuzhiyun * Wait if the fence is from a foreign context, or if the fence
108*4882a593Smuzhiyun * array contains any fence from a foreign context.
109*4882a593Smuzhiyun */
110*4882a593Smuzhiyun ret = 0;
111*4882a593Smuzhiyun if (!dma_fence_match_context(in_fence, vgdev->fence_drv.context))
112*4882a593Smuzhiyun ret = dma_fence_wait(in_fence, true);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun dma_fence_put(in_fence);
115*4882a593Smuzhiyun if (ret)
116*4882a593Smuzhiyun return ret;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) {
120*4882a593Smuzhiyun out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
121*4882a593Smuzhiyun if (out_fence_fd < 0)
122*4882a593Smuzhiyun return out_fence_fd;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun if (exbuf->num_bo_handles) {
126*4882a593Smuzhiyun bo_handles = kvmalloc_array(exbuf->num_bo_handles,
127*4882a593Smuzhiyun sizeof(uint32_t), GFP_KERNEL);
128*4882a593Smuzhiyun if (!bo_handles) {
129*4882a593Smuzhiyun ret = -ENOMEM;
130*4882a593Smuzhiyun goto out_unused_fd;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun user_bo_handles = u64_to_user_ptr(exbuf->bo_handles);
134*4882a593Smuzhiyun if (copy_from_user(bo_handles, user_bo_handles,
135*4882a593Smuzhiyun exbuf->num_bo_handles * sizeof(uint32_t))) {
136*4882a593Smuzhiyun ret = -EFAULT;
137*4882a593Smuzhiyun goto out_unused_fd;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun buflist = virtio_gpu_array_from_handles(file, bo_handles,
141*4882a593Smuzhiyun exbuf->num_bo_handles);
142*4882a593Smuzhiyun if (!buflist) {
143*4882a593Smuzhiyun ret = -ENOENT;
144*4882a593Smuzhiyun goto out_unused_fd;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun kvfree(bo_handles);
147*4882a593Smuzhiyun bo_handles = NULL;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun buf = vmemdup_user(u64_to_user_ptr(exbuf->command), exbuf->size);
151*4882a593Smuzhiyun if (IS_ERR(buf)) {
152*4882a593Smuzhiyun ret = PTR_ERR(buf);
153*4882a593Smuzhiyun goto out_unused_fd;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun if (buflist) {
157*4882a593Smuzhiyun ret = virtio_gpu_array_lock_resv(buflist);
158*4882a593Smuzhiyun if (ret)
159*4882a593Smuzhiyun goto out_memdup;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun out_fence = virtio_gpu_fence_alloc(vgdev);
163*4882a593Smuzhiyun if(!out_fence) {
164*4882a593Smuzhiyun ret = -ENOMEM;
165*4882a593Smuzhiyun goto out_unresv;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun if (out_fence_fd >= 0) {
169*4882a593Smuzhiyun sync_file = sync_file_create(&out_fence->f);
170*4882a593Smuzhiyun if (!sync_file) {
171*4882a593Smuzhiyun dma_fence_put(&out_fence->f);
172*4882a593Smuzhiyun ret = -ENOMEM;
173*4882a593Smuzhiyun goto out_memdup;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun exbuf->fence_fd = out_fence_fd;
177*4882a593Smuzhiyun fd_install(out_fence_fd, sync_file->file);
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
181*4882a593Smuzhiyun vfpriv->ctx_id, buflist, out_fence);
182*4882a593Smuzhiyun dma_fence_put(&out_fence->f);
183*4882a593Smuzhiyun virtio_gpu_notify(vgdev);
184*4882a593Smuzhiyun return 0;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun out_unresv:
187*4882a593Smuzhiyun if (buflist)
188*4882a593Smuzhiyun virtio_gpu_array_unlock_resv(buflist);
189*4882a593Smuzhiyun out_memdup:
190*4882a593Smuzhiyun kvfree(buf);
191*4882a593Smuzhiyun out_unused_fd:
192*4882a593Smuzhiyun kvfree(bo_handles);
193*4882a593Smuzhiyun if (buflist)
194*4882a593Smuzhiyun virtio_gpu_array_put_free(buflist);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun if (out_fence_fd >= 0)
197*4882a593Smuzhiyun put_unused_fd(out_fence_fd);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun return ret;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
virtio_gpu_getparam_ioctl(struct drm_device * dev,void * data,struct drm_file * file)202*4882a593Smuzhiyun static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
203*4882a593Smuzhiyun struct drm_file *file)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun struct virtio_gpu_device *vgdev = dev->dev_private;
206*4882a593Smuzhiyun struct drm_virtgpu_getparam *param = data;
207*4882a593Smuzhiyun int value;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun switch (param->param) {
210*4882a593Smuzhiyun case VIRTGPU_PARAM_3D_FEATURES:
211*4882a593Smuzhiyun value = vgdev->has_virgl_3d == true ? 1 : 0;
212*4882a593Smuzhiyun break;
213*4882a593Smuzhiyun case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
214*4882a593Smuzhiyun value = 1;
215*4882a593Smuzhiyun break;
216*4882a593Smuzhiyun default:
217*4882a593Smuzhiyun return -EINVAL;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun if (copy_to_user(u64_to_user_ptr(param->value), &value, sizeof(int)))
220*4882a593Smuzhiyun return -EFAULT;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun return 0;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
virtio_gpu_resource_create_ioctl(struct drm_device * dev,void * data,struct drm_file * file)225*4882a593Smuzhiyun static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
226*4882a593Smuzhiyun struct drm_file *file)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun struct virtio_gpu_device *vgdev = dev->dev_private;
229*4882a593Smuzhiyun struct drm_virtgpu_resource_create *rc = data;
230*4882a593Smuzhiyun struct virtio_gpu_fence *fence;
231*4882a593Smuzhiyun int ret;
232*4882a593Smuzhiyun struct virtio_gpu_object *qobj;
233*4882a593Smuzhiyun struct drm_gem_object *obj;
234*4882a593Smuzhiyun uint32_t handle = 0;
235*4882a593Smuzhiyun struct virtio_gpu_object_params params = { 0 };
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun if (vgdev->has_virgl_3d) {
238*4882a593Smuzhiyun virtio_gpu_create_context(dev, file);
239*4882a593Smuzhiyun params.virgl = true;
240*4882a593Smuzhiyun params.target = rc->target;
241*4882a593Smuzhiyun params.bind = rc->bind;
242*4882a593Smuzhiyun params.depth = rc->depth;
243*4882a593Smuzhiyun params.array_size = rc->array_size;
244*4882a593Smuzhiyun params.last_level = rc->last_level;
245*4882a593Smuzhiyun params.nr_samples = rc->nr_samples;
246*4882a593Smuzhiyun params.flags = rc->flags;
247*4882a593Smuzhiyun } else {
248*4882a593Smuzhiyun if (rc->depth > 1)
249*4882a593Smuzhiyun return -EINVAL;
250*4882a593Smuzhiyun if (rc->nr_samples > 1)
251*4882a593Smuzhiyun return -EINVAL;
252*4882a593Smuzhiyun if (rc->last_level > 1)
253*4882a593Smuzhiyun return -EINVAL;
254*4882a593Smuzhiyun if (rc->target != 2)
255*4882a593Smuzhiyun return -EINVAL;
256*4882a593Smuzhiyun if (rc->array_size > 1)
257*4882a593Smuzhiyun return -EINVAL;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun params.format = rc->format;
261*4882a593Smuzhiyun params.width = rc->width;
262*4882a593Smuzhiyun params.height = rc->height;
263*4882a593Smuzhiyun params.size = rc->size;
264*4882a593Smuzhiyun /* allocate a single page size object */
265*4882a593Smuzhiyun if (params.size == 0)
266*4882a593Smuzhiyun params.size = PAGE_SIZE;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun fence = virtio_gpu_fence_alloc(vgdev);
269*4882a593Smuzhiyun if (!fence)
270*4882a593Smuzhiyun return -ENOMEM;
271*4882a593Smuzhiyun ret = virtio_gpu_object_create(vgdev, ¶ms, &qobj, fence);
272*4882a593Smuzhiyun dma_fence_put(&fence->f);
273*4882a593Smuzhiyun if (ret < 0)
274*4882a593Smuzhiyun return ret;
275*4882a593Smuzhiyun obj = &qobj->base.base;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun ret = drm_gem_handle_create(file, obj, &handle);
278*4882a593Smuzhiyun if (ret) {
279*4882a593Smuzhiyun drm_gem_object_release(obj);
280*4882a593Smuzhiyun return ret;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun drm_gem_object_put(obj);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */
285*4882a593Smuzhiyun rc->bo_handle = handle;
286*4882a593Smuzhiyun return 0;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
virtio_gpu_resource_info_ioctl(struct drm_device * dev,void * data,struct drm_file * file)289*4882a593Smuzhiyun static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
290*4882a593Smuzhiyun struct drm_file *file)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun struct drm_virtgpu_resource_info *ri = data;
293*4882a593Smuzhiyun struct drm_gem_object *gobj = NULL;
294*4882a593Smuzhiyun struct virtio_gpu_object *qobj = NULL;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun gobj = drm_gem_object_lookup(file, ri->bo_handle);
297*4882a593Smuzhiyun if (gobj == NULL)
298*4882a593Smuzhiyun return -ENOENT;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun qobj = gem_to_virtio_gpu_obj(gobj);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun ri->size = qobj->base.base.size;
303*4882a593Smuzhiyun ri->res_handle = qobj->hw_res_handle;
304*4882a593Smuzhiyun drm_gem_object_put(gobj);
305*4882a593Smuzhiyun return 0;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
virtio_gpu_transfer_from_host_ioctl(struct drm_device * dev,void * data,struct drm_file * file)308*4882a593Smuzhiyun static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
309*4882a593Smuzhiyun void *data,
310*4882a593Smuzhiyun struct drm_file *file)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun struct virtio_gpu_device *vgdev = dev->dev_private;
313*4882a593Smuzhiyun struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
314*4882a593Smuzhiyun struct drm_virtgpu_3d_transfer_from_host *args = data;
315*4882a593Smuzhiyun struct virtio_gpu_object_array *objs;
316*4882a593Smuzhiyun struct virtio_gpu_fence *fence;
317*4882a593Smuzhiyun int ret;
318*4882a593Smuzhiyun u32 offset = args->offset;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun if (vgdev->has_virgl_3d == false)
321*4882a593Smuzhiyun return -ENOSYS;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun virtio_gpu_create_context(dev, file);
324*4882a593Smuzhiyun objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
325*4882a593Smuzhiyun if (objs == NULL)
326*4882a593Smuzhiyun return -ENOENT;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun ret = virtio_gpu_array_lock_resv(objs);
329*4882a593Smuzhiyun if (ret != 0)
330*4882a593Smuzhiyun goto err_put_free;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun fence = virtio_gpu_fence_alloc(vgdev);
333*4882a593Smuzhiyun if (!fence) {
334*4882a593Smuzhiyun ret = -ENOMEM;
335*4882a593Smuzhiyun goto err_unlock;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun virtio_gpu_cmd_transfer_from_host_3d
338*4882a593Smuzhiyun (vgdev, vfpriv->ctx_id, offset, args->level,
339*4882a593Smuzhiyun &args->box, objs, fence);
340*4882a593Smuzhiyun dma_fence_put(&fence->f);
341*4882a593Smuzhiyun virtio_gpu_notify(vgdev);
342*4882a593Smuzhiyun return 0;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun err_unlock:
345*4882a593Smuzhiyun virtio_gpu_array_unlock_resv(objs);
346*4882a593Smuzhiyun err_put_free:
347*4882a593Smuzhiyun virtio_gpu_array_put_free(objs);
348*4882a593Smuzhiyun return ret;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
virtio_gpu_transfer_to_host_ioctl(struct drm_device * dev,void * data,struct drm_file * file)351*4882a593Smuzhiyun static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
352*4882a593Smuzhiyun struct drm_file *file)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun struct virtio_gpu_device *vgdev = dev->dev_private;
355*4882a593Smuzhiyun struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
356*4882a593Smuzhiyun struct drm_virtgpu_3d_transfer_to_host *args = data;
357*4882a593Smuzhiyun struct virtio_gpu_object_array *objs;
358*4882a593Smuzhiyun struct virtio_gpu_fence *fence;
359*4882a593Smuzhiyun int ret;
360*4882a593Smuzhiyun u32 offset = args->offset;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
363*4882a593Smuzhiyun if (objs == NULL)
364*4882a593Smuzhiyun return -ENOENT;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun if (!vgdev->has_virgl_3d) {
367*4882a593Smuzhiyun virtio_gpu_cmd_transfer_to_host_2d
368*4882a593Smuzhiyun (vgdev, offset,
369*4882a593Smuzhiyun args->box.w, args->box.h, args->box.x, args->box.y,
370*4882a593Smuzhiyun objs, NULL);
371*4882a593Smuzhiyun } else {
372*4882a593Smuzhiyun virtio_gpu_create_context(dev, file);
373*4882a593Smuzhiyun ret = virtio_gpu_array_lock_resv(objs);
374*4882a593Smuzhiyun if (ret != 0)
375*4882a593Smuzhiyun goto err_put_free;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun ret = -ENOMEM;
378*4882a593Smuzhiyun fence = virtio_gpu_fence_alloc(vgdev);
379*4882a593Smuzhiyun if (!fence)
380*4882a593Smuzhiyun goto err_unlock;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun virtio_gpu_cmd_transfer_to_host_3d
383*4882a593Smuzhiyun (vgdev,
384*4882a593Smuzhiyun vfpriv ? vfpriv->ctx_id : 0, offset,
385*4882a593Smuzhiyun args->level, &args->box, objs, fence);
386*4882a593Smuzhiyun dma_fence_put(&fence->f);
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun virtio_gpu_notify(vgdev);
389*4882a593Smuzhiyun return 0;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun err_unlock:
392*4882a593Smuzhiyun virtio_gpu_array_unlock_resv(objs);
393*4882a593Smuzhiyun err_put_free:
394*4882a593Smuzhiyun virtio_gpu_array_put_free(objs);
395*4882a593Smuzhiyun return ret;
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
virtio_gpu_wait_ioctl(struct drm_device * dev,void * data,struct drm_file * file)398*4882a593Smuzhiyun static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
399*4882a593Smuzhiyun struct drm_file *file)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun struct drm_virtgpu_3d_wait *args = data;
402*4882a593Smuzhiyun struct drm_gem_object *obj;
403*4882a593Smuzhiyun long timeout = 15 * HZ;
404*4882a593Smuzhiyun int ret;
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun obj = drm_gem_object_lookup(file, args->handle);
407*4882a593Smuzhiyun if (obj == NULL)
408*4882a593Smuzhiyun return -ENOENT;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun if (args->flags & VIRTGPU_WAIT_NOWAIT) {
411*4882a593Smuzhiyun ret = dma_resv_test_signaled_rcu(obj->resv, true);
412*4882a593Smuzhiyun } else {
413*4882a593Smuzhiyun ret = dma_resv_wait_timeout_rcu(obj->resv, true, true,
414*4882a593Smuzhiyun timeout);
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun if (ret == 0)
417*4882a593Smuzhiyun ret = -EBUSY;
418*4882a593Smuzhiyun else if (ret > 0)
419*4882a593Smuzhiyun ret = 0;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun drm_gem_object_put(obj);
422*4882a593Smuzhiyun return ret;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
virtio_gpu_get_caps_ioctl(struct drm_device * dev,void * data,struct drm_file * file)425*4882a593Smuzhiyun static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
426*4882a593Smuzhiyun void *data, struct drm_file *file)
427*4882a593Smuzhiyun {
428*4882a593Smuzhiyun struct virtio_gpu_device *vgdev = dev->dev_private;
429*4882a593Smuzhiyun struct drm_virtgpu_get_caps *args = data;
430*4882a593Smuzhiyun unsigned size, host_caps_size;
431*4882a593Smuzhiyun int i;
432*4882a593Smuzhiyun int found_valid = -1;
433*4882a593Smuzhiyun int ret;
434*4882a593Smuzhiyun struct virtio_gpu_drv_cap_cache *cache_ent;
435*4882a593Smuzhiyun void *ptr;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun if (vgdev->num_capsets == 0)
438*4882a593Smuzhiyun return -ENOSYS;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun /* don't allow userspace to pass 0 */
441*4882a593Smuzhiyun if (args->size == 0)
442*4882a593Smuzhiyun return -EINVAL;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun spin_lock(&vgdev->display_info_lock);
445*4882a593Smuzhiyun for (i = 0; i < vgdev->num_capsets; i++) {
446*4882a593Smuzhiyun if (vgdev->capsets[i].id == args->cap_set_id) {
447*4882a593Smuzhiyun if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
448*4882a593Smuzhiyun found_valid = i;
449*4882a593Smuzhiyun break;
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun if (found_valid == -1) {
455*4882a593Smuzhiyun spin_unlock(&vgdev->display_info_lock);
456*4882a593Smuzhiyun return -EINVAL;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun host_caps_size = vgdev->capsets[found_valid].max_size;
460*4882a593Smuzhiyun /* only copy to user the minimum of the host caps size or the guest caps size */
461*4882a593Smuzhiyun size = min(args->size, host_caps_size);
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
464*4882a593Smuzhiyun if (cache_ent->id == args->cap_set_id &&
465*4882a593Smuzhiyun cache_ent->version == args->cap_set_ver) {
466*4882a593Smuzhiyun spin_unlock(&vgdev->display_info_lock);
467*4882a593Smuzhiyun goto copy_exit;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun spin_unlock(&vgdev->display_info_lock);
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun /* not in cache - need to talk to hw */
473*4882a593Smuzhiyun ret = virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
474*4882a593Smuzhiyun &cache_ent);
475*4882a593Smuzhiyun if (ret)
476*4882a593Smuzhiyun return ret;
477*4882a593Smuzhiyun virtio_gpu_notify(vgdev);
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun copy_exit:
480*4882a593Smuzhiyun ret = wait_event_timeout(vgdev->resp_wq,
481*4882a593Smuzhiyun atomic_read(&cache_ent->is_valid), 5 * HZ);
482*4882a593Smuzhiyun if (!ret)
483*4882a593Smuzhiyun return -EBUSY;
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /* is_valid check must proceed before copy of the cache entry. */
486*4882a593Smuzhiyun smp_rmb();
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun ptr = cache_ent->caps_cache;
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun if (copy_to_user(u64_to_user_ptr(args->addr), ptr, size))
491*4882a593Smuzhiyun return -EFAULT;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun return 0;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
497*4882a593Smuzhiyun DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
498*4882a593Smuzhiyun DRM_RENDER_ALLOW),
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
501*4882a593Smuzhiyun DRM_RENDER_ALLOW),
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
504*4882a593Smuzhiyun DRM_RENDER_ALLOW),
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
507*4882a593Smuzhiyun virtio_gpu_resource_create_ioctl,
508*4882a593Smuzhiyun DRM_RENDER_ALLOW),
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
511*4882a593Smuzhiyun DRM_RENDER_ALLOW),
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun /* make transfer async to the main ring? - no sure, can we
514*4882a593Smuzhiyun * thread these in the underlying GL
515*4882a593Smuzhiyun */
516*4882a593Smuzhiyun DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
517*4882a593Smuzhiyun virtio_gpu_transfer_from_host_ioctl,
518*4882a593Smuzhiyun DRM_RENDER_ALLOW),
519*4882a593Smuzhiyun DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
520*4882a593Smuzhiyun virtio_gpu_transfer_to_host_ioctl,
521*4882a593Smuzhiyun DRM_RENDER_ALLOW),
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
524*4882a593Smuzhiyun DRM_RENDER_ALLOW),
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
527*4882a593Smuzhiyun DRM_RENDER_ALLOW),
528*4882a593Smuzhiyun };
529