1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015 Red Hat, Inc.
3*4882a593Smuzhiyun * All Rights Reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors:
6*4882a593Smuzhiyun * Dave Airlie
7*4882a593Smuzhiyun * Alon Levy
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
10*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
11*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
12*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
14*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
17*4882a593Smuzhiyun * all copies or substantial portions of the Software.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
29*4882a593Smuzhiyun #include <drm/drm_damage_helper.h>
30*4882a593Smuzhiyun #include <drm/drm_fourcc.h>
31*4882a593Smuzhiyun #include <drm/drm_gem_framebuffer_helper.h>
32*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
33*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #include "virtgpu_drv.h"
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define XRES_MIN 32
38*4882a593Smuzhiyun #define YRES_MIN 32
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define XRES_DEF 1024
41*4882a593Smuzhiyun #define YRES_DEF 768
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define XRES_MAX 8192
44*4882a593Smuzhiyun #define YRES_MAX 8192
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define drm_connector_to_virtio_gpu_output(x) \
47*4882a593Smuzhiyun container_of(x, struct virtio_gpu_output, conn)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static const struct drm_crtc_funcs virtio_gpu_crtc_funcs = {
50*4882a593Smuzhiyun .set_config = drm_atomic_helper_set_config,
51*4882a593Smuzhiyun .destroy = drm_crtc_cleanup,
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun .page_flip = drm_atomic_helper_page_flip,
54*4882a593Smuzhiyun .reset = drm_atomic_helper_crtc_reset,
55*4882a593Smuzhiyun .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
56*4882a593Smuzhiyun .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct drm_framebuffer_funcs virtio_gpu_fb_funcs = {
60*4882a593Smuzhiyun .create_handle = drm_gem_fb_create_handle,
61*4882a593Smuzhiyun .destroy = drm_gem_fb_destroy,
62*4882a593Smuzhiyun .dirty = drm_atomic_helper_dirtyfb,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun static int
virtio_gpu_framebuffer_init(struct drm_device * dev,struct virtio_gpu_framebuffer * vgfb,const struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)66*4882a593Smuzhiyun virtio_gpu_framebuffer_init(struct drm_device *dev,
67*4882a593Smuzhiyun struct virtio_gpu_framebuffer *vgfb,
68*4882a593Smuzhiyun const struct drm_mode_fb_cmd2 *mode_cmd,
69*4882a593Smuzhiyun struct drm_gem_object *obj)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun int ret;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun vgfb->base.obj[0] = obj;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun drm_helper_mode_fill_fb_struct(dev, &vgfb->base, mode_cmd);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun ret = drm_framebuffer_init(dev, &vgfb->base, &virtio_gpu_fb_funcs);
78*4882a593Smuzhiyun if (ret) {
79*4882a593Smuzhiyun vgfb->base.obj[0] = NULL;
80*4882a593Smuzhiyun return ret;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
virtio_gpu_crtc_mode_set_nofb(struct drm_crtc * crtc)85*4882a593Smuzhiyun static void virtio_gpu_crtc_mode_set_nofb(struct drm_crtc *crtc)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct drm_device *dev = crtc->dev;
88*4882a593Smuzhiyun struct virtio_gpu_device *vgdev = dev->dev_private;
89*4882a593Smuzhiyun struct virtio_gpu_output *output = drm_crtc_to_virtio_gpu_output(crtc);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun virtio_gpu_cmd_set_scanout(vgdev, output->index, 0,
92*4882a593Smuzhiyun crtc->mode.hdisplay,
93*4882a593Smuzhiyun crtc->mode.vdisplay, 0, 0);
94*4882a593Smuzhiyun virtio_gpu_notify(vgdev);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
virtio_gpu_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)97*4882a593Smuzhiyun static void virtio_gpu_crtc_atomic_enable(struct drm_crtc *crtc,
98*4882a593Smuzhiyun struct drm_crtc_state *old_state)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
virtio_gpu_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)102*4882a593Smuzhiyun static void virtio_gpu_crtc_atomic_disable(struct drm_crtc *crtc,
103*4882a593Smuzhiyun struct drm_crtc_state *old_state)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun struct drm_device *dev = crtc->dev;
106*4882a593Smuzhiyun struct virtio_gpu_device *vgdev = dev->dev_private;
107*4882a593Smuzhiyun struct virtio_gpu_output *output = drm_crtc_to_virtio_gpu_output(crtc);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun virtio_gpu_cmd_set_scanout(vgdev, output->index, 0, 0, 0, 0, 0);
110*4882a593Smuzhiyun virtio_gpu_notify(vgdev);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
virtio_gpu_crtc_atomic_check(struct drm_crtc * crtc,struct drm_crtc_state * state)113*4882a593Smuzhiyun static int virtio_gpu_crtc_atomic_check(struct drm_crtc *crtc,
114*4882a593Smuzhiyun struct drm_crtc_state *state)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun return 0;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
virtio_gpu_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_crtc_state * old_state)119*4882a593Smuzhiyun static void virtio_gpu_crtc_atomic_flush(struct drm_crtc *crtc,
120*4882a593Smuzhiyun struct drm_crtc_state *old_state)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun struct virtio_gpu_output *output = drm_crtc_to_virtio_gpu_output(crtc);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /*
125*4882a593Smuzhiyun * virtio-gpu can't do modeset and plane update operations
126*4882a593Smuzhiyun * independent from each other. So the actual modeset happens
127*4882a593Smuzhiyun * in the plane update callback, and here we just check
128*4882a593Smuzhiyun * whenever we must force the modeset.
129*4882a593Smuzhiyun */
130*4882a593Smuzhiyun if (drm_atomic_crtc_needs_modeset(crtc->state)) {
131*4882a593Smuzhiyun output->needs_modeset = true;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun static const struct drm_crtc_helper_funcs virtio_gpu_crtc_helper_funcs = {
136*4882a593Smuzhiyun .mode_set_nofb = virtio_gpu_crtc_mode_set_nofb,
137*4882a593Smuzhiyun .atomic_check = virtio_gpu_crtc_atomic_check,
138*4882a593Smuzhiyun .atomic_flush = virtio_gpu_crtc_atomic_flush,
139*4882a593Smuzhiyun .atomic_enable = virtio_gpu_crtc_atomic_enable,
140*4882a593Smuzhiyun .atomic_disable = virtio_gpu_crtc_atomic_disable,
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun
virtio_gpu_enc_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)143*4882a593Smuzhiyun static void virtio_gpu_enc_mode_set(struct drm_encoder *encoder,
144*4882a593Smuzhiyun struct drm_display_mode *mode,
145*4882a593Smuzhiyun struct drm_display_mode *adjusted_mode)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
virtio_gpu_enc_enable(struct drm_encoder * encoder)149*4882a593Smuzhiyun static void virtio_gpu_enc_enable(struct drm_encoder *encoder)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
virtio_gpu_enc_disable(struct drm_encoder * encoder)153*4882a593Smuzhiyun static void virtio_gpu_enc_disable(struct drm_encoder *encoder)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
virtio_gpu_conn_get_modes(struct drm_connector * connector)157*4882a593Smuzhiyun static int virtio_gpu_conn_get_modes(struct drm_connector *connector)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun struct virtio_gpu_output *output =
160*4882a593Smuzhiyun drm_connector_to_virtio_gpu_output(connector);
161*4882a593Smuzhiyun struct drm_display_mode *mode = NULL;
162*4882a593Smuzhiyun int count, width, height;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun if (output->edid) {
165*4882a593Smuzhiyun count = drm_add_edid_modes(connector, output->edid);
166*4882a593Smuzhiyun if (count)
167*4882a593Smuzhiyun return count;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun width = le32_to_cpu(output->info.r.width);
171*4882a593Smuzhiyun height = le32_to_cpu(output->info.r.height);
172*4882a593Smuzhiyun count = drm_add_modes_noedid(connector, XRES_MAX, YRES_MAX);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun if (width == 0 || height == 0) {
175*4882a593Smuzhiyun drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF);
176*4882a593Smuzhiyun } else {
177*4882a593Smuzhiyun DRM_DEBUG("add mode: %dx%d\n", width, height);
178*4882a593Smuzhiyun mode = drm_cvt_mode(connector->dev, width, height, 60,
179*4882a593Smuzhiyun false, false, false);
180*4882a593Smuzhiyun if (!mode)
181*4882a593Smuzhiyun return count;
182*4882a593Smuzhiyun mode->type |= DRM_MODE_TYPE_PREFERRED;
183*4882a593Smuzhiyun drm_mode_probed_add(connector, mode);
184*4882a593Smuzhiyun count++;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return count;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
virtio_gpu_conn_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)190*4882a593Smuzhiyun static enum drm_mode_status virtio_gpu_conn_mode_valid(struct drm_connector *connector,
191*4882a593Smuzhiyun struct drm_display_mode *mode)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct virtio_gpu_output *output =
194*4882a593Smuzhiyun drm_connector_to_virtio_gpu_output(connector);
195*4882a593Smuzhiyun int width, height;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun width = le32_to_cpu(output->info.r.width);
198*4882a593Smuzhiyun height = le32_to_cpu(output->info.r.height);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun if (!(mode->type & DRM_MODE_TYPE_PREFERRED))
201*4882a593Smuzhiyun return MODE_OK;
202*4882a593Smuzhiyun if (mode->hdisplay == XRES_DEF && mode->vdisplay == YRES_DEF)
203*4882a593Smuzhiyun return MODE_OK;
204*4882a593Smuzhiyun if (mode->hdisplay <= width && mode->hdisplay >= width - 16 &&
205*4882a593Smuzhiyun mode->vdisplay <= height && mode->vdisplay >= height - 16)
206*4882a593Smuzhiyun return MODE_OK;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun DRM_DEBUG("del mode: %dx%d\n", mode->hdisplay, mode->vdisplay);
209*4882a593Smuzhiyun return MODE_BAD;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs virtio_gpu_enc_helper_funcs = {
213*4882a593Smuzhiyun .mode_set = virtio_gpu_enc_mode_set,
214*4882a593Smuzhiyun .enable = virtio_gpu_enc_enable,
215*4882a593Smuzhiyun .disable = virtio_gpu_enc_disable,
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun static const struct drm_connector_helper_funcs virtio_gpu_conn_helper_funcs = {
219*4882a593Smuzhiyun .get_modes = virtio_gpu_conn_get_modes,
220*4882a593Smuzhiyun .mode_valid = virtio_gpu_conn_mode_valid,
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun
virtio_gpu_conn_detect(struct drm_connector * connector,bool force)223*4882a593Smuzhiyun static enum drm_connector_status virtio_gpu_conn_detect(
224*4882a593Smuzhiyun struct drm_connector *connector,
225*4882a593Smuzhiyun bool force)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun struct virtio_gpu_output *output =
228*4882a593Smuzhiyun drm_connector_to_virtio_gpu_output(connector);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun if (output->info.enabled)
231*4882a593Smuzhiyun return connector_status_connected;
232*4882a593Smuzhiyun else
233*4882a593Smuzhiyun return connector_status_disconnected;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
virtio_gpu_conn_destroy(struct drm_connector * connector)236*4882a593Smuzhiyun static void virtio_gpu_conn_destroy(struct drm_connector *connector)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun drm_connector_unregister(connector);
239*4882a593Smuzhiyun drm_connector_cleanup(connector);
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun static const struct drm_connector_funcs virtio_gpu_connector_funcs = {
243*4882a593Smuzhiyun .detect = virtio_gpu_conn_detect,
244*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
245*4882a593Smuzhiyun .destroy = virtio_gpu_conn_destroy,
246*4882a593Smuzhiyun .reset = drm_atomic_helper_connector_reset,
247*4882a593Smuzhiyun .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
248*4882a593Smuzhiyun .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun
vgdev_output_init(struct virtio_gpu_device * vgdev,int index)251*4882a593Smuzhiyun static int vgdev_output_init(struct virtio_gpu_device *vgdev, int index)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun struct drm_device *dev = vgdev->ddev;
254*4882a593Smuzhiyun struct virtio_gpu_output *output = vgdev->outputs + index;
255*4882a593Smuzhiyun struct drm_connector *connector = &output->conn;
256*4882a593Smuzhiyun struct drm_encoder *encoder = &output->enc;
257*4882a593Smuzhiyun struct drm_crtc *crtc = &output->crtc;
258*4882a593Smuzhiyun struct drm_plane *primary, *cursor;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun output->index = index;
261*4882a593Smuzhiyun if (index == 0) {
262*4882a593Smuzhiyun output->info.enabled = cpu_to_le32(true);
263*4882a593Smuzhiyun output->info.r.width = cpu_to_le32(XRES_DEF);
264*4882a593Smuzhiyun output->info.r.height = cpu_to_le32(YRES_DEF);
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun primary = virtio_gpu_plane_init(vgdev, DRM_PLANE_TYPE_PRIMARY, index);
268*4882a593Smuzhiyun if (IS_ERR(primary))
269*4882a593Smuzhiyun return PTR_ERR(primary);
270*4882a593Smuzhiyun cursor = virtio_gpu_plane_init(vgdev, DRM_PLANE_TYPE_CURSOR, index);
271*4882a593Smuzhiyun if (IS_ERR(cursor))
272*4882a593Smuzhiyun return PTR_ERR(cursor);
273*4882a593Smuzhiyun drm_crtc_init_with_planes(dev, crtc, primary, cursor,
274*4882a593Smuzhiyun &virtio_gpu_crtc_funcs, NULL);
275*4882a593Smuzhiyun drm_crtc_helper_add(crtc, &virtio_gpu_crtc_helper_funcs);
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun drm_connector_init(dev, connector, &virtio_gpu_connector_funcs,
278*4882a593Smuzhiyun DRM_MODE_CONNECTOR_VIRTUAL);
279*4882a593Smuzhiyun drm_connector_helper_add(connector, &virtio_gpu_conn_helper_funcs);
280*4882a593Smuzhiyun if (vgdev->has_edid)
281*4882a593Smuzhiyun drm_connector_attach_edid_property(connector);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_VIRTUAL);
284*4882a593Smuzhiyun drm_encoder_helper_add(encoder, &virtio_gpu_enc_helper_funcs);
285*4882a593Smuzhiyun encoder->possible_crtcs = 1 << index;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun drm_connector_attach_encoder(connector, encoder);
288*4882a593Smuzhiyun drm_connector_register(connector);
289*4882a593Smuzhiyun return 0;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun static struct drm_framebuffer *
virtio_gpu_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_mode_fb_cmd2 * mode_cmd)293*4882a593Smuzhiyun virtio_gpu_user_framebuffer_create(struct drm_device *dev,
294*4882a593Smuzhiyun struct drm_file *file_priv,
295*4882a593Smuzhiyun const struct drm_mode_fb_cmd2 *mode_cmd)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun struct drm_gem_object *obj = NULL;
298*4882a593Smuzhiyun struct virtio_gpu_framebuffer *virtio_gpu_fb;
299*4882a593Smuzhiyun int ret;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun /* lookup object associated with res handle */
302*4882a593Smuzhiyun obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
303*4882a593Smuzhiyun if (!obj)
304*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun virtio_gpu_fb = kzalloc(sizeof(*virtio_gpu_fb), GFP_KERNEL);
307*4882a593Smuzhiyun if (virtio_gpu_fb == NULL)
308*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun ret = virtio_gpu_framebuffer_init(dev, virtio_gpu_fb, mode_cmd, obj);
311*4882a593Smuzhiyun if (ret) {
312*4882a593Smuzhiyun kfree(virtio_gpu_fb);
313*4882a593Smuzhiyun drm_gem_object_put(obj);
314*4882a593Smuzhiyun return NULL;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun return &virtio_gpu_fb->base;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun static const struct drm_mode_config_funcs virtio_gpu_mode_funcs = {
321*4882a593Smuzhiyun .fb_create = virtio_gpu_user_framebuffer_create,
322*4882a593Smuzhiyun .atomic_check = drm_atomic_helper_check,
323*4882a593Smuzhiyun .atomic_commit = drm_atomic_helper_commit,
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun
virtio_gpu_modeset_init(struct virtio_gpu_device * vgdev)326*4882a593Smuzhiyun int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun int i, ret;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun ret = drmm_mode_config_init(vgdev->ddev);
331*4882a593Smuzhiyun if (ret)
332*4882a593Smuzhiyun return ret;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun vgdev->ddev->mode_config.funcs = &virtio_gpu_mode_funcs;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun /* modes will be validated against the framebuffer size */
337*4882a593Smuzhiyun vgdev->ddev->mode_config.min_width = XRES_MIN;
338*4882a593Smuzhiyun vgdev->ddev->mode_config.min_height = YRES_MIN;
339*4882a593Smuzhiyun vgdev->ddev->mode_config.max_width = XRES_MAX;
340*4882a593Smuzhiyun vgdev->ddev->mode_config.max_height = YRES_MAX;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun for (i = 0 ; i < vgdev->num_scanouts; ++i)
343*4882a593Smuzhiyun vgdev_output_init(vgdev, i);
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun drm_mode_config_reset(vgdev->ddev);
346*4882a593Smuzhiyun return 0;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
virtio_gpu_modeset_fini(struct virtio_gpu_device * vgdev)349*4882a593Smuzhiyun void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun int i;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun for (i = 0 ; i < vgdev->num_scanouts; ++i)
354*4882a593Smuzhiyun kfree(vgdev->outputs[i].edid);
355*4882a593Smuzhiyun }
356