xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/vc4/vc4_dpi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2016 Broadcom Limited
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun /**
7*4882a593Smuzhiyun  * DOC: VC4 DPI module
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * The VC4 DPI hardware supports MIPI DPI type 4 and Nokia ViSSI
10*4882a593Smuzhiyun  * signals.  On BCM2835, these can be routed out to GPIO0-27 with the
11*4882a593Smuzhiyun  * ALT2 function.
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
15*4882a593Smuzhiyun #include <drm/drm_bridge.h>
16*4882a593Smuzhiyun #include <drm/drm_edid.h>
17*4882a593Smuzhiyun #include <drm/drm_of.h>
18*4882a593Smuzhiyun #include <drm/drm_panel.h>
19*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
20*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
21*4882a593Smuzhiyun #include <linux/clk.h>
22*4882a593Smuzhiyun #include <linux/component.h>
23*4882a593Smuzhiyun #include <linux/of_graph.h>
24*4882a593Smuzhiyun #include <linux/of_platform.h>
25*4882a593Smuzhiyun #include "vc4_drv.h"
26*4882a593Smuzhiyun #include "vc4_regs.h"
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define DPI_C			0x00
29*4882a593Smuzhiyun # define DPI_OUTPUT_ENABLE_MODE		BIT(16)
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /* The order field takes the incoming 24 bit RGB from the pixel valve
32*4882a593Smuzhiyun  * and shuffles the 3 channels.
33*4882a593Smuzhiyun  */
34*4882a593Smuzhiyun # define DPI_ORDER_MASK			VC4_MASK(15, 14)
35*4882a593Smuzhiyun # define DPI_ORDER_SHIFT		14
36*4882a593Smuzhiyun # define DPI_ORDER_RGB			0
37*4882a593Smuzhiyun # define DPI_ORDER_BGR			1
38*4882a593Smuzhiyun # define DPI_ORDER_GRB			2
39*4882a593Smuzhiyun # define DPI_ORDER_BRG			3
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /* The format field takes the ORDER-shuffled pixel valve data and
42*4882a593Smuzhiyun  * formats it onto the output lines.
43*4882a593Smuzhiyun  */
44*4882a593Smuzhiyun # define DPI_FORMAT_MASK		VC4_MASK(13, 11)
45*4882a593Smuzhiyun # define DPI_FORMAT_SHIFT		11
46*4882a593Smuzhiyun /* This define is named in the hardware, but actually just outputs 0. */
47*4882a593Smuzhiyun # define DPI_FORMAT_9BIT_666_RGB	0
48*4882a593Smuzhiyun /* Outputs 00000000rrrrrggggggbbbbb */
49*4882a593Smuzhiyun # define DPI_FORMAT_16BIT_565_RGB_1	1
50*4882a593Smuzhiyun /* Outputs 000rrrrr00gggggg000bbbbb */
51*4882a593Smuzhiyun # define DPI_FORMAT_16BIT_565_RGB_2	2
52*4882a593Smuzhiyun /* Outputs 00rrrrr000gggggg00bbbbb0 */
53*4882a593Smuzhiyun # define DPI_FORMAT_16BIT_565_RGB_3	3
54*4882a593Smuzhiyun /* Outputs 000000rrrrrrggggggbbbbbb */
55*4882a593Smuzhiyun # define DPI_FORMAT_18BIT_666_RGB_1	4
56*4882a593Smuzhiyun /* Outputs 00rrrrrr00gggggg00bbbbbb */
57*4882a593Smuzhiyun # define DPI_FORMAT_18BIT_666_RGB_2	5
58*4882a593Smuzhiyun /* Outputs rrrrrrrrggggggggbbbbbbbb */
59*4882a593Smuzhiyun # define DPI_FORMAT_24BIT_888_RGB	6
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /* Reverses the polarity of the corresponding signal */
62*4882a593Smuzhiyun # define DPI_PIXEL_CLK_INVERT		BIT(10)
63*4882a593Smuzhiyun # define DPI_HSYNC_INVERT		BIT(9)
64*4882a593Smuzhiyun # define DPI_VSYNC_INVERT		BIT(8)
65*4882a593Smuzhiyun # define DPI_OUTPUT_ENABLE_INVERT	BIT(7)
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /* Outputs the signal the falling clock edge instead of rising. */
68*4882a593Smuzhiyun # define DPI_HSYNC_NEGATE		BIT(6)
69*4882a593Smuzhiyun # define DPI_VSYNC_NEGATE		BIT(5)
70*4882a593Smuzhiyun # define DPI_OUTPUT_ENABLE_NEGATE	BIT(4)
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* Disables the signal */
73*4882a593Smuzhiyun # define DPI_HSYNC_DISABLE		BIT(3)
74*4882a593Smuzhiyun # define DPI_VSYNC_DISABLE		BIT(2)
75*4882a593Smuzhiyun # define DPI_OUTPUT_ENABLE_DISABLE	BIT(1)
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun /* Power gate to the device, full reset at 0 -> 1 transition */
78*4882a593Smuzhiyun # define DPI_ENABLE			BIT(0)
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* All other registers besides DPI_C return the ID */
81*4882a593Smuzhiyun #define DPI_ID			0x04
82*4882a593Smuzhiyun # define DPI_ID_VALUE		0x00647069
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /* General DPI hardware state. */
85*4882a593Smuzhiyun struct vc4_dpi {
86*4882a593Smuzhiyun 	struct platform_device *pdev;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	struct drm_encoder *encoder;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	void __iomem *regs;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	struct clk *pixel_clock;
93*4882a593Smuzhiyun 	struct clk *core_clock;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	struct debugfs_regset32 regset;
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define DPI_READ(offset) readl(dpi->regs + (offset))
99*4882a593Smuzhiyun #define DPI_WRITE(offset, val) writel(val, dpi->regs + (offset))
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* VC4 DPI encoder KMS struct */
102*4882a593Smuzhiyun struct vc4_dpi_encoder {
103*4882a593Smuzhiyun 	struct vc4_encoder base;
104*4882a593Smuzhiyun 	struct vc4_dpi *dpi;
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun static inline struct vc4_dpi_encoder *
to_vc4_dpi_encoder(struct drm_encoder * encoder)108*4882a593Smuzhiyun to_vc4_dpi_encoder(struct drm_encoder *encoder)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun 	return container_of(encoder, struct vc4_dpi_encoder, base.base);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun static const struct debugfs_reg32 dpi_regs[] = {
114*4882a593Smuzhiyun 	VC4_REG32(DPI_C),
115*4882a593Smuzhiyun 	VC4_REG32(DPI_ID),
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun 
vc4_dpi_encoder_disable(struct drm_encoder * encoder)118*4882a593Smuzhiyun static void vc4_dpi_encoder_disable(struct drm_encoder *encoder)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun 	struct vc4_dpi_encoder *vc4_encoder = to_vc4_dpi_encoder(encoder);
121*4882a593Smuzhiyun 	struct vc4_dpi *dpi = vc4_encoder->dpi;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	clk_disable_unprepare(dpi->pixel_clock);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
vc4_dpi_encoder_enable(struct drm_encoder * encoder)126*4882a593Smuzhiyun static void vc4_dpi_encoder_enable(struct drm_encoder *encoder)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	struct drm_device *dev = encoder->dev;
129*4882a593Smuzhiyun 	struct drm_display_mode *mode = &encoder->crtc->mode;
130*4882a593Smuzhiyun 	struct vc4_dpi_encoder *vc4_encoder = to_vc4_dpi_encoder(encoder);
131*4882a593Smuzhiyun 	struct vc4_dpi *dpi = vc4_encoder->dpi;
132*4882a593Smuzhiyun 	struct drm_connector_list_iter conn_iter;
133*4882a593Smuzhiyun 	struct drm_connector *connector = NULL, *connector_scan;
134*4882a593Smuzhiyun 	u32 dpi_c = DPI_ENABLE | DPI_OUTPUT_ENABLE_MODE;
135*4882a593Smuzhiyun 	int ret;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	/* Look up the connector attached to DPI so we can get the
138*4882a593Smuzhiyun 	 * bus_format.  Ideally the bridge would tell us the
139*4882a593Smuzhiyun 	 * bus_format we want, but it doesn't yet, so assume that it's
140*4882a593Smuzhiyun 	 * uniform throughout the bridge chain.
141*4882a593Smuzhiyun 	 */
142*4882a593Smuzhiyun 	drm_connector_list_iter_begin(dev, &conn_iter);
143*4882a593Smuzhiyun 	drm_for_each_connector_iter(connector_scan, &conn_iter) {
144*4882a593Smuzhiyun 		if (connector_scan->encoder == encoder) {
145*4882a593Smuzhiyun 			connector = connector_scan;
146*4882a593Smuzhiyun 			break;
147*4882a593Smuzhiyun 		}
148*4882a593Smuzhiyun 	}
149*4882a593Smuzhiyun 	drm_connector_list_iter_end(&conn_iter);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	if (connector && connector->display_info.num_bus_formats) {
152*4882a593Smuzhiyun 		u32 bus_format = connector->display_info.bus_formats[0];
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 		switch (bus_format) {
155*4882a593Smuzhiyun 		case MEDIA_BUS_FMT_RGB888_1X24:
156*4882a593Smuzhiyun 			dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB,
157*4882a593Smuzhiyun 					       DPI_FORMAT);
158*4882a593Smuzhiyun 			break;
159*4882a593Smuzhiyun 		case MEDIA_BUS_FMT_BGR888_1X24:
160*4882a593Smuzhiyun 			dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB,
161*4882a593Smuzhiyun 					       DPI_FORMAT);
162*4882a593Smuzhiyun 			dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);
163*4882a593Smuzhiyun 			break;
164*4882a593Smuzhiyun 		case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
165*4882a593Smuzhiyun 			dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,
166*4882a593Smuzhiyun 					       DPI_FORMAT);
167*4882a593Smuzhiyun 			break;
168*4882a593Smuzhiyun 		case MEDIA_BUS_FMT_RGB666_1X18:
169*4882a593Smuzhiyun 			dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,
170*4882a593Smuzhiyun 					       DPI_FORMAT);
171*4882a593Smuzhiyun 			break;
172*4882a593Smuzhiyun 		case MEDIA_BUS_FMT_RGB565_1X16:
173*4882a593Smuzhiyun 			dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3,
174*4882a593Smuzhiyun 					       DPI_FORMAT);
175*4882a593Smuzhiyun 			break;
176*4882a593Smuzhiyun 		default:
177*4882a593Smuzhiyun 			DRM_ERROR("Unknown media bus format %d\n", bus_format);
178*4882a593Smuzhiyun 			break;
179*4882a593Smuzhiyun 		}
180*4882a593Smuzhiyun 	} else {
181*4882a593Smuzhiyun 		/* Default to 24bit if no connector found. */
182*4882a593Smuzhiyun 		dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT);
183*4882a593Smuzhiyun 	}
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
186*4882a593Smuzhiyun 		dpi_c |= DPI_HSYNC_INVERT;
187*4882a593Smuzhiyun 	else if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
188*4882a593Smuzhiyun 		dpi_c |= DPI_HSYNC_DISABLE;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
191*4882a593Smuzhiyun 		dpi_c |= DPI_VSYNC_INVERT;
192*4882a593Smuzhiyun 	else if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
193*4882a593Smuzhiyun 		dpi_c |= DPI_VSYNC_DISABLE;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	DPI_WRITE(DPI_C, dpi_c);
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	ret = clk_set_rate(dpi->pixel_clock, mode->clock * 1000);
198*4882a593Smuzhiyun 	if (ret)
199*4882a593Smuzhiyun 		DRM_ERROR("Failed to set clock rate: %d\n", ret);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	ret = clk_prepare_enable(dpi->pixel_clock);
202*4882a593Smuzhiyun 	if (ret)
203*4882a593Smuzhiyun 		DRM_ERROR("Failed to set clock rate: %d\n", ret);
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun 
vc4_dpi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)206*4882a593Smuzhiyun static enum drm_mode_status vc4_dpi_encoder_mode_valid(struct drm_encoder *encoder,
207*4882a593Smuzhiyun 						       const struct drm_display_mode *mode)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
210*4882a593Smuzhiyun 		return MODE_NO_INTERLACE;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	return MODE_OK;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs vc4_dpi_encoder_helper_funcs = {
216*4882a593Smuzhiyun 	.disable = vc4_dpi_encoder_disable,
217*4882a593Smuzhiyun 	.enable = vc4_dpi_encoder_enable,
218*4882a593Smuzhiyun 	.mode_valid = vc4_dpi_encoder_mode_valid,
219*4882a593Smuzhiyun };
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun static const struct of_device_id vc4_dpi_dt_match[] = {
222*4882a593Smuzhiyun 	{ .compatible = "brcm,bcm2835-dpi", .data = NULL },
223*4882a593Smuzhiyun 	{}
224*4882a593Smuzhiyun };
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun /* Sets up the next link in the display chain, whether it's a panel or
227*4882a593Smuzhiyun  * a bridge.
228*4882a593Smuzhiyun  */
vc4_dpi_init_bridge(struct vc4_dpi * dpi)229*4882a593Smuzhiyun static int vc4_dpi_init_bridge(struct vc4_dpi *dpi)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun 	struct device *dev = &dpi->pdev->dev;
232*4882a593Smuzhiyun 	struct drm_panel *panel;
233*4882a593Smuzhiyun 	struct drm_bridge *bridge;
234*4882a593Smuzhiyun 	int ret;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
237*4882a593Smuzhiyun 					  &panel, &bridge);
238*4882a593Smuzhiyun 	if (ret) {
239*4882a593Smuzhiyun 		/* If nothing was connected in the DT, that's not an
240*4882a593Smuzhiyun 		 * error.
241*4882a593Smuzhiyun 		 */
242*4882a593Smuzhiyun 		if (ret == -ENODEV)
243*4882a593Smuzhiyun 			return 0;
244*4882a593Smuzhiyun 		else
245*4882a593Smuzhiyun 			return ret;
246*4882a593Smuzhiyun 	}
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	if (panel)
249*4882a593Smuzhiyun 		bridge = drm_panel_bridge_add_typed(panel,
250*4882a593Smuzhiyun 						    DRM_MODE_CONNECTOR_DPI);
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	return drm_bridge_attach(dpi->encoder, bridge, NULL, 0);
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun 
vc4_dpi_bind(struct device * dev,struct device * master,void * data)255*4882a593Smuzhiyun static int vc4_dpi_bind(struct device *dev, struct device *master, void *data)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun 	struct platform_device *pdev = to_platform_device(dev);
258*4882a593Smuzhiyun 	struct drm_device *drm = dev_get_drvdata(master);
259*4882a593Smuzhiyun 	struct vc4_dev *vc4 = to_vc4_dev(drm);
260*4882a593Smuzhiyun 	struct vc4_dpi *dpi;
261*4882a593Smuzhiyun 	struct vc4_dpi_encoder *vc4_dpi_encoder;
262*4882a593Smuzhiyun 	int ret;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
265*4882a593Smuzhiyun 	if (!dpi)
266*4882a593Smuzhiyun 		return -ENOMEM;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	vc4_dpi_encoder = devm_kzalloc(dev, sizeof(*vc4_dpi_encoder),
269*4882a593Smuzhiyun 				       GFP_KERNEL);
270*4882a593Smuzhiyun 	if (!vc4_dpi_encoder)
271*4882a593Smuzhiyun 		return -ENOMEM;
272*4882a593Smuzhiyun 	vc4_dpi_encoder->base.type = VC4_ENCODER_TYPE_DPI;
273*4882a593Smuzhiyun 	vc4_dpi_encoder->dpi = dpi;
274*4882a593Smuzhiyun 	dpi->encoder = &vc4_dpi_encoder->base.base;
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	dpi->pdev = pdev;
277*4882a593Smuzhiyun 	dpi->regs = vc4_ioremap_regs(pdev, 0);
278*4882a593Smuzhiyun 	if (IS_ERR(dpi->regs))
279*4882a593Smuzhiyun 		return PTR_ERR(dpi->regs);
280*4882a593Smuzhiyun 	dpi->regset.base = dpi->regs;
281*4882a593Smuzhiyun 	dpi->regset.regs = dpi_regs;
282*4882a593Smuzhiyun 	dpi->regset.nregs = ARRAY_SIZE(dpi_regs);
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	if (DPI_READ(DPI_ID) != DPI_ID_VALUE) {
285*4882a593Smuzhiyun 		dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
286*4882a593Smuzhiyun 			DPI_READ(DPI_ID), DPI_ID_VALUE);
287*4882a593Smuzhiyun 		return -ENODEV;
288*4882a593Smuzhiyun 	}
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	dpi->core_clock = devm_clk_get(dev, "core");
291*4882a593Smuzhiyun 	if (IS_ERR(dpi->core_clock)) {
292*4882a593Smuzhiyun 		ret = PTR_ERR(dpi->core_clock);
293*4882a593Smuzhiyun 		if (ret != -EPROBE_DEFER)
294*4882a593Smuzhiyun 			DRM_ERROR("Failed to get core clock: %d\n", ret);
295*4882a593Smuzhiyun 		return ret;
296*4882a593Smuzhiyun 	}
297*4882a593Smuzhiyun 	dpi->pixel_clock = devm_clk_get(dev, "pixel");
298*4882a593Smuzhiyun 	if (IS_ERR(dpi->pixel_clock)) {
299*4882a593Smuzhiyun 		ret = PTR_ERR(dpi->pixel_clock);
300*4882a593Smuzhiyun 		if (ret != -EPROBE_DEFER)
301*4882a593Smuzhiyun 			DRM_ERROR("Failed to get pixel clock: %d\n", ret);
302*4882a593Smuzhiyun 		return ret;
303*4882a593Smuzhiyun 	}
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	ret = clk_prepare_enable(dpi->core_clock);
306*4882a593Smuzhiyun 	if (ret)
307*4882a593Smuzhiyun 		DRM_ERROR("Failed to turn on core clock: %d\n", ret);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	drm_simple_encoder_init(drm, dpi->encoder, DRM_MODE_ENCODER_DPI);
310*4882a593Smuzhiyun 	drm_encoder_helper_add(dpi->encoder, &vc4_dpi_encoder_helper_funcs);
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	ret = vc4_dpi_init_bridge(dpi);
313*4882a593Smuzhiyun 	if (ret)
314*4882a593Smuzhiyun 		goto err_destroy_encoder;
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	dev_set_drvdata(dev, dpi);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	vc4->dpi = dpi;
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	vc4_debugfs_add_regset32(drm, "dpi_regs", &dpi->regset);
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	return 0;
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun err_destroy_encoder:
325*4882a593Smuzhiyun 	drm_encoder_cleanup(dpi->encoder);
326*4882a593Smuzhiyun 	clk_disable_unprepare(dpi->core_clock);
327*4882a593Smuzhiyun 	return ret;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun 
vc4_dpi_unbind(struct device * dev,struct device * master,void * data)330*4882a593Smuzhiyun static void vc4_dpi_unbind(struct device *dev, struct device *master,
331*4882a593Smuzhiyun 			   void *data)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun 	struct drm_device *drm = dev_get_drvdata(master);
334*4882a593Smuzhiyun 	struct vc4_dev *vc4 = to_vc4_dev(drm);
335*4882a593Smuzhiyun 	struct vc4_dpi *dpi = dev_get_drvdata(dev);
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	drm_of_panel_bridge_remove(dev->of_node, 0, 0);
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	drm_encoder_cleanup(dpi->encoder);
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	clk_disable_unprepare(dpi->core_clock);
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	vc4->dpi = NULL;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun static const struct component_ops vc4_dpi_ops = {
347*4882a593Smuzhiyun 	.bind   = vc4_dpi_bind,
348*4882a593Smuzhiyun 	.unbind = vc4_dpi_unbind,
349*4882a593Smuzhiyun };
350*4882a593Smuzhiyun 
vc4_dpi_dev_probe(struct platform_device * pdev)351*4882a593Smuzhiyun static int vc4_dpi_dev_probe(struct platform_device *pdev)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	return component_add(&pdev->dev, &vc4_dpi_ops);
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun 
vc4_dpi_dev_remove(struct platform_device * pdev)356*4882a593Smuzhiyun static int vc4_dpi_dev_remove(struct platform_device *pdev)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	component_del(&pdev->dev, &vc4_dpi_ops);
359*4882a593Smuzhiyun 	return 0;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun struct platform_driver vc4_dpi_driver = {
363*4882a593Smuzhiyun 	.probe = vc4_dpi_dev_probe,
364*4882a593Smuzhiyun 	.remove = vc4_dpi_dev_remove,
365*4882a593Smuzhiyun 	.driver = {
366*4882a593Smuzhiyun 		.name = "vc4_dpi",
367*4882a593Smuzhiyun 		.of_match_table = vc4_dpi_dt_match,
368*4882a593Smuzhiyun 	},
369*4882a593Smuzhiyun };
370