xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/tiny/repaper.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * DRM driver for Pervasive Displays RePaper branded e-ink panels
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2013-2017 Pervasive Displays, Inc.
6*4882a593Smuzhiyun  * Copyright 2017 Noralf Trønnes
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * The driver supports:
9*4882a593Smuzhiyun  * Material Film: Aurora Mb (V231)
10*4882a593Smuzhiyun  * Driver IC: G2 (eTC)
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * The controller code was taken from the userspace driver:
13*4882a593Smuzhiyun  * https://github.com/repaper/gratis
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun #include <linux/dma-buf.h>
18*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/property.h>
21*4882a593Smuzhiyun #include <linux/sched/clock.h>
22*4882a593Smuzhiyun #include <linux/spi/spi.h>
23*4882a593Smuzhiyun #include <linux/thermal.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
26*4882a593Smuzhiyun #include <drm/drm_connector.h>
27*4882a593Smuzhiyun #include <drm/drm_damage_helper.h>
28*4882a593Smuzhiyun #include <drm/drm_drv.h>
29*4882a593Smuzhiyun #include <drm/drm_fb_cma_helper.h>
30*4882a593Smuzhiyun #include <drm/drm_fb_helper.h>
31*4882a593Smuzhiyun #include <drm/drm_format_helper.h>
32*4882a593Smuzhiyun #include <drm/drm_gem_cma_helper.h>
33*4882a593Smuzhiyun #include <drm/drm_gem_framebuffer_helper.h>
34*4882a593Smuzhiyun #include <drm/drm_managed.h>
35*4882a593Smuzhiyun #include <drm/drm_modes.h>
36*4882a593Smuzhiyun #include <drm/drm_rect.h>
37*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
38*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define REPAPER_RID_G2_COG_ID	0x12
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun enum repaper_model {
43*4882a593Smuzhiyun 	/* 0 is reserved to avoid clashing with NULL */
44*4882a593Smuzhiyun 	E1144CS021 = 1,
45*4882a593Smuzhiyun 	E1190CS021,
46*4882a593Smuzhiyun 	E2200CS021,
47*4882a593Smuzhiyun 	E2271CS021,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun enum repaper_stage {         /* Image pixel -> Display pixel */
51*4882a593Smuzhiyun 	REPAPER_COMPENSATE,  /* B -> W, W -> B (Current Image) */
52*4882a593Smuzhiyun 	REPAPER_WHITE,       /* B -> N, W -> W (Current Image) */
53*4882a593Smuzhiyun 	REPAPER_INVERSE,     /* B -> N, W -> B (New Image) */
54*4882a593Smuzhiyun 	REPAPER_NORMAL       /* B -> B, W -> W (New Image) */
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun enum repaper_epd_border_byte {
58*4882a593Smuzhiyun 	REPAPER_BORDER_BYTE_NONE,
59*4882a593Smuzhiyun 	REPAPER_BORDER_BYTE_ZERO,
60*4882a593Smuzhiyun 	REPAPER_BORDER_BYTE_SET,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun struct repaper_epd {
64*4882a593Smuzhiyun 	struct drm_device drm;
65*4882a593Smuzhiyun 	struct drm_simple_display_pipe pipe;
66*4882a593Smuzhiyun 	const struct drm_display_mode *mode;
67*4882a593Smuzhiyun 	struct drm_connector connector;
68*4882a593Smuzhiyun 	struct spi_device *spi;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	struct gpio_desc *panel_on;
71*4882a593Smuzhiyun 	struct gpio_desc *border;
72*4882a593Smuzhiyun 	struct gpio_desc *discharge;
73*4882a593Smuzhiyun 	struct gpio_desc *reset;
74*4882a593Smuzhiyun 	struct gpio_desc *busy;
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	struct thermal_zone_device *thermal;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	unsigned int height;
79*4882a593Smuzhiyun 	unsigned int width;
80*4882a593Smuzhiyun 	unsigned int bytes_per_scan;
81*4882a593Smuzhiyun 	const u8 *channel_select;
82*4882a593Smuzhiyun 	unsigned int stage_time;
83*4882a593Smuzhiyun 	unsigned int factored_stage_time;
84*4882a593Smuzhiyun 	bool middle_scan;
85*4882a593Smuzhiyun 	bool pre_border_byte;
86*4882a593Smuzhiyun 	enum repaper_epd_border_byte border_byte;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	u8 *line_buffer;
89*4882a593Smuzhiyun 	void *current_frame;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	bool cleared;
92*4882a593Smuzhiyun 	bool partial;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
drm_to_epd(struct drm_device * drm)95*4882a593Smuzhiyun static inline struct repaper_epd *drm_to_epd(struct drm_device *drm)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	return container_of(drm, struct repaper_epd, drm);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun 
repaper_spi_transfer(struct spi_device * spi,u8 header,const void * tx,void * rx,size_t len)100*4882a593Smuzhiyun static int repaper_spi_transfer(struct spi_device *spi, u8 header,
101*4882a593Smuzhiyun 				const void *tx, void *rx, size_t len)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	void *txbuf = NULL, *rxbuf = NULL;
104*4882a593Smuzhiyun 	struct spi_transfer tr[2] = {};
105*4882a593Smuzhiyun 	u8 *headerbuf;
106*4882a593Smuzhiyun 	int ret;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	headerbuf = kmalloc(1, GFP_KERNEL);
109*4882a593Smuzhiyun 	if (!headerbuf)
110*4882a593Smuzhiyun 		return -ENOMEM;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	headerbuf[0] = header;
113*4882a593Smuzhiyun 	tr[0].tx_buf = headerbuf;
114*4882a593Smuzhiyun 	tr[0].len = 1;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	/* Stack allocated tx? */
117*4882a593Smuzhiyun 	if (tx && len <= 32) {
118*4882a593Smuzhiyun 		txbuf = kmemdup(tx, len, GFP_KERNEL);
119*4882a593Smuzhiyun 		if (!txbuf) {
120*4882a593Smuzhiyun 			ret = -ENOMEM;
121*4882a593Smuzhiyun 			goto out_free;
122*4882a593Smuzhiyun 		}
123*4882a593Smuzhiyun 	}
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	if (rx) {
126*4882a593Smuzhiyun 		rxbuf = kmalloc(len, GFP_KERNEL);
127*4882a593Smuzhiyun 		if (!rxbuf) {
128*4882a593Smuzhiyun 			ret = -ENOMEM;
129*4882a593Smuzhiyun 			goto out_free;
130*4882a593Smuzhiyun 		}
131*4882a593Smuzhiyun 	}
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	tr[1].tx_buf = txbuf ? txbuf : tx;
134*4882a593Smuzhiyun 	tr[1].rx_buf = rxbuf;
135*4882a593Smuzhiyun 	tr[1].len = len;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	ndelay(80);
138*4882a593Smuzhiyun 	ret = spi_sync_transfer(spi, tr, 2);
139*4882a593Smuzhiyun 	if (rx && !ret)
140*4882a593Smuzhiyun 		memcpy(rx, rxbuf, len);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun out_free:
143*4882a593Smuzhiyun 	kfree(headerbuf);
144*4882a593Smuzhiyun 	kfree(txbuf);
145*4882a593Smuzhiyun 	kfree(rxbuf);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	return ret;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
repaper_write_buf(struct spi_device * spi,u8 reg,const u8 * buf,size_t len)150*4882a593Smuzhiyun static int repaper_write_buf(struct spi_device *spi, u8 reg,
151*4882a593Smuzhiyun 			     const u8 *buf, size_t len)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	int ret;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	ret = repaper_spi_transfer(spi, 0x70, &reg, NULL, 1);
156*4882a593Smuzhiyun 	if (ret)
157*4882a593Smuzhiyun 		return ret;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	return repaper_spi_transfer(spi, 0x72, buf, NULL, len);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun 
repaper_write_val(struct spi_device * spi,u8 reg,u8 val)162*4882a593Smuzhiyun static int repaper_write_val(struct spi_device *spi, u8 reg, u8 val)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	return repaper_write_buf(spi, reg, &val, 1);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun 
repaper_read_val(struct spi_device * spi,u8 reg)167*4882a593Smuzhiyun static int repaper_read_val(struct spi_device *spi, u8 reg)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun 	int ret;
170*4882a593Smuzhiyun 	u8 val;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	ret = repaper_spi_transfer(spi, 0x70, &reg, NULL, 1);
173*4882a593Smuzhiyun 	if (ret)
174*4882a593Smuzhiyun 		return ret;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	ret = repaper_spi_transfer(spi, 0x73, NULL, &val, 1);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	return ret ? ret : val;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
repaper_read_id(struct spi_device * spi)181*4882a593Smuzhiyun static int repaper_read_id(struct spi_device *spi)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	int ret;
184*4882a593Smuzhiyun 	u8 id;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	ret = repaper_spi_transfer(spi, 0x71, NULL, &id, 1);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	return ret ? ret : id;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
repaper_spi_mosi_low(struct spi_device * spi)191*4882a593Smuzhiyun static void repaper_spi_mosi_low(struct spi_device *spi)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	const u8 buf[1] = { 0 };
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	spi_write(spi, buf, 1);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun /* pixels on display are numbered from 1 so even is actually bits 1,3,5,... */
repaper_even_pixels(struct repaper_epd * epd,u8 ** pp,const u8 * data,u8 fixed_value,const u8 * mask,enum repaper_stage stage)199*4882a593Smuzhiyun static void repaper_even_pixels(struct repaper_epd *epd, u8 **pp,
200*4882a593Smuzhiyun 				const u8 *data, u8 fixed_value, const u8 *mask,
201*4882a593Smuzhiyun 				enum repaper_stage stage)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun 	unsigned int b;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	for (b = 0; b < (epd->width / 8); b++) {
206*4882a593Smuzhiyun 		if (data) {
207*4882a593Smuzhiyun 			u8 pixels = data[b] & 0xaa;
208*4882a593Smuzhiyun 			u8 pixel_mask = 0xff;
209*4882a593Smuzhiyun 			u8 p1, p2, p3, p4;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 			if (mask) {
212*4882a593Smuzhiyun 				pixel_mask = (mask[b] ^ pixels) & 0xaa;
213*4882a593Smuzhiyun 				pixel_mask |= pixel_mask >> 1;
214*4882a593Smuzhiyun 			}
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 			switch (stage) {
217*4882a593Smuzhiyun 			case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
218*4882a593Smuzhiyun 				pixels = 0xaa | ((pixels ^ 0xaa) >> 1);
219*4882a593Smuzhiyun 				break;
220*4882a593Smuzhiyun 			case REPAPER_WHITE:      /* B -> N, W -> W (Current) */
221*4882a593Smuzhiyun 				pixels = 0x55 + ((pixels ^ 0xaa) >> 1);
222*4882a593Smuzhiyun 				break;
223*4882a593Smuzhiyun 			case REPAPER_INVERSE:    /* B -> N, W -> B (New) */
224*4882a593Smuzhiyun 				pixels = 0x55 | (pixels ^ 0xaa);
225*4882a593Smuzhiyun 				break;
226*4882a593Smuzhiyun 			case REPAPER_NORMAL:     /* B -> B, W -> W (New) */
227*4882a593Smuzhiyun 				pixels = 0xaa | (pixels >> 1);
228*4882a593Smuzhiyun 				break;
229*4882a593Smuzhiyun 			}
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 			pixels = (pixels & pixel_mask) | (~pixel_mask & 0x55);
232*4882a593Smuzhiyun 			p1 = (pixels >> 6) & 0x03;
233*4882a593Smuzhiyun 			p2 = (pixels >> 4) & 0x03;
234*4882a593Smuzhiyun 			p3 = (pixels >> 2) & 0x03;
235*4882a593Smuzhiyun 			p4 = (pixels >> 0) & 0x03;
236*4882a593Smuzhiyun 			pixels = (p1 << 0) | (p2 << 2) | (p3 << 4) | (p4 << 6);
237*4882a593Smuzhiyun 			*(*pp)++ = pixels;
238*4882a593Smuzhiyun 		} else {
239*4882a593Smuzhiyun 			*(*pp)++ = fixed_value;
240*4882a593Smuzhiyun 		}
241*4882a593Smuzhiyun 	}
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun /* pixels on display are numbered from 1 so odd is actually bits 0,2,4,... */
repaper_odd_pixels(struct repaper_epd * epd,u8 ** pp,const u8 * data,u8 fixed_value,const u8 * mask,enum repaper_stage stage)245*4882a593Smuzhiyun static void repaper_odd_pixels(struct repaper_epd *epd, u8 **pp,
246*4882a593Smuzhiyun 			       const u8 *data, u8 fixed_value, const u8 *mask,
247*4882a593Smuzhiyun 			       enum repaper_stage stage)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun 	unsigned int b;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	for (b = epd->width / 8; b > 0; b--) {
252*4882a593Smuzhiyun 		if (data) {
253*4882a593Smuzhiyun 			u8 pixels = data[b - 1] & 0x55;
254*4882a593Smuzhiyun 			u8 pixel_mask = 0xff;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 			if (mask) {
257*4882a593Smuzhiyun 				pixel_mask = (mask[b - 1] ^ pixels) & 0x55;
258*4882a593Smuzhiyun 				pixel_mask |= pixel_mask << 1;
259*4882a593Smuzhiyun 			}
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 			switch (stage) {
262*4882a593Smuzhiyun 			case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
263*4882a593Smuzhiyun 				pixels = 0xaa | (pixels ^ 0x55);
264*4882a593Smuzhiyun 				break;
265*4882a593Smuzhiyun 			case REPAPER_WHITE:      /* B -> N, W -> W (Current) */
266*4882a593Smuzhiyun 				pixels = 0x55 + (pixels ^ 0x55);
267*4882a593Smuzhiyun 				break;
268*4882a593Smuzhiyun 			case REPAPER_INVERSE:    /* B -> N, W -> B (New) */
269*4882a593Smuzhiyun 				pixels = 0x55 | ((pixels ^ 0x55) << 1);
270*4882a593Smuzhiyun 				break;
271*4882a593Smuzhiyun 			case REPAPER_NORMAL:     /* B -> B, W -> W (New) */
272*4882a593Smuzhiyun 				pixels = 0xaa | pixels;
273*4882a593Smuzhiyun 				break;
274*4882a593Smuzhiyun 			}
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 			pixels = (pixels & pixel_mask) | (~pixel_mask & 0x55);
277*4882a593Smuzhiyun 			*(*pp)++ = pixels;
278*4882a593Smuzhiyun 		} else {
279*4882a593Smuzhiyun 			*(*pp)++ = fixed_value;
280*4882a593Smuzhiyun 		}
281*4882a593Smuzhiyun 	}
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun /* interleave bits: (byte)76543210 -> (16 bit).7.6.5.4.3.2.1 */
repaper_interleave_bits(u16 value)285*4882a593Smuzhiyun static inline u16 repaper_interleave_bits(u16 value)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun 	value = (value | (value << 4)) & 0x0f0f;
288*4882a593Smuzhiyun 	value = (value | (value << 2)) & 0x3333;
289*4882a593Smuzhiyun 	value = (value | (value << 1)) & 0x5555;
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	return value;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun /* pixels on display are numbered from 1 */
repaper_all_pixels(struct repaper_epd * epd,u8 ** pp,const u8 * data,u8 fixed_value,const u8 * mask,enum repaper_stage stage)295*4882a593Smuzhiyun static void repaper_all_pixels(struct repaper_epd *epd, u8 **pp,
296*4882a593Smuzhiyun 			       const u8 *data, u8 fixed_value, const u8 *mask,
297*4882a593Smuzhiyun 			       enum repaper_stage stage)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun 	unsigned int b;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	for (b = epd->width / 8; b > 0; b--) {
302*4882a593Smuzhiyun 		if (data) {
303*4882a593Smuzhiyun 			u16 pixels = repaper_interleave_bits(data[b - 1]);
304*4882a593Smuzhiyun 			u16 pixel_mask = 0xffff;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 			if (mask) {
307*4882a593Smuzhiyun 				pixel_mask = repaper_interleave_bits(mask[b - 1]);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 				pixel_mask = (pixel_mask ^ pixels) & 0x5555;
310*4882a593Smuzhiyun 				pixel_mask |= pixel_mask << 1;
311*4882a593Smuzhiyun 			}
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 			switch (stage) {
314*4882a593Smuzhiyun 			case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
315*4882a593Smuzhiyun 				pixels = 0xaaaa | (pixels ^ 0x5555);
316*4882a593Smuzhiyun 				break;
317*4882a593Smuzhiyun 			case REPAPER_WHITE:      /* B -> N, W -> W (Current) */
318*4882a593Smuzhiyun 				pixels = 0x5555 + (pixels ^ 0x5555);
319*4882a593Smuzhiyun 				break;
320*4882a593Smuzhiyun 			case REPAPER_INVERSE:    /* B -> N, W -> B (New) */
321*4882a593Smuzhiyun 				pixels = 0x5555 | ((pixels ^ 0x5555) << 1);
322*4882a593Smuzhiyun 				break;
323*4882a593Smuzhiyun 			case REPAPER_NORMAL:     /* B -> B, W -> W (New) */
324*4882a593Smuzhiyun 				pixels = 0xaaaa | pixels;
325*4882a593Smuzhiyun 				break;
326*4882a593Smuzhiyun 			}
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 			pixels = (pixels & pixel_mask) | (~pixel_mask & 0x5555);
329*4882a593Smuzhiyun 			*(*pp)++ = pixels >> 8;
330*4882a593Smuzhiyun 			*(*pp)++ = pixels;
331*4882a593Smuzhiyun 		} else {
332*4882a593Smuzhiyun 			*(*pp)++ = fixed_value;
333*4882a593Smuzhiyun 			*(*pp)++ = fixed_value;
334*4882a593Smuzhiyun 		}
335*4882a593Smuzhiyun 	}
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun /* output one line of scan and data bytes to the display */
repaper_one_line(struct repaper_epd * epd,unsigned int line,const u8 * data,u8 fixed_value,const u8 * mask,enum repaper_stage stage)339*4882a593Smuzhiyun static void repaper_one_line(struct repaper_epd *epd, unsigned int line,
340*4882a593Smuzhiyun 			     const u8 *data, u8 fixed_value, const u8 *mask,
341*4882a593Smuzhiyun 			     enum repaper_stage stage)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun 	u8 *p = epd->line_buffer;
344*4882a593Smuzhiyun 	unsigned int b;
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	repaper_spi_mosi_low(epd->spi);
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	if (epd->pre_border_byte)
349*4882a593Smuzhiyun 		*p++ = 0x00;
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	if (epd->middle_scan) {
352*4882a593Smuzhiyun 		/* data bytes */
353*4882a593Smuzhiyun 		repaper_odd_pixels(epd, &p, data, fixed_value, mask, stage);
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 		/* scan line */
356*4882a593Smuzhiyun 		for (b = epd->bytes_per_scan; b > 0; b--) {
357*4882a593Smuzhiyun 			if (line / 4 == b - 1)
358*4882a593Smuzhiyun 				*p++ = 0x03 << (2 * (line & 0x03));
359*4882a593Smuzhiyun 			else
360*4882a593Smuzhiyun 				*p++ = 0x00;
361*4882a593Smuzhiyun 		}
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 		/* data bytes */
364*4882a593Smuzhiyun 		repaper_even_pixels(epd, &p, data, fixed_value, mask, stage);
365*4882a593Smuzhiyun 	} else {
366*4882a593Smuzhiyun 		/*
367*4882a593Smuzhiyun 		 * even scan line, but as lines on display are numbered from 1,
368*4882a593Smuzhiyun 		 * line: 1,3,5,...
369*4882a593Smuzhiyun 		 */
370*4882a593Smuzhiyun 		for (b = 0; b < epd->bytes_per_scan; b++) {
371*4882a593Smuzhiyun 			if (0 != (line & 0x01) && line / 8 == b)
372*4882a593Smuzhiyun 				*p++ = 0xc0 >> (line & 0x06);
373*4882a593Smuzhiyun 			else
374*4882a593Smuzhiyun 				*p++ = 0x00;
375*4882a593Smuzhiyun 		}
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 		/* data bytes */
378*4882a593Smuzhiyun 		repaper_all_pixels(epd, &p, data, fixed_value, mask, stage);
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 		/*
381*4882a593Smuzhiyun 		 * odd scan line, but as lines on display are numbered from 1,
382*4882a593Smuzhiyun 		 * line: 0,2,4,6,...
383*4882a593Smuzhiyun 		 */
384*4882a593Smuzhiyun 		for (b = epd->bytes_per_scan; b > 0; b--) {
385*4882a593Smuzhiyun 			if (0 == (line & 0x01) && line / 8 == b - 1)
386*4882a593Smuzhiyun 				*p++ = 0x03 << (line & 0x06);
387*4882a593Smuzhiyun 			else
388*4882a593Smuzhiyun 				*p++ = 0x00;
389*4882a593Smuzhiyun 		}
390*4882a593Smuzhiyun 	}
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	switch (epd->border_byte) {
393*4882a593Smuzhiyun 	case REPAPER_BORDER_BYTE_NONE:
394*4882a593Smuzhiyun 		break;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	case REPAPER_BORDER_BYTE_ZERO:
397*4882a593Smuzhiyun 		*p++ = 0x00;
398*4882a593Smuzhiyun 		break;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	case REPAPER_BORDER_BYTE_SET:
401*4882a593Smuzhiyun 		switch (stage) {
402*4882a593Smuzhiyun 		case REPAPER_COMPENSATE:
403*4882a593Smuzhiyun 		case REPAPER_WHITE:
404*4882a593Smuzhiyun 		case REPAPER_INVERSE:
405*4882a593Smuzhiyun 			*p++ = 0x00;
406*4882a593Smuzhiyun 			break;
407*4882a593Smuzhiyun 		case REPAPER_NORMAL:
408*4882a593Smuzhiyun 			*p++ = 0xaa;
409*4882a593Smuzhiyun 			break;
410*4882a593Smuzhiyun 		}
411*4882a593Smuzhiyun 		break;
412*4882a593Smuzhiyun 	}
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	repaper_write_buf(epd->spi, 0x0a, epd->line_buffer,
415*4882a593Smuzhiyun 			  p - epd->line_buffer);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	/* Output data to panel */
418*4882a593Smuzhiyun 	repaper_write_val(epd->spi, 0x02, 0x07);
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	repaper_spi_mosi_low(epd->spi);
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun 
repaper_frame_fixed(struct repaper_epd * epd,u8 fixed_value,enum repaper_stage stage)423*4882a593Smuzhiyun static void repaper_frame_fixed(struct repaper_epd *epd, u8 fixed_value,
424*4882a593Smuzhiyun 				enum repaper_stage stage)
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun 	unsigned int line;
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	for (line = 0; line < epd->height; line++)
429*4882a593Smuzhiyun 		repaper_one_line(epd, line, NULL, fixed_value, NULL, stage);
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun 
repaper_frame_data(struct repaper_epd * epd,const u8 * image,const u8 * mask,enum repaper_stage stage)432*4882a593Smuzhiyun static void repaper_frame_data(struct repaper_epd *epd, const u8 *image,
433*4882a593Smuzhiyun 			       const u8 *mask, enum repaper_stage stage)
434*4882a593Smuzhiyun {
435*4882a593Smuzhiyun 	unsigned int line;
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	if (!mask) {
438*4882a593Smuzhiyun 		for (line = 0; line < epd->height; line++) {
439*4882a593Smuzhiyun 			repaper_one_line(epd, line,
440*4882a593Smuzhiyun 					 &image[line * (epd->width / 8)],
441*4882a593Smuzhiyun 					 0, NULL, stage);
442*4882a593Smuzhiyun 		}
443*4882a593Smuzhiyun 	} else {
444*4882a593Smuzhiyun 		for (line = 0; line < epd->height; line++) {
445*4882a593Smuzhiyun 			size_t n = line * epd->width / 8;
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 			repaper_one_line(epd, line, &image[n], 0, &mask[n],
448*4882a593Smuzhiyun 					 stage);
449*4882a593Smuzhiyun 		}
450*4882a593Smuzhiyun 	}
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun 
repaper_frame_fixed_repeat(struct repaper_epd * epd,u8 fixed_value,enum repaper_stage stage)453*4882a593Smuzhiyun static void repaper_frame_fixed_repeat(struct repaper_epd *epd, u8 fixed_value,
454*4882a593Smuzhiyun 				       enum repaper_stage stage)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun 	u64 start = local_clock();
457*4882a593Smuzhiyun 	u64 end = start + (epd->factored_stage_time * 1000 * 1000);
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	do {
460*4882a593Smuzhiyun 		repaper_frame_fixed(epd, fixed_value, stage);
461*4882a593Smuzhiyun 	} while (local_clock() < end);
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun 
repaper_frame_data_repeat(struct repaper_epd * epd,const u8 * image,const u8 * mask,enum repaper_stage stage)464*4882a593Smuzhiyun static void repaper_frame_data_repeat(struct repaper_epd *epd, const u8 *image,
465*4882a593Smuzhiyun 				      const u8 *mask, enum repaper_stage stage)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun 	u64 start = local_clock();
468*4882a593Smuzhiyun 	u64 end = start + (epd->factored_stage_time * 1000 * 1000);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	do {
471*4882a593Smuzhiyun 		repaper_frame_data(epd, image, mask, stage);
472*4882a593Smuzhiyun 	} while (local_clock() < end);
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun 
repaper_get_temperature(struct repaper_epd * epd)475*4882a593Smuzhiyun static void repaper_get_temperature(struct repaper_epd *epd)
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun 	int ret, temperature = 0;
478*4882a593Smuzhiyun 	unsigned int factor10x;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	if (!epd->thermal)
481*4882a593Smuzhiyun 		return;
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	ret = thermal_zone_get_temp(epd->thermal, &temperature);
484*4882a593Smuzhiyun 	if (ret) {
485*4882a593Smuzhiyun 		DRM_DEV_ERROR(&epd->spi->dev, "Failed to get temperature (%d)\n", ret);
486*4882a593Smuzhiyun 		return;
487*4882a593Smuzhiyun 	}
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	temperature /= 1000;
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	if (temperature <= -10)
492*4882a593Smuzhiyun 		factor10x = 170;
493*4882a593Smuzhiyun 	else if (temperature <= -5)
494*4882a593Smuzhiyun 		factor10x = 120;
495*4882a593Smuzhiyun 	else if (temperature <= 5)
496*4882a593Smuzhiyun 		factor10x = 80;
497*4882a593Smuzhiyun 	else if (temperature <= 10)
498*4882a593Smuzhiyun 		factor10x = 40;
499*4882a593Smuzhiyun 	else if (temperature <= 15)
500*4882a593Smuzhiyun 		factor10x = 30;
501*4882a593Smuzhiyun 	else if (temperature <= 20)
502*4882a593Smuzhiyun 		factor10x = 20;
503*4882a593Smuzhiyun 	else if (temperature <= 40)
504*4882a593Smuzhiyun 		factor10x = 10;
505*4882a593Smuzhiyun 	else
506*4882a593Smuzhiyun 		factor10x = 7;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	epd->factored_stage_time = epd->stage_time * factor10x / 10;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun 
repaper_gray8_to_mono_reversed(u8 * buf,u32 width,u32 height)511*4882a593Smuzhiyun static void repaper_gray8_to_mono_reversed(u8 *buf, u32 width, u32 height)
512*4882a593Smuzhiyun {
513*4882a593Smuzhiyun 	u8 *gray8 = buf, *mono = buf;
514*4882a593Smuzhiyun 	int y, xb, i;
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	for (y = 0; y < height; y++)
517*4882a593Smuzhiyun 		for (xb = 0; xb < width / 8; xb++) {
518*4882a593Smuzhiyun 			u8 byte = 0x00;
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 			for (i = 0; i < 8; i++) {
521*4882a593Smuzhiyun 				int x = xb * 8 + i;
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun 				byte >>= 1;
524*4882a593Smuzhiyun 				if (gray8[y * width + x] >> 7)
525*4882a593Smuzhiyun 					byte |= BIT(7);
526*4882a593Smuzhiyun 			}
527*4882a593Smuzhiyun 			*mono++ = byte;
528*4882a593Smuzhiyun 		}
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun 
repaper_fb_dirty(struct drm_framebuffer * fb)531*4882a593Smuzhiyun static int repaper_fb_dirty(struct drm_framebuffer *fb)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun 	struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
534*4882a593Smuzhiyun 	struct dma_buf_attachment *import_attach = cma_obj->base.import_attach;
535*4882a593Smuzhiyun 	struct repaper_epd *epd = drm_to_epd(fb->dev);
536*4882a593Smuzhiyun 	struct drm_rect clip;
537*4882a593Smuzhiyun 	int idx, ret = 0;
538*4882a593Smuzhiyun 	u8 *buf = NULL;
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	if (!drm_dev_enter(fb->dev, &idx))
541*4882a593Smuzhiyun 		return -ENODEV;
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	/* repaper can't do partial updates */
544*4882a593Smuzhiyun 	clip.x1 = 0;
545*4882a593Smuzhiyun 	clip.x2 = fb->width;
546*4882a593Smuzhiyun 	clip.y1 = 0;
547*4882a593Smuzhiyun 	clip.y2 = fb->height;
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	repaper_get_temperature(epd);
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	DRM_DEBUG("Flushing [FB:%d] st=%ums\n", fb->base.id,
552*4882a593Smuzhiyun 		  epd->factored_stage_time);
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	buf = kmalloc_array(fb->width, fb->height, GFP_KERNEL);
555*4882a593Smuzhiyun 	if (!buf) {
556*4882a593Smuzhiyun 		ret = -ENOMEM;
557*4882a593Smuzhiyun 		goto out_exit;
558*4882a593Smuzhiyun 	}
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 	if (import_attach) {
561*4882a593Smuzhiyun 		ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
562*4882a593Smuzhiyun 					       DMA_FROM_DEVICE);
563*4882a593Smuzhiyun 		if (ret)
564*4882a593Smuzhiyun 			goto out_free;
565*4882a593Smuzhiyun 	}
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	drm_fb_xrgb8888_to_gray8(buf, cma_obj->vaddr, fb, &clip);
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	if (import_attach) {
570*4882a593Smuzhiyun 		ret = dma_buf_end_cpu_access(import_attach->dmabuf,
571*4882a593Smuzhiyun 					     DMA_FROM_DEVICE);
572*4882a593Smuzhiyun 		if (ret)
573*4882a593Smuzhiyun 			goto out_free;
574*4882a593Smuzhiyun 	}
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun 	repaper_gray8_to_mono_reversed(buf, fb->width, fb->height);
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	if (epd->partial) {
579*4882a593Smuzhiyun 		repaper_frame_data_repeat(epd, buf, epd->current_frame,
580*4882a593Smuzhiyun 					  REPAPER_NORMAL);
581*4882a593Smuzhiyun 	} else if (epd->cleared) {
582*4882a593Smuzhiyun 		repaper_frame_data_repeat(epd, epd->current_frame, NULL,
583*4882a593Smuzhiyun 					  REPAPER_COMPENSATE);
584*4882a593Smuzhiyun 		repaper_frame_data_repeat(epd, epd->current_frame, NULL,
585*4882a593Smuzhiyun 					  REPAPER_WHITE);
586*4882a593Smuzhiyun 		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_INVERSE);
587*4882a593Smuzhiyun 		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_NORMAL);
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 		epd->partial = true;
590*4882a593Smuzhiyun 	} else {
591*4882a593Smuzhiyun 		/* Clear display (anything -> white) */
592*4882a593Smuzhiyun 		repaper_frame_fixed_repeat(epd, 0xff, REPAPER_COMPENSATE);
593*4882a593Smuzhiyun 		repaper_frame_fixed_repeat(epd, 0xff, REPAPER_WHITE);
594*4882a593Smuzhiyun 		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_INVERSE);
595*4882a593Smuzhiyun 		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_NORMAL);
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 		/* Assuming a clear (white) screen output an image */
598*4882a593Smuzhiyun 		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_COMPENSATE);
599*4882a593Smuzhiyun 		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_WHITE);
600*4882a593Smuzhiyun 		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_INVERSE);
601*4882a593Smuzhiyun 		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_NORMAL);
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 		epd->cleared = true;
604*4882a593Smuzhiyun 		epd->partial = true;
605*4882a593Smuzhiyun 	}
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	memcpy(epd->current_frame, buf, fb->width * fb->height / 8);
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	/*
610*4882a593Smuzhiyun 	 * An extra frame write is needed if pixels are set in the bottom line,
611*4882a593Smuzhiyun 	 * or else grey lines rises up from the pixels
612*4882a593Smuzhiyun 	 */
613*4882a593Smuzhiyun 	if (epd->pre_border_byte) {
614*4882a593Smuzhiyun 		unsigned int x;
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 		for (x = 0; x < (fb->width / 8); x++)
617*4882a593Smuzhiyun 			if (buf[x + (fb->width * (fb->height - 1) / 8)]) {
618*4882a593Smuzhiyun 				repaper_frame_data_repeat(epd, buf,
619*4882a593Smuzhiyun 							  epd->current_frame,
620*4882a593Smuzhiyun 							  REPAPER_NORMAL);
621*4882a593Smuzhiyun 				break;
622*4882a593Smuzhiyun 			}
623*4882a593Smuzhiyun 	}
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun out_free:
626*4882a593Smuzhiyun 	kfree(buf);
627*4882a593Smuzhiyun out_exit:
628*4882a593Smuzhiyun 	drm_dev_exit(idx);
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	return ret;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun 
power_off(struct repaper_epd * epd)633*4882a593Smuzhiyun static void power_off(struct repaper_epd *epd)
634*4882a593Smuzhiyun {
635*4882a593Smuzhiyun 	/* Turn off power and all signals */
636*4882a593Smuzhiyun 	gpiod_set_value_cansleep(epd->reset, 0);
637*4882a593Smuzhiyun 	gpiod_set_value_cansleep(epd->panel_on, 0);
638*4882a593Smuzhiyun 	if (epd->border)
639*4882a593Smuzhiyun 		gpiod_set_value_cansleep(epd->border, 0);
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	/* Ensure SPI MOSI and CLOCK are Low before CS Low */
642*4882a593Smuzhiyun 	repaper_spi_mosi_low(epd->spi);
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun 	/* Discharge pulse */
645*4882a593Smuzhiyun 	gpiod_set_value_cansleep(epd->discharge, 1);
646*4882a593Smuzhiyun 	msleep(150);
647*4882a593Smuzhiyun 	gpiod_set_value_cansleep(epd->discharge, 0);
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun 
repaper_pipe_enable(struct drm_simple_display_pipe * pipe,struct drm_crtc_state * crtc_state,struct drm_plane_state * plane_state)650*4882a593Smuzhiyun static void repaper_pipe_enable(struct drm_simple_display_pipe *pipe,
651*4882a593Smuzhiyun 				struct drm_crtc_state *crtc_state,
652*4882a593Smuzhiyun 				struct drm_plane_state *plane_state)
653*4882a593Smuzhiyun {
654*4882a593Smuzhiyun 	struct repaper_epd *epd = drm_to_epd(pipe->crtc.dev);
655*4882a593Smuzhiyun 	struct spi_device *spi = epd->spi;
656*4882a593Smuzhiyun 	struct device *dev = &spi->dev;
657*4882a593Smuzhiyun 	bool dc_ok = false;
658*4882a593Smuzhiyun 	int i, ret, idx;
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	if (!drm_dev_enter(pipe->crtc.dev, &idx))
661*4882a593Smuzhiyun 		return;
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("\n");
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	/* Power up sequence */
666*4882a593Smuzhiyun 	gpiod_set_value_cansleep(epd->reset, 0);
667*4882a593Smuzhiyun 	gpiod_set_value_cansleep(epd->panel_on, 0);
668*4882a593Smuzhiyun 	gpiod_set_value_cansleep(epd->discharge, 0);
669*4882a593Smuzhiyun 	if (epd->border)
670*4882a593Smuzhiyun 		gpiod_set_value_cansleep(epd->border, 0);
671*4882a593Smuzhiyun 	repaper_spi_mosi_low(spi);
672*4882a593Smuzhiyun 	usleep_range(5000, 10000);
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun 	gpiod_set_value_cansleep(epd->panel_on, 1);
675*4882a593Smuzhiyun 	/*
676*4882a593Smuzhiyun 	 * This delay comes from the repaper.org userspace driver, it's not
677*4882a593Smuzhiyun 	 * mentioned in the datasheet.
678*4882a593Smuzhiyun 	 */
679*4882a593Smuzhiyun 	usleep_range(10000, 15000);
680*4882a593Smuzhiyun 	gpiod_set_value_cansleep(epd->reset, 1);
681*4882a593Smuzhiyun 	if (epd->border)
682*4882a593Smuzhiyun 		gpiod_set_value_cansleep(epd->border, 1);
683*4882a593Smuzhiyun 	usleep_range(5000, 10000);
684*4882a593Smuzhiyun 	gpiod_set_value_cansleep(epd->reset, 0);
685*4882a593Smuzhiyun 	usleep_range(5000, 10000);
686*4882a593Smuzhiyun 	gpiod_set_value_cansleep(epd->reset, 1);
687*4882a593Smuzhiyun 	usleep_range(5000, 10000);
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun 	/* Wait for COG to become ready */
690*4882a593Smuzhiyun 	for (i = 100; i > 0; i--) {
691*4882a593Smuzhiyun 		if (!gpiod_get_value_cansleep(epd->busy))
692*4882a593Smuzhiyun 			break;
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 		usleep_range(10, 100);
695*4882a593Smuzhiyun 	}
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	if (!i) {
698*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "timeout waiting for panel to become ready.\n");
699*4882a593Smuzhiyun 		power_off(epd);
700*4882a593Smuzhiyun 		goto out_exit;
701*4882a593Smuzhiyun 	}
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	repaper_read_id(spi);
704*4882a593Smuzhiyun 	ret = repaper_read_id(spi);
705*4882a593Smuzhiyun 	if (ret != REPAPER_RID_G2_COG_ID) {
706*4882a593Smuzhiyun 		if (ret < 0)
707*4882a593Smuzhiyun 			dev_err(dev, "failed to read chip (%d)\n", ret);
708*4882a593Smuzhiyun 		else
709*4882a593Smuzhiyun 			dev_err(dev, "wrong COG ID 0x%02x\n", ret);
710*4882a593Smuzhiyun 		power_off(epd);
711*4882a593Smuzhiyun 		goto out_exit;
712*4882a593Smuzhiyun 	}
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun 	/* Disable OE */
715*4882a593Smuzhiyun 	repaper_write_val(spi, 0x02, 0x40);
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	ret = repaper_read_val(spi, 0x0f);
718*4882a593Smuzhiyun 	if (ret < 0 || !(ret & 0x80)) {
719*4882a593Smuzhiyun 		if (ret < 0)
720*4882a593Smuzhiyun 			DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
721*4882a593Smuzhiyun 		else
722*4882a593Smuzhiyun 			DRM_DEV_ERROR(dev, "panel is reported broken\n");
723*4882a593Smuzhiyun 		power_off(epd);
724*4882a593Smuzhiyun 		goto out_exit;
725*4882a593Smuzhiyun 	}
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	/* Power saving mode */
728*4882a593Smuzhiyun 	repaper_write_val(spi, 0x0b, 0x02);
729*4882a593Smuzhiyun 	/* Channel select */
730*4882a593Smuzhiyun 	repaper_write_buf(spi, 0x01, epd->channel_select, 8);
731*4882a593Smuzhiyun 	/* High power mode osc */
732*4882a593Smuzhiyun 	repaper_write_val(spi, 0x07, 0xd1);
733*4882a593Smuzhiyun 	/* Power setting */
734*4882a593Smuzhiyun 	repaper_write_val(spi, 0x08, 0x02);
735*4882a593Smuzhiyun 	/* Vcom level */
736*4882a593Smuzhiyun 	repaper_write_val(spi, 0x09, 0xc2);
737*4882a593Smuzhiyun 	/* Power setting */
738*4882a593Smuzhiyun 	repaper_write_val(spi, 0x04, 0x03);
739*4882a593Smuzhiyun 	/* Driver latch on */
740*4882a593Smuzhiyun 	repaper_write_val(spi, 0x03, 0x01);
741*4882a593Smuzhiyun 	/* Driver latch off */
742*4882a593Smuzhiyun 	repaper_write_val(spi, 0x03, 0x00);
743*4882a593Smuzhiyun 	usleep_range(5000, 10000);
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun 	/* Start chargepump */
746*4882a593Smuzhiyun 	for (i = 0; i < 4; ++i) {
747*4882a593Smuzhiyun 		/* Charge pump positive voltage on - VGH/VDL on */
748*4882a593Smuzhiyun 		repaper_write_val(spi, 0x05, 0x01);
749*4882a593Smuzhiyun 		msleep(240);
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun 		/* Charge pump negative voltage on - VGL/VDL on */
752*4882a593Smuzhiyun 		repaper_write_val(spi, 0x05, 0x03);
753*4882a593Smuzhiyun 		msleep(40);
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 		/* Charge pump Vcom on - Vcom driver on */
756*4882a593Smuzhiyun 		repaper_write_val(spi, 0x05, 0x0f);
757*4882a593Smuzhiyun 		msleep(40);
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun 		/* check DC/DC */
760*4882a593Smuzhiyun 		ret = repaper_read_val(spi, 0x0f);
761*4882a593Smuzhiyun 		if (ret < 0) {
762*4882a593Smuzhiyun 			DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
763*4882a593Smuzhiyun 			power_off(epd);
764*4882a593Smuzhiyun 			goto out_exit;
765*4882a593Smuzhiyun 		}
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun 		if (ret & 0x40) {
768*4882a593Smuzhiyun 			dc_ok = true;
769*4882a593Smuzhiyun 			break;
770*4882a593Smuzhiyun 		}
771*4882a593Smuzhiyun 	}
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	if (!dc_ok) {
774*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "dc/dc failed\n");
775*4882a593Smuzhiyun 		power_off(epd);
776*4882a593Smuzhiyun 		goto out_exit;
777*4882a593Smuzhiyun 	}
778*4882a593Smuzhiyun 
779*4882a593Smuzhiyun 	/*
780*4882a593Smuzhiyun 	 * Output enable to disable
781*4882a593Smuzhiyun 	 * The userspace driver sets this to 0x04, but the datasheet says 0x06
782*4882a593Smuzhiyun 	 */
783*4882a593Smuzhiyun 	repaper_write_val(spi, 0x02, 0x04);
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun 	epd->partial = false;
786*4882a593Smuzhiyun out_exit:
787*4882a593Smuzhiyun 	drm_dev_exit(idx);
788*4882a593Smuzhiyun }
789*4882a593Smuzhiyun 
repaper_pipe_disable(struct drm_simple_display_pipe * pipe)790*4882a593Smuzhiyun static void repaper_pipe_disable(struct drm_simple_display_pipe *pipe)
791*4882a593Smuzhiyun {
792*4882a593Smuzhiyun 	struct repaper_epd *epd = drm_to_epd(pipe->crtc.dev);
793*4882a593Smuzhiyun 	struct spi_device *spi = epd->spi;
794*4882a593Smuzhiyun 	unsigned int line;
795*4882a593Smuzhiyun 
796*4882a593Smuzhiyun 	/*
797*4882a593Smuzhiyun 	 * This callback is not protected by drm_dev_enter/exit since we want to
798*4882a593Smuzhiyun 	 * turn off the display on regular driver unload. It's highly unlikely
799*4882a593Smuzhiyun 	 * that the underlying SPI controller is gone should this be called after
800*4882a593Smuzhiyun 	 * unplug.
801*4882a593Smuzhiyun 	 */
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("\n");
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun 	/* Nothing frame */
806*4882a593Smuzhiyun 	for (line = 0; line < epd->height; line++)
807*4882a593Smuzhiyun 		repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
808*4882a593Smuzhiyun 				 REPAPER_COMPENSATE);
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 	/* 2.7" */
811*4882a593Smuzhiyun 	if (epd->border) {
812*4882a593Smuzhiyun 		/* Dummy line */
813*4882a593Smuzhiyun 		repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
814*4882a593Smuzhiyun 				 REPAPER_COMPENSATE);
815*4882a593Smuzhiyun 		msleep(25);
816*4882a593Smuzhiyun 		gpiod_set_value_cansleep(epd->border, 0);
817*4882a593Smuzhiyun 		msleep(200);
818*4882a593Smuzhiyun 		gpiod_set_value_cansleep(epd->border, 1);
819*4882a593Smuzhiyun 	} else {
820*4882a593Smuzhiyun 		/* Border dummy line */
821*4882a593Smuzhiyun 		repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
822*4882a593Smuzhiyun 				 REPAPER_NORMAL);
823*4882a593Smuzhiyun 		msleep(200);
824*4882a593Smuzhiyun 	}
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun 	/* not described in datasheet */
827*4882a593Smuzhiyun 	repaper_write_val(spi, 0x0b, 0x00);
828*4882a593Smuzhiyun 	/* Latch reset turn on */
829*4882a593Smuzhiyun 	repaper_write_val(spi, 0x03, 0x01);
830*4882a593Smuzhiyun 	/* Power off charge pump Vcom */
831*4882a593Smuzhiyun 	repaper_write_val(spi, 0x05, 0x03);
832*4882a593Smuzhiyun 	/* Power off charge pump neg voltage */
833*4882a593Smuzhiyun 	repaper_write_val(spi, 0x05, 0x01);
834*4882a593Smuzhiyun 	msleep(120);
835*4882a593Smuzhiyun 	/* Discharge internal */
836*4882a593Smuzhiyun 	repaper_write_val(spi, 0x04, 0x80);
837*4882a593Smuzhiyun 	/* turn off all charge pumps */
838*4882a593Smuzhiyun 	repaper_write_val(spi, 0x05, 0x00);
839*4882a593Smuzhiyun 	/* Turn off osc */
840*4882a593Smuzhiyun 	repaper_write_val(spi, 0x07, 0x01);
841*4882a593Smuzhiyun 	msleep(50);
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun 	power_off(epd);
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun 
repaper_pipe_update(struct drm_simple_display_pipe * pipe,struct drm_plane_state * old_state)846*4882a593Smuzhiyun static void repaper_pipe_update(struct drm_simple_display_pipe *pipe,
847*4882a593Smuzhiyun 				struct drm_plane_state *old_state)
848*4882a593Smuzhiyun {
849*4882a593Smuzhiyun 	struct drm_plane_state *state = pipe->plane.state;
850*4882a593Smuzhiyun 	struct drm_rect rect;
851*4882a593Smuzhiyun 
852*4882a593Smuzhiyun 	if (!pipe->crtc.state->active)
853*4882a593Smuzhiyun 		return;
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun 	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
856*4882a593Smuzhiyun 		repaper_fb_dirty(state->fb);
857*4882a593Smuzhiyun }
858*4882a593Smuzhiyun 
859*4882a593Smuzhiyun static const struct drm_simple_display_pipe_funcs repaper_pipe_funcs = {
860*4882a593Smuzhiyun 	.enable = repaper_pipe_enable,
861*4882a593Smuzhiyun 	.disable = repaper_pipe_disable,
862*4882a593Smuzhiyun 	.update = repaper_pipe_update,
863*4882a593Smuzhiyun 	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
864*4882a593Smuzhiyun };
865*4882a593Smuzhiyun 
repaper_connector_get_modes(struct drm_connector * connector)866*4882a593Smuzhiyun static int repaper_connector_get_modes(struct drm_connector *connector)
867*4882a593Smuzhiyun {
868*4882a593Smuzhiyun 	struct repaper_epd *epd = drm_to_epd(connector->dev);
869*4882a593Smuzhiyun 	struct drm_display_mode *mode;
870*4882a593Smuzhiyun 
871*4882a593Smuzhiyun 	mode = drm_mode_duplicate(connector->dev, epd->mode);
872*4882a593Smuzhiyun 	if (!mode) {
873*4882a593Smuzhiyun 		DRM_ERROR("Failed to duplicate mode\n");
874*4882a593Smuzhiyun 		return 0;
875*4882a593Smuzhiyun 	}
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	drm_mode_set_name(mode);
878*4882a593Smuzhiyun 	mode->type |= DRM_MODE_TYPE_PREFERRED;
879*4882a593Smuzhiyun 	drm_mode_probed_add(connector, mode);
880*4882a593Smuzhiyun 
881*4882a593Smuzhiyun 	connector->display_info.width_mm = mode->width_mm;
882*4882a593Smuzhiyun 	connector->display_info.height_mm = mode->height_mm;
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun 	return 1;
885*4882a593Smuzhiyun }
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun static const struct drm_connector_helper_funcs repaper_connector_hfuncs = {
888*4882a593Smuzhiyun 	.get_modes = repaper_connector_get_modes,
889*4882a593Smuzhiyun };
890*4882a593Smuzhiyun 
891*4882a593Smuzhiyun static const struct drm_connector_funcs repaper_connector_funcs = {
892*4882a593Smuzhiyun 	.reset = drm_atomic_helper_connector_reset,
893*4882a593Smuzhiyun 	.fill_modes = drm_helper_probe_single_connector_modes,
894*4882a593Smuzhiyun 	.destroy = drm_connector_cleanup,
895*4882a593Smuzhiyun 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
896*4882a593Smuzhiyun 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
897*4882a593Smuzhiyun };
898*4882a593Smuzhiyun 
899*4882a593Smuzhiyun static const struct drm_mode_config_funcs repaper_mode_config_funcs = {
900*4882a593Smuzhiyun 	.fb_create = drm_gem_fb_create_with_dirty,
901*4882a593Smuzhiyun 	.atomic_check = drm_atomic_helper_check,
902*4882a593Smuzhiyun 	.atomic_commit = drm_atomic_helper_commit,
903*4882a593Smuzhiyun };
904*4882a593Smuzhiyun 
905*4882a593Smuzhiyun static const uint32_t repaper_formats[] = {
906*4882a593Smuzhiyun 	DRM_FORMAT_XRGB8888,
907*4882a593Smuzhiyun };
908*4882a593Smuzhiyun 
909*4882a593Smuzhiyun static const struct drm_display_mode repaper_e1144cs021_mode = {
910*4882a593Smuzhiyun 	DRM_SIMPLE_MODE(128, 96, 29, 22),
911*4882a593Smuzhiyun };
912*4882a593Smuzhiyun 
913*4882a593Smuzhiyun static const u8 repaper_e1144cs021_cs[] = { 0x00, 0x00, 0x00, 0x00,
914*4882a593Smuzhiyun 					    0x00, 0x0f, 0xff, 0x00 };
915*4882a593Smuzhiyun 
916*4882a593Smuzhiyun static const struct drm_display_mode repaper_e1190cs021_mode = {
917*4882a593Smuzhiyun 	DRM_SIMPLE_MODE(144, 128, 36, 32),
918*4882a593Smuzhiyun };
919*4882a593Smuzhiyun 
920*4882a593Smuzhiyun static const u8 repaper_e1190cs021_cs[] = { 0x00, 0x00, 0x00, 0x03,
921*4882a593Smuzhiyun 					    0xfc, 0x00, 0x00, 0xff };
922*4882a593Smuzhiyun 
923*4882a593Smuzhiyun static const struct drm_display_mode repaper_e2200cs021_mode = {
924*4882a593Smuzhiyun 	DRM_SIMPLE_MODE(200, 96, 46, 22),
925*4882a593Smuzhiyun };
926*4882a593Smuzhiyun 
927*4882a593Smuzhiyun static const u8 repaper_e2200cs021_cs[] = { 0x00, 0x00, 0x00, 0x00,
928*4882a593Smuzhiyun 					    0x01, 0xff, 0xe0, 0x00 };
929*4882a593Smuzhiyun 
930*4882a593Smuzhiyun static const struct drm_display_mode repaper_e2271cs021_mode = {
931*4882a593Smuzhiyun 	DRM_SIMPLE_MODE(264, 176, 57, 38),
932*4882a593Smuzhiyun };
933*4882a593Smuzhiyun 
934*4882a593Smuzhiyun static const u8 repaper_e2271cs021_cs[] = { 0x00, 0x00, 0x00, 0x7f,
935*4882a593Smuzhiyun 					    0xff, 0xfe, 0x00, 0x00 };
936*4882a593Smuzhiyun 
937*4882a593Smuzhiyun DEFINE_DRM_GEM_CMA_FOPS(repaper_fops);
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun static struct drm_driver repaper_driver = {
940*4882a593Smuzhiyun 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
941*4882a593Smuzhiyun 	.fops			= &repaper_fops,
942*4882a593Smuzhiyun 	DRM_GEM_CMA_DRIVER_OPS_VMAP,
943*4882a593Smuzhiyun 	.name			= "repaper",
944*4882a593Smuzhiyun 	.desc			= "Pervasive Displays RePaper e-ink panels",
945*4882a593Smuzhiyun 	.date			= "20170405",
946*4882a593Smuzhiyun 	.major			= 1,
947*4882a593Smuzhiyun 	.minor			= 0,
948*4882a593Smuzhiyun };
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun static const struct of_device_id repaper_of_match[] = {
951*4882a593Smuzhiyun 	{ .compatible = "pervasive,e1144cs021", .data = (void *)E1144CS021 },
952*4882a593Smuzhiyun 	{ .compatible = "pervasive,e1190cs021", .data = (void *)E1190CS021 },
953*4882a593Smuzhiyun 	{ .compatible = "pervasive,e2200cs021", .data = (void *)E2200CS021 },
954*4882a593Smuzhiyun 	{ .compatible = "pervasive,e2271cs021", .data = (void *)E2271CS021 },
955*4882a593Smuzhiyun 	{},
956*4882a593Smuzhiyun };
957*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, repaper_of_match);
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun static const struct spi_device_id repaper_id[] = {
960*4882a593Smuzhiyun 	{ "e1144cs021", E1144CS021 },
961*4882a593Smuzhiyun 	{ "e1190cs021", E1190CS021 },
962*4882a593Smuzhiyun 	{ "e2200cs021", E2200CS021 },
963*4882a593Smuzhiyun 	{ "e2271cs021", E2271CS021 },
964*4882a593Smuzhiyun 	{ },
965*4882a593Smuzhiyun };
966*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, repaper_id);
967*4882a593Smuzhiyun 
repaper_probe(struct spi_device * spi)968*4882a593Smuzhiyun static int repaper_probe(struct spi_device *spi)
969*4882a593Smuzhiyun {
970*4882a593Smuzhiyun 	const struct drm_display_mode *mode;
971*4882a593Smuzhiyun 	const struct spi_device_id *spi_id;
972*4882a593Smuzhiyun 	struct device *dev = &spi->dev;
973*4882a593Smuzhiyun 	enum repaper_model model;
974*4882a593Smuzhiyun 	const char *thermal_zone;
975*4882a593Smuzhiyun 	struct repaper_epd *epd;
976*4882a593Smuzhiyun 	size_t line_buffer_size;
977*4882a593Smuzhiyun 	struct drm_device *drm;
978*4882a593Smuzhiyun 	const void *match;
979*4882a593Smuzhiyun 	int ret;
980*4882a593Smuzhiyun 
981*4882a593Smuzhiyun 	match = device_get_match_data(dev);
982*4882a593Smuzhiyun 	if (match) {
983*4882a593Smuzhiyun 		model = (enum repaper_model)match;
984*4882a593Smuzhiyun 	} else {
985*4882a593Smuzhiyun 		spi_id = spi_get_device_id(spi);
986*4882a593Smuzhiyun 		model = (enum repaper_model)spi_id->driver_data;
987*4882a593Smuzhiyun 	}
988*4882a593Smuzhiyun 
989*4882a593Smuzhiyun 	/* The SPI device is used to allocate dma memory */
990*4882a593Smuzhiyun 	if (!dev->coherent_dma_mask) {
991*4882a593Smuzhiyun 		ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
992*4882a593Smuzhiyun 		if (ret) {
993*4882a593Smuzhiyun 			dev_warn(dev, "Failed to set dma mask %d\n", ret);
994*4882a593Smuzhiyun 			return ret;
995*4882a593Smuzhiyun 		}
996*4882a593Smuzhiyun 	}
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	epd = devm_drm_dev_alloc(dev, &repaper_driver,
999*4882a593Smuzhiyun 				 struct repaper_epd, drm);
1000*4882a593Smuzhiyun 	if (IS_ERR(epd))
1001*4882a593Smuzhiyun 		return PTR_ERR(epd);
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun 	drm = &epd->drm;
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun 	ret = drmm_mode_config_init(drm);
1006*4882a593Smuzhiyun 	if (ret)
1007*4882a593Smuzhiyun 		return ret;
1008*4882a593Smuzhiyun 	drm->mode_config.funcs = &repaper_mode_config_funcs;
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	epd->spi = spi;
1011*4882a593Smuzhiyun 
1012*4882a593Smuzhiyun 	epd->panel_on = devm_gpiod_get(dev, "panel-on", GPIOD_OUT_LOW);
1013*4882a593Smuzhiyun 	if (IS_ERR(epd->panel_on)) {
1014*4882a593Smuzhiyun 		ret = PTR_ERR(epd->panel_on);
1015*4882a593Smuzhiyun 		if (ret != -EPROBE_DEFER)
1016*4882a593Smuzhiyun 			DRM_DEV_ERROR(dev, "Failed to get gpio 'panel-on'\n");
1017*4882a593Smuzhiyun 		return ret;
1018*4882a593Smuzhiyun 	}
1019*4882a593Smuzhiyun 
1020*4882a593Smuzhiyun 	epd->discharge = devm_gpiod_get(dev, "discharge", GPIOD_OUT_LOW);
1021*4882a593Smuzhiyun 	if (IS_ERR(epd->discharge)) {
1022*4882a593Smuzhiyun 		ret = PTR_ERR(epd->discharge);
1023*4882a593Smuzhiyun 		if (ret != -EPROBE_DEFER)
1024*4882a593Smuzhiyun 			DRM_DEV_ERROR(dev, "Failed to get gpio 'discharge'\n");
1025*4882a593Smuzhiyun 		return ret;
1026*4882a593Smuzhiyun 	}
1027*4882a593Smuzhiyun 
1028*4882a593Smuzhiyun 	epd->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1029*4882a593Smuzhiyun 	if (IS_ERR(epd->reset)) {
1030*4882a593Smuzhiyun 		ret = PTR_ERR(epd->reset);
1031*4882a593Smuzhiyun 		if (ret != -EPROBE_DEFER)
1032*4882a593Smuzhiyun 			DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
1033*4882a593Smuzhiyun 		return ret;
1034*4882a593Smuzhiyun 	}
1035*4882a593Smuzhiyun 
1036*4882a593Smuzhiyun 	epd->busy = devm_gpiod_get(dev, "busy", GPIOD_IN);
1037*4882a593Smuzhiyun 	if (IS_ERR(epd->busy)) {
1038*4882a593Smuzhiyun 		ret = PTR_ERR(epd->busy);
1039*4882a593Smuzhiyun 		if (ret != -EPROBE_DEFER)
1040*4882a593Smuzhiyun 			DRM_DEV_ERROR(dev, "Failed to get gpio 'busy'\n");
1041*4882a593Smuzhiyun 		return ret;
1042*4882a593Smuzhiyun 	}
1043*4882a593Smuzhiyun 
1044*4882a593Smuzhiyun 	if (!device_property_read_string(dev, "pervasive,thermal-zone",
1045*4882a593Smuzhiyun 					 &thermal_zone)) {
1046*4882a593Smuzhiyun 		epd->thermal = thermal_zone_get_zone_by_name(thermal_zone);
1047*4882a593Smuzhiyun 		if (IS_ERR(epd->thermal)) {
1048*4882a593Smuzhiyun 			DRM_DEV_ERROR(dev, "Failed to get thermal zone: %s\n", thermal_zone);
1049*4882a593Smuzhiyun 			return PTR_ERR(epd->thermal);
1050*4882a593Smuzhiyun 		}
1051*4882a593Smuzhiyun 	}
1052*4882a593Smuzhiyun 
1053*4882a593Smuzhiyun 	switch (model) {
1054*4882a593Smuzhiyun 	case E1144CS021:
1055*4882a593Smuzhiyun 		mode = &repaper_e1144cs021_mode;
1056*4882a593Smuzhiyun 		epd->channel_select = repaper_e1144cs021_cs;
1057*4882a593Smuzhiyun 		epd->stage_time = 480;
1058*4882a593Smuzhiyun 		epd->bytes_per_scan = 96 / 4;
1059*4882a593Smuzhiyun 		epd->middle_scan = true; /* data-scan-data */
1060*4882a593Smuzhiyun 		epd->pre_border_byte = false;
1061*4882a593Smuzhiyun 		epd->border_byte = REPAPER_BORDER_BYTE_ZERO;
1062*4882a593Smuzhiyun 		break;
1063*4882a593Smuzhiyun 
1064*4882a593Smuzhiyun 	case E1190CS021:
1065*4882a593Smuzhiyun 		mode = &repaper_e1190cs021_mode;
1066*4882a593Smuzhiyun 		epd->channel_select = repaper_e1190cs021_cs;
1067*4882a593Smuzhiyun 		epd->stage_time = 480;
1068*4882a593Smuzhiyun 		epd->bytes_per_scan = 128 / 4 / 2;
1069*4882a593Smuzhiyun 		epd->middle_scan = false; /* scan-data-scan */
1070*4882a593Smuzhiyun 		epd->pre_border_byte = false;
1071*4882a593Smuzhiyun 		epd->border_byte = REPAPER_BORDER_BYTE_SET;
1072*4882a593Smuzhiyun 		break;
1073*4882a593Smuzhiyun 
1074*4882a593Smuzhiyun 	case E2200CS021:
1075*4882a593Smuzhiyun 		mode = &repaper_e2200cs021_mode;
1076*4882a593Smuzhiyun 		epd->channel_select = repaper_e2200cs021_cs;
1077*4882a593Smuzhiyun 		epd->stage_time = 480;
1078*4882a593Smuzhiyun 		epd->bytes_per_scan = 96 / 4;
1079*4882a593Smuzhiyun 		epd->middle_scan = true; /* data-scan-data */
1080*4882a593Smuzhiyun 		epd->pre_border_byte = true;
1081*4882a593Smuzhiyun 		epd->border_byte = REPAPER_BORDER_BYTE_NONE;
1082*4882a593Smuzhiyun 		break;
1083*4882a593Smuzhiyun 
1084*4882a593Smuzhiyun 	case E2271CS021:
1085*4882a593Smuzhiyun 		epd->border = devm_gpiod_get(dev, "border", GPIOD_OUT_LOW);
1086*4882a593Smuzhiyun 		if (IS_ERR(epd->border)) {
1087*4882a593Smuzhiyun 			ret = PTR_ERR(epd->border);
1088*4882a593Smuzhiyun 			if (ret != -EPROBE_DEFER)
1089*4882a593Smuzhiyun 				DRM_DEV_ERROR(dev, "Failed to get gpio 'border'\n");
1090*4882a593Smuzhiyun 			return ret;
1091*4882a593Smuzhiyun 		}
1092*4882a593Smuzhiyun 
1093*4882a593Smuzhiyun 		mode = &repaper_e2271cs021_mode;
1094*4882a593Smuzhiyun 		epd->channel_select = repaper_e2271cs021_cs;
1095*4882a593Smuzhiyun 		epd->stage_time = 630;
1096*4882a593Smuzhiyun 		epd->bytes_per_scan = 176 / 4;
1097*4882a593Smuzhiyun 		epd->middle_scan = true; /* data-scan-data */
1098*4882a593Smuzhiyun 		epd->pre_border_byte = true;
1099*4882a593Smuzhiyun 		epd->border_byte = REPAPER_BORDER_BYTE_NONE;
1100*4882a593Smuzhiyun 		break;
1101*4882a593Smuzhiyun 
1102*4882a593Smuzhiyun 	default:
1103*4882a593Smuzhiyun 		return -ENODEV;
1104*4882a593Smuzhiyun 	}
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	epd->mode = mode;
1107*4882a593Smuzhiyun 	epd->width = mode->hdisplay;
1108*4882a593Smuzhiyun 	epd->height = mode->vdisplay;
1109*4882a593Smuzhiyun 	epd->factored_stage_time = epd->stage_time;
1110*4882a593Smuzhiyun 
1111*4882a593Smuzhiyun 	line_buffer_size = 2 * epd->width / 8 + epd->bytes_per_scan + 2;
1112*4882a593Smuzhiyun 	epd->line_buffer = devm_kzalloc(dev, line_buffer_size, GFP_KERNEL);
1113*4882a593Smuzhiyun 	if (!epd->line_buffer)
1114*4882a593Smuzhiyun 		return -ENOMEM;
1115*4882a593Smuzhiyun 
1116*4882a593Smuzhiyun 	epd->current_frame = devm_kzalloc(dev, epd->width * epd->height / 8,
1117*4882a593Smuzhiyun 					  GFP_KERNEL);
1118*4882a593Smuzhiyun 	if (!epd->current_frame)
1119*4882a593Smuzhiyun 		return -ENOMEM;
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun 	drm->mode_config.min_width = mode->hdisplay;
1122*4882a593Smuzhiyun 	drm->mode_config.max_width = mode->hdisplay;
1123*4882a593Smuzhiyun 	drm->mode_config.min_height = mode->vdisplay;
1124*4882a593Smuzhiyun 	drm->mode_config.max_height = mode->vdisplay;
1125*4882a593Smuzhiyun 
1126*4882a593Smuzhiyun 	drm_connector_helper_add(&epd->connector, &repaper_connector_hfuncs);
1127*4882a593Smuzhiyun 	ret = drm_connector_init(drm, &epd->connector, &repaper_connector_funcs,
1128*4882a593Smuzhiyun 				 DRM_MODE_CONNECTOR_SPI);
1129*4882a593Smuzhiyun 	if (ret)
1130*4882a593Smuzhiyun 		return ret;
1131*4882a593Smuzhiyun 
1132*4882a593Smuzhiyun 	ret = drm_simple_display_pipe_init(drm, &epd->pipe, &repaper_pipe_funcs,
1133*4882a593Smuzhiyun 					   repaper_formats, ARRAY_SIZE(repaper_formats),
1134*4882a593Smuzhiyun 					   NULL, &epd->connector);
1135*4882a593Smuzhiyun 	if (ret)
1136*4882a593Smuzhiyun 		return ret;
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 	drm_mode_config_reset(drm);
1139*4882a593Smuzhiyun 
1140*4882a593Smuzhiyun 	ret = drm_dev_register(drm, 0);
1141*4882a593Smuzhiyun 	if (ret)
1142*4882a593Smuzhiyun 		return ret;
1143*4882a593Smuzhiyun 
1144*4882a593Smuzhiyun 	spi_set_drvdata(spi, drm);
1145*4882a593Smuzhiyun 
1146*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1147*4882a593Smuzhiyun 
1148*4882a593Smuzhiyun 	drm_fbdev_generic_setup(drm, 0);
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun 	return 0;
1151*4882a593Smuzhiyun }
1152*4882a593Smuzhiyun 
repaper_remove(struct spi_device * spi)1153*4882a593Smuzhiyun static int repaper_remove(struct spi_device *spi)
1154*4882a593Smuzhiyun {
1155*4882a593Smuzhiyun 	struct drm_device *drm = spi_get_drvdata(spi);
1156*4882a593Smuzhiyun 
1157*4882a593Smuzhiyun 	drm_dev_unplug(drm);
1158*4882a593Smuzhiyun 	drm_atomic_helper_shutdown(drm);
1159*4882a593Smuzhiyun 
1160*4882a593Smuzhiyun 	return 0;
1161*4882a593Smuzhiyun }
1162*4882a593Smuzhiyun 
repaper_shutdown(struct spi_device * spi)1163*4882a593Smuzhiyun static void repaper_shutdown(struct spi_device *spi)
1164*4882a593Smuzhiyun {
1165*4882a593Smuzhiyun 	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
1166*4882a593Smuzhiyun }
1167*4882a593Smuzhiyun 
1168*4882a593Smuzhiyun static struct spi_driver repaper_spi_driver = {
1169*4882a593Smuzhiyun 	.driver = {
1170*4882a593Smuzhiyun 		.name = "repaper",
1171*4882a593Smuzhiyun 		.of_match_table = repaper_of_match,
1172*4882a593Smuzhiyun 	},
1173*4882a593Smuzhiyun 	.id_table = repaper_id,
1174*4882a593Smuzhiyun 	.probe = repaper_probe,
1175*4882a593Smuzhiyun 	.remove = repaper_remove,
1176*4882a593Smuzhiyun 	.shutdown = repaper_shutdown,
1177*4882a593Smuzhiyun };
1178*4882a593Smuzhiyun module_spi_driver(repaper_spi_driver);
1179*4882a593Smuzhiyun 
1180*4882a593Smuzhiyun MODULE_DESCRIPTION("Pervasive Displays RePaper DRM driver");
1181*4882a593Smuzhiyun MODULE_AUTHOR("Noralf Trønnes");
1182*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1183