xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/tiny/ili9486.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * DRM driver for Ilitek ILI9486 panels
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2020 Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/backlight.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/property.h>
13*4882a593Smuzhiyun #include <linux/spi/spi.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <video/mipi_display.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
18*4882a593Smuzhiyun #include <drm/drm_drv.h>
19*4882a593Smuzhiyun #include <drm/drm_fb_helper.h>
20*4882a593Smuzhiyun #include <drm/drm_gem_cma_helper.h>
21*4882a593Smuzhiyun #include <drm/drm_gem_framebuffer_helper.h>
22*4882a593Smuzhiyun #include <drm/drm_managed.h>
23*4882a593Smuzhiyun #include <drm/drm_mipi_dbi.h>
24*4882a593Smuzhiyun #include <drm/drm_modeset_helper.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define ILI9486_ITFCTR1         0xb0
27*4882a593Smuzhiyun #define ILI9486_PWCTRL1         0xc2
28*4882a593Smuzhiyun #define ILI9486_VMCTRL1         0xc5
29*4882a593Smuzhiyun #define ILI9486_PGAMCTRL        0xe0
30*4882a593Smuzhiyun #define ILI9486_NGAMCTRL        0xe1
31*4882a593Smuzhiyun #define ILI9486_DGAMCTRL        0xe2
32*4882a593Smuzhiyun #define ILI9486_MADCTL_BGR      BIT(3)
33*4882a593Smuzhiyun #define ILI9486_MADCTL_MV       BIT(5)
34*4882a593Smuzhiyun #define ILI9486_MADCTL_MX       BIT(6)
35*4882a593Smuzhiyun #define ILI9486_MADCTL_MY       BIT(7)
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun  * The PiScreen/waveshare rpi-lcd-35 has a SPI to 16-bit parallel bus converter
39*4882a593Smuzhiyun  * in front of the  display controller. This means that 8-bit values have to be
40*4882a593Smuzhiyun  * transferred as 16-bit.
41*4882a593Smuzhiyun  */
waveshare_command(struct mipi_dbi * mipi,u8 * cmd,u8 * par,size_t num)42*4882a593Smuzhiyun static int waveshare_command(struct mipi_dbi *mipi, u8 *cmd, u8 *par,
43*4882a593Smuzhiyun 			     size_t num)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun 	struct spi_device *spi = mipi->spi;
46*4882a593Smuzhiyun 	void *data = par;
47*4882a593Smuzhiyun 	u32 speed_hz;
48*4882a593Smuzhiyun 	int i, ret;
49*4882a593Smuzhiyun 	__be16 *buf;
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	buf = kmalloc(32 * sizeof(u16), GFP_KERNEL);
52*4882a593Smuzhiyun 	if (!buf)
53*4882a593Smuzhiyun 		return -ENOMEM;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	/*
56*4882a593Smuzhiyun 	 * The displays are Raspberry Pi HATs and connected to the 8-bit only
57*4882a593Smuzhiyun 	 * SPI controller, so 16-bit command and parameters need byte swapping
58*4882a593Smuzhiyun 	 * before being transferred as 8-bit on the big endian SPI bus.
59*4882a593Smuzhiyun 	 * Pixel data bytes have already been swapped before this function is
60*4882a593Smuzhiyun 	 * called.
61*4882a593Smuzhiyun 	 */
62*4882a593Smuzhiyun 	buf[0] = cpu_to_be16(*cmd);
63*4882a593Smuzhiyun 	gpiod_set_value_cansleep(mipi->dc, 0);
64*4882a593Smuzhiyun 	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 2);
65*4882a593Smuzhiyun 	ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, buf, 2);
66*4882a593Smuzhiyun 	if (ret || !num)
67*4882a593Smuzhiyun 		goto free;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	/* 8-bit configuration data, not 16-bit pixel data */
70*4882a593Smuzhiyun 	if (num <= 32) {
71*4882a593Smuzhiyun 		for (i = 0; i < num; i++)
72*4882a593Smuzhiyun 			buf[i] = cpu_to_be16(par[i]);
73*4882a593Smuzhiyun 		num *= 2;
74*4882a593Smuzhiyun 		speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
75*4882a593Smuzhiyun 		data = buf;
76*4882a593Smuzhiyun 	}
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	gpiod_set_value_cansleep(mipi->dc, 1);
79*4882a593Smuzhiyun 	ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, data, num);
80*4882a593Smuzhiyun  free:
81*4882a593Smuzhiyun 	kfree(buf);
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	return ret;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun 
waveshare_enable(struct drm_simple_display_pipe * pipe,struct drm_crtc_state * crtc_state,struct drm_plane_state * plane_state)86*4882a593Smuzhiyun static void waveshare_enable(struct drm_simple_display_pipe *pipe,
87*4882a593Smuzhiyun 			     struct drm_crtc_state *crtc_state,
88*4882a593Smuzhiyun 			     struct drm_plane_state *plane_state)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
91*4882a593Smuzhiyun 	struct mipi_dbi *dbi = &dbidev->dbi;
92*4882a593Smuzhiyun 	u8 addr_mode;
93*4882a593Smuzhiyun 	int ret, idx;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	if (!drm_dev_enter(pipe->crtc.dev, &idx))
96*4882a593Smuzhiyun 		return;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	DRM_DEBUG_KMS("\n");
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	ret = mipi_dbi_poweron_conditional_reset(dbidev);
101*4882a593Smuzhiyun 	if (ret < 0)
102*4882a593Smuzhiyun 		goto out_exit;
103*4882a593Smuzhiyun 	if (ret == 1)
104*4882a593Smuzhiyun 		goto out_enable;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	mipi_dbi_command(dbi, ILI9486_ITFCTR1);
107*4882a593Smuzhiyun 	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
108*4882a593Smuzhiyun 	msleep(250);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, 0x55);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	mipi_dbi_command(dbi, ILI9486_PWCTRL1, 0x44);
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	mipi_dbi_command(dbi, ILI9486_VMCTRL1, 0x00, 0x00, 0x00, 0x00);
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	mipi_dbi_command(dbi, ILI9486_PGAMCTRL,
117*4882a593Smuzhiyun 			 0x0F, 0x1F, 0x1C, 0x0C, 0x0F, 0x08, 0x48, 0x98,
118*4882a593Smuzhiyun 			 0x37, 0x0A, 0x13, 0x04, 0x11, 0x0D, 0x0);
119*4882a593Smuzhiyun 	mipi_dbi_command(dbi, ILI9486_NGAMCTRL,
120*4882a593Smuzhiyun 			 0x0F, 0x32, 0x2E, 0x0B, 0x0D, 0x05, 0x47, 0x75,
121*4882a593Smuzhiyun 			 0x37, 0x06, 0x10, 0x03, 0x24, 0x20, 0x00);
122*4882a593Smuzhiyun 	mipi_dbi_command(dbi, ILI9486_DGAMCTRL,
123*4882a593Smuzhiyun 			 0x0F, 0x32, 0x2E, 0x0B, 0x0D, 0x05, 0x47, 0x75,
124*4882a593Smuzhiyun 			 0x37, 0x06, 0x10, 0x03, 0x24, 0x20, 0x00);
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
127*4882a593Smuzhiyun 	msleep(100);
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun  out_enable:
130*4882a593Smuzhiyun 	switch (dbidev->rotation) {
131*4882a593Smuzhiyun 	case 90:
132*4882a593Smuzhiyun 		addr_mode = ILI9486_MADCTL_MY;
133*4882a593Smuzhiyun 		break;
134*4882a593Smuzhiyun 	case 180:
135*4882a593Smuzhiyun 		addr_mode = ILI9486_MADCTL_MV;
136*4882a593Smuzhiyun 		break;
137*4882a593Smuzhiyun 	case 270:
138*4882a593Smuzhiyun 		addr_mode = ILI9486_MADCTL_MX;
139*4882a593Smuzhiyun 		break;
140*4882a593Smuzhiyun 	default:
141*4882a593Smuzhiyun 		addr_mode = ILI9486_MADCTL_MV | ILI9486_MADCTL_MY |
142*4882a593Smuzhiyun 			ILI9486_MADCTL_MX;
143*4882a593Smuzhiyun 		break;
144*4882a593Smuzhiyun 	}
145*4882a593Smuzhiyun 	addr_mode |= ILI9486_MADCTL_BGR;
146*4882a593Smuzhiyun 	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
147*4882a593Smuzhiyun 	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
148*4882a593Smuzhiyun  out_exit:
149*4882a593Smuzhiyun 	drm_dev_exit(idx);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun static const struct drm_simple_display_pipe_funcs waveshare_pipe_funcs = {
153*4882a593Smuzhiyun 	.enable = waveshare_enable,
154*4882a593Smuzhiyun 	.disable = mipi_dbi_pipe_disable,
155*4882a593Smuzhiyun 	.update = mipi_dbi_pipe_update,
156*4882a593Smuzhiyun 	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun static const struct drm_display_mode waveshare_mode = {
160*4882a593Smuzhiyun 	DRM_SIMPLE_MODE(480, 320, 73, 49),
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun DEFINE_DRM_GEM_CMA_FOPS(ili9486_fops);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun static struct drm_driver ili9486_driver = {
166*4882a593Smuzhiyun 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
167*4882a593Smuzhiyun 	.fops			= &ili9486_fops,
168*4882a593Smuzhiyun 	DRM_GEM_CMA_DRIVER_OPS_VMAP,
169*4882a593Smuzhiyun 	.debugfs_init		= mipi_dbi_debugfs_init,
170*4882a593Smuzhiyun 	.name			= "ili9486",
171*4882a593Smuzhiyun 	.desc			= "Ilitek ILI9486",
172*4882a593Smuzhiyun 	.date			= "20200118",
173*4882a593Smuzhiyun 	.major			= 1,
174*4882a593Smuzhiyun 	.minor			= 0,
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun static const struct of_device_id ili9486_of_match[] = {
178*4882a593Smuzhiyun 	{ .compatible = "waveshare,rpi-lcd-35" },
179*4882a593Smuzhiyun 	{ .compatible = "ozzmaker,piscreen" },
180*4882a593Smuzhiyun 	{},
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ili9486_of_match);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun static const struct spi_device_id ili9486_id[] = {
185*4882a593Smuzhiyun 	{ "ili9486", 0 },
186*4882a593Smuzhiyun 	{ }
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ili9486_id);
189*4882a593Smuzhiyun 
ili9486_probe(struct spi_device * spi)190*4882a593Smuzhiyun static int ili9486_probe(struct spi_device *spi)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun 	struct device *dev = &spi->dev;
193*4882a593Smuzhiyun 	struct mipi_dbi_dev *dbidev;
194*4882a593Smuzhiyun 	struct drm_device *drm;
195*4882a593Smuzhiyun 	struct mipi_dbi *dbi;
196*4882a593Smuzhiyun 	struct gpio_desc *dc;
197*4882a593Smuzhiyun 	u32 rotation = 0;
198*4882a593Smuzhiyun 	int ret;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	dbidev = devm_drm_dev_alloc(dev, &ili9486_driver,
201*4882a593Smuzhiyun 				    struct mipi_dbi_dev, drm);
202*4882a593Smuzhiyun 	if (IS_ERR(dbidev))
203*4882a593Smuzhiyun 		return PTR_ERR(dbidev);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	dbi = &dbidev->dbi;
206*4882a593Smuzhiyun 	drm = &dbidev->drm;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
209*4882a593Smuzhiyun 	if (IS_ERR(dbi->reset)) {
210*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
211*4882a593Smuzhiyun 		return PTR_ERR(dbi->reset);
212*4882a593Smuzhiyun 	}
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
215*4882a593Smuzhiyun 	if (IS_ERR(dc)) {
216*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
217*4882a593Smuzhiyun 		return PTR_ERR(dc);
218*4882a593Smuzhiyun 	}
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	dbidev->backlight = devm_of_find_backlight(dev);
221*4882a593Smuzhiyun 	if (IS_ERR(dbidev->backlight))
222*4882a593Smuzhiyun 		return PTR_ERR(dbidev->backlight);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	device_property_read_u32(dev, "rotation", &rotation);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	ret = mipi_dbi_spi_init(spi, dbi, dc);
227*4882a593Smuzhiyun 	if (ret)
228*4882a593Smuzhiyun 		return ret;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	dbi->command = waveshare_command;
231*4882a593Smuzhiyun 	dbi->read_commands = NULL;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	ret = mipi_dbi_dev_init(dbidev, &waveshare_pipe_funcs,
234*4882a593Smuzhiyun 				&waveshare_mode, rotation);
235*4882a593Smuzhiyun 	if (ret)
236*4882a593Smuzhiyun 		return ret;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	drm_mode_config_reset(drm);
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	ret = drm_dev_register(drm, 0);
241*4882a593Smuzhiyun 	if (ret)
242*4882a593Smuzhiyun 		return ret;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	spi_set_drvdata(spi, drm);
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	drm_fbdev_generic_setup(drm, 0);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	return 0;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun 
ili9486_remove(struct spi_device * spi)251*4882a593Smuzhiyun static int ili9486_remove(struct spi_device *spi)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun 	struct drm_device *drm = spi_get_drvdata(spi);
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	drm_dev_unplug(drm);
256*4882a593Smuzhiyun 	drm_atomic_helper_shutdown(drm);
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	return 0;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun 
ili9486_shutdown(struct spi_device * spi)261*4882a593Smuzhiyun static void ili9486_shutdown(struct spi_device *spi)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun 	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun static struct spi_driver ili9486_spi_driver = {
267*4882a593Smuzhiyun 	.driver = {
268*4882a593Smuzhiyun 		.name = "ili9486",
269*4882a593Smuzhiyun 		.of_match_table = ili9486_of_match,
270*4882a593Smuzhiyun 	},
271*4882a593Smuzhiyun 	.id_table = ili9486_id,
272*4882a593Smuzhiyun 	.probe = ili9486_probe,
273*4882a593Smuzhiyun 	.remove = ili9486_remove,
274*4882a593Smuzhiyun 	.shutdown = ili9486_shutdown,
275*4882a593Smuzhiyun };
276*4882a593Smuzhiyun module_spi_driver(ili9486_spi_driver);
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun MODULE_DESCRIPTION("Ilitek ILI9486 DRM driver");
279*4882a593Smuzhiyun MODULE_AUTHOR("Kamlesh Gurudasani <kamlesh.gurudasani@gmail.com>");
280*4882a593Smuzhiyun MODULE_LICENSE("GPL");
281