1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * DRM driver for Ilitek ILI9341 panels
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2018 David Lechner <david@lechnology.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on mi0283qt.c:
8*4882a593Smuzhiyun * Copyright 2016 Noralf Trønnes
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/backlight.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/property.h>
16*4882a593Smuzhiyun #include <linux/spi/spi.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
19*4882a593Smuzhiyun #include <drm/drm_drv.h>
20*4882a593Smuzhiyun #include <drm/drm_fb_helper.h>
21*4882a593Smuzhiyun #include <drm/drm_gem_cma_helper.h>
22*4882a593Smuzhiyun #include <drm/drm_gem_framebuffer_helper.h>
23*4882a593Smuzhiyun #include <drm/drm_managed.h>
24*4882a593Smuzhiyun #include <drm/drm_mipi_dbi.h>
25*4882a593Smuzhiyun #include <drm/drm_modeset_helper.h>
26*4882a593Smuzhiyun #include <video/mipi_display.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define ILI9341_FRMCTR1 0xb1
29*4882a593Smuzhiyun #define ILI9341_DISCTRL 0xb6
30*4882a593Smuzhiyun #define ILI9341_ETMOD 0xb7
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define ILI9341_PWCTRL1 0xc0
33*4882a593Smuzhiyun #define ILI9341_PWCTRL2 0xc1
34*4882a593Smuzhiyun #define ILI9341_VMCTRL1 0xc5
35*4882a593Smuzhiyun #define ILI9341_VMCTRL2 0xc7
36*4882a593Smuzhiyun #define ILI9341_PWCTRLA 0xcb
37*4882a593Smuzhiyun #define ILI9341_PWCTRLB 0xcf
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define ILI9341_PGAMCTRL 0xe0
40*4882a593Smuzhiyun #define ILI9341_NGAMCTRL 0xe1
41*4882a593Smuzhiyun #define ILI9341_DTCTRLA 0xe8
42*4882a593Smuzhiyun #define ILI9341_DTCTRLB 0xea
43*4882a593Smuzhiyun #define ILI9341_PWRSEQ 0xed
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define ILI9341_EN3GAM 0xf2
46*4882a593Smuzhiyun #define ILI9341_PUMPCTRL 0xf7
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define ILI9341_MADCTL_BGR BIT(3)
49*4882a593Smuzhiyun #define ILI9341_MADCTL_MV BIT(5)
50*4882a593Smuzhiyun #define ILI9341_MADCTL_MX BIT(6)
51*4882a593Smuzhiyun #define ILI9341_MADCTL_MY BIT(7)
52*4882a593Smuzhiyun
yx240qv29_enable(struct drm_simple_display_pipe * pipe,struct drm_crtc_state * crtc_state,struct drm_plane_state * plane_state)53*4882a593Smuzhiyun static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
54*4882a593Smuzhiyun struct drm_crtc_state *crtc_state,
55*4882a593Smuzhiyun struct drm_plane_state *plane_state)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
58*4882a593Smuzhiyun struct mipi_dbi *dbi = &dbidev->dbi;
59*4882a593Smuzhiyun u8 addr_mode;
60*4882a593Smuzhiyun int ret, idx;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (!drm_dev_enter(pipe->crtc.dev, &idx))
63*4882a593Smuzhiyun return;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun DRM_DEBUG_KMS("\n");
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun ret = mipi_dbi_poweron_conditional_reset(dbidev);
68*4882a593Smuzhiyun if (ret < 0)
69*4882a593Smuzhiyun goto out_exit;
70*4882a593Smuzhiyun if (ret == 1)
71*4882a593Smuzhiyun goto out_enable;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_PWCTRLB, 0x00, 0xc1, 0x30);
76*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_PWRSEQ, 0x64, 0x03, 0x12, 0x81);
77*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_DTCTRLA, 0x85, 0x00, 0x78);
78*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_PWCTRLA, 0x39, 0x2c, 0x00, 0x34, 0x02);
79*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_PUMPCTRL, 0x20);
80*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_DTCTRLB, 0x00, 0x00);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Power Control */
83*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_PWCTRL1, 0x23);
84*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_PWCTRL2, 0x10);
85*4882a593Smuzhiyun /* VCOM */
86*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_VMCTRL1, 0x3e, 0x28);
87*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_VMCTRL2, 0x86);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* Memory Access Control */
90*4882a593Smuzhiyun mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* Frame Rate */
93*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_FRMCTR1, 0x00, 0x1b);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* Gamma */
96*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_EN3GAM, 0x00);
97*4882a593Smuzhiyun mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x01);
98*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_PGAMCTRL,
99*4882a593Smuzhiyun 0x0f, 0x31, 0x2b, 0x0c, 0x0e, 0x08, 0x4e, 0xf1,
100*4882a593Smuzhiyun 0x37, 0x07, 0x10, 0x03, 0x0e, 0x09, 0x00);
101*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_NGAMCTRL,
102*4882a593Smuzhiyun 0x00, 0x0e, 0x14, 0x03, 0x11, 0x07, 0x31, 0xc1,
103*4882a593Smuzhiyun 0x48, 0x08, 0x0f, 0x0c, 0x31, 0x36, 0x0f);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* DDRAM */
106*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_ETMOD, 0x07);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* Display */
109*4882a593Smuzhiyun mipi_dbi_command(dbi, ILI9341_DISCTRL, 0x08, 0x82, 0x27, 0x00);
110*4882a593Smuzhiyun mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
111*4882a593Smuzhiyun msleep(100);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
114*4882a593Smuzhiyun msleep(100);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun out_enable:
117*4882a593Smuzhiyun switch (dbidev->rotation) {
118*4882a593Smuzhiyun default:
119*4882a593Smuzhiyun addr_mode = ILI9341_MADCTL_MX;
120*4882a593Smuzhiyun break;
121*4882a593Smuzhiyun case 90:
122*4882a593Smuzhiyun addr_mode = ILI9341_MADCTL_MV;
123*4882a593Smuzhiyun break;
124*4882a593Smuzhiyun case 180:
125*4882a593Smuzhiyun addr_mode = ILI9341_MADCTL_MY;
126*4882a593Smuzhiyun break;
127*4882a593Smuzhiyun case 270:
128*4882a593Smuzhiyun addr_mode = ILI9341_MADCTL_MV | ILI9341_MADCTL_MY |
129*4882a593Smuzhiyun ILI9341_MADCTL_MX;
130*4882a593Smuzhiyun break;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun addr_mode |= ILI9341_MADCTL_BGR;
133*4882a593Smuzhiyun mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
134*4882a593Smuzhiyun mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
135*4882a593Smuzhiyun out_exit:
136*4882a593Smuzhiyun drm_dev_exit(idx);
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun static const struct drm_simple_display_pipe_funcs ili9341_pipe_funcs = {
140*4882a593Smuzhiyun .enable = yx240qv29_enable,
141*4882a593Smuzhiyun .disable = mipi_dbi_pipe_disable,
142*4882a593Smuzhiyun .update = mipi_dbi_pipe_update,
143*4882a593Smuzhiyun .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun static const struct drm_display_mode yx240qv29_mode = {
147*4882a593Smuzhiyun DRM_SIMPLE_MODE(240, 320, 37, 49),
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun DEFINE_DRM_GEM_CMA_FOPS(ili9341_fops);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun static struct drm_driver ili9341_driver = {
153*4882a593Smuzhiyun .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
154*4882a593Smuzhiyun .fops = &ili9341_fops,
155*4882a593Smuzhiyun DRM_GEM_CMA_DRIVER_OPS_VMAP,
156*4882a593Smuzhiyun .debugfs_init = mipi_dbi_debugfs_init,
157*4882a593Smuzhiyun .name = "ili9341",
158*4882a593Smuzhiyun .desc = "Ilitek ILI9341",
159*4882a593Smuzhiyun .date = "20180514",
160*4882a593Smuzhiyun .major = 1,
161*4882a593Smuzhiyun .minor = 0,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun static const struct of_device_id ili9341_of_match[] = {
165*4882a593Smuzhiyun { .compatible = "adafruit,yx240qv29" },
166*4882a593Smuzhiyun { }
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ili9341_of_match);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static const struct spi_device_id ili9341_id[] = {
171*4882a593Smuzhiyun { "yx240qv29", 0 },
172*4882a593Smuzhiyun { }
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ili9341_id);
175*4882a593Smuzhiyun
ili9341_probe(struct spi_device * spi)176*4882a593Smuzhiyun static int ili9341_probe(struct spi_device *spi)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun struct device *dev = &spi->dev;
179*4882a593Smuzhiyun struct mipi_dbi_dev *dbidev;
180*4882a593Smuzhiyun struct drm_device *drm;
181*4882a593Smuzhiyun struct mipi_dbi *dbi;
182*4882a593Smuzhiyun struct gpio_desc *dc;
183*4882a593Smuzhiyun u32 rotation = 0;
184*4882a593Smuzhiyun int ret;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun dbidev = devm_drm_dev_alloc(dev, &ili9341_driver,
187*4882a593Smuzhiyun struct mipi_dbi_dev, drm);
188*4882a593Smuzhiyun if (IS_ERR(dbidev))
189*4882a593Smuzhiyun return PTR_ERR(dbidev);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun dbi = &dbidev->dbi;
192*4882a593Smuzhiyun drm = &dbidev->drm;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun dbi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
195*4882a593Smuzhiyun if (IS_ERR(dbi->reset)) {
196*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
197*4882a593Smuzhiyun return PTR_ERR(dbi->reset);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
201*4882a593Smuzhiyun if (IS_ERR(dc)) {
202*4882a593Smuzhiyun DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
203*4882a593Smuzhiyun return PTR_ERR(dc);
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun dbidev->backlight = devm_of_find_backlight(dev);
207*4882a593Smuzhiyun if (IS_ERR(dbidev->backlight))
208*4882a593Smuzhiyun return PTR_ERR(dbidev->backlight);
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun device_property_read_u32(dev, "rotation", &rotation);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun ret = mipi_dbi_spi_init(spi, dbi, dc);
213*4882a593Smuzhiyun if (ret)
214*4882a593Smuzhiyun return ret;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun ret = mipi_dbi_dev_init(dbidev, &ili9341_pipe_funcs, &yx240qv29_mode, rotation);
217*4882a593Smuzhiyun if (ret)
218*4882a593Smuzhiyun return ret;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun drm_mode_config_reset(drm);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun ret = drm_dev_register(drm, 0);
223*4882a593Smuzhiyun if (ret)
224*4882a593Smuzhiyun return ret;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun spi_set_drvdata(spi, drm);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun drm_fbdev_generic_setup(drm, 0);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun return 0;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
ili9341_remove(struct spi_device * spi)233*4882a593Smuzhiyun static int ili9341_remove(struct spi_device *spi)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun struct drm_device *drm = spi_get_drvdata(spi);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun drm_dev_unplug(drm);
238*4882a593Smuzhiyun drm_atomic_helper_shutdown(drm);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun return 0;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
ili9341_shutdown(struct spi_device * spi)243*4882a593Smuzhiyun static void ili9341_shutdown(struct spi_device *spi)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun drm_atomic_helper_shutdown(spi_get_drvdata(spi));
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun static struct spi_driver ili9341_spi_driver = {
249*4882a593Smuzhiyun .driver = {
250*4882a593Smuzhiyun .name = "ili9341",
251*4882a593Smuzhiyun .of_match_table = ili9341_of_match,
252*4882a593Smuzhiyun },
253*4882a593Smuzhiyun .id_table = ili9341_id,
254*4882a593Smuzhiyun .probe = ili9341_probe,
255*4882a593Smuzhiyun .remove = ili9341_remove,
256*4882a593Smuzhiyun .shutdown = ili9341_shutdown,
257*4882a593Smuzhiyun };
258*4882a593Smuzhiyun module_spi_driver(ili9341_spi_driver);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun MODULE_DESCRIPTION("Ilitek ILI9341 DRM driver");
261*4882a593Smuzhiyun MODULE_AUTHOR("David Lechner <david@lechnology.com>");
262*4882a593Smuzhiyun MODULE_LICENSE("GPL");
263