xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/tiny/hx8357d.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * DRM driver for the HX8357D LCD controller
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2018 Broadcom
6*4882a593Smuzhiyun  * Copyright 2018 David Lechner <david@lechnology.com>
7*4882a593Smuzhiyun  * Copyright 2016 Noralf Trønnes
8*4882a593Smuzhiyun  * Copyright (C) 2015 Adafruit Industries
9*4882a593Smuzhiyun  * Copyright (C) 2013 Christian Vogelgsang
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/backlight.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/property.h>
17*4882a593Smuzhiyun #include <linux/spi/spi.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
20*4882a593Smuzhiyun #include <drm/drm_drv.h>
21*4882a593Smuzhiyun #include <drm/drm_fb_helper.h>
22*4882a593Smuzhiyun #include <drm/drm_gem_cma_helper.h>
23*4882a593Smuzhiyun #include <drm/drm_gem_framebuffer_helper.h>
24*4882a593Smuzhiyun #include <drm/drm_managed.h>
25*4882a593Smuzhiyun #include <drm/drm_mipi_dbi.h>
26*4882a593Smuzhiyun #include <drm/drm_modeset_helper.h>
27*4882a593Smuzhiyun #include <video/mipi_display.h>
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define HX8357D_SETOSC 0xb0
30*4882a593Smuzhiyun #define HX8357D_SETPOWER 0xb1
31*4882a593Smuzhiyun #define HX8357D_SETRGB 0xb3
32*4882a593Smuzhiyun #define HX8357D_SETCYC 0xb3
33*4882a593Smuzhiyun #define HX8357D_SETCOM 0xb6
34*4882a593Smuzhiyun #define HX8357D_SETEXTC 0xb9
35*4882a593Smuzhiyun #define HX8357D_SETSTBA 0xc0
36*4882a593Smuzhiyun #define HX8357D_SETPANEL 0xcc
37*4882a593Smuzhiyun #define HX8357D_SETGAMMA 0xe0
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define HX8357D_MADCTL_MY  0x80
40*4882a593Smuzhiyun #define HX8357D_MADCTL_MX  0x40
41*4882a593Smuzhiyun #define HX8357D_MADCTL_MV  0x20
42*4882a593Smuzhiyun #define HX8357D_MADCTL_ML  0x10
43*4882a593Smuzhiyun #define HX8357D_MADCTL_RGB 0x00
44*4882a593Smuzhiyun #define HX8357D_MADCTL_BGR 0x08
45*4882a593Smuzhiyun #define HX8357D_MADCTL_MH  0x04
46*4882a593Smuzhiyun 
yx240qv29_enable(struct drm_simple_display_pipe * pipe,struct drm_crtc_state * crtc_state,struct drm_plane_state * plane_state)47*4882a593Smuzhiyun static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
48*4882a593Smuzhiyun 			     struct drm_crtc_state *crtc_state,
49*4882a593Smuzhiyun 			     struct drm_plane_state *plane_state)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
52*4882a593Smuzhiyun 	struct mipi_dbi *dbi = &dbidev->dbi;
53*4882a593Smuzhiyun 	u8 addr_mode;
54*4882a593Smuzhiyun 	int ret, idx;
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	if (!drm_dev_enter(pipe->crtc.dev, &idx))
57*4882a593Smuzhiyun 		return;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	DRM_DEBUG_KMS("\n");
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	ret = mipi_dbi_poweron_conditional_reset(dbidev);
62*4882a593Smuzhiyun 	if (ret < 0)
63*4882a593Smuzhiyun 		goto out_exit;
64*4882a593Smuzhiyun 	if (ret == 1)
65*4882a593Smuzhiyun 		goto out_enable;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	/* setextc */
68*4882a593Smuzhiyun 	mipi_dbi_command(dbi, HX8357D_SETEXTC, 0xFF, 0x83, 0x57);
69*4882a593Smuzhiyun 	msleep(150);
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	/* setRGB which also enables SDO */
72*4882a593Smuzhiyun 	mipi_dbi_command(dbi, HX8357D_SETRGB, 0x00, 0x00, 0x06, 0x06);
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	/* -1.52V */
75*4882a593Smuzhiyun 	mipi_dbi_command(dbi, HX8357D_SETCOM, 0x25);
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	/* Normal mode 70Hz, Idle mode 55 Hz */
78*4882a593Smuzhiyun 	mipi_dbi_command(dbi, HX8357D_SETOSC, 0x68);
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/* Set Panel - BGR, Gate direction swapped */
81*4882a593Smuzhiyun 	mipi_dbi_command(dbi, HX8357D_SETPANEL, 0x05);
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	mipi_dbi_command(dbi, HX8357D_SETPOWER,
84*4882a593Smuzhiyun 			 0x00,  /* Not deep standby */
85*4882a593Smuzhiyun 			 0x15,  /* BT */
86*4882a593Smuzhiyun 			 0x1C,  /* VSPR */
87*4882a593Smuzhiyun 			 0x1C,  /* VSNR */
88*4882a593Smuzhiyun 			 0x83,  /* AP */
89*4882a593Smuzhiyun 			 0xAA);  /* FS */
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	mipi_dbi_command(dbi, HX8357D_SETSTBA,
92*4882a593Smuzhiyun 			 0x50,  /* OPON normal */
93*4882a593Smuzhiyun 			 0x50,  /* OPON idle */
94*4882a593Smuzhiyun 			 0x01,  /* STBA */
95*4882a593Smuzhiyun 			 0x3C,  /* STBA */
96*4882a593Smuzhiyun 			 0x1E,  /* STBA */
97*4882a593Smuzhiyun 			 0x08);  /* GEN */
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	mipi_dbi_command(dbi, HX8357D_SETCYC,
100*4882a593Smuzhiyun 			 0x02,  /* NW 0x02 */
101*4882a593Smuzhiyun 			 0x40,  /* RTN */
102*4882a593Smuzhiyun 			 0x00,  /* DIV */
103*4882a593Smuzhiyun 			 0x2A,  /* DUM */
104*4882a593Smuzhiyun 			 0x2A,  /* DUM */
105*4882a593Smuzhiyun 			 0x0D,  /* GDON */
106*4882a593Smuzhiyun 			 0x78);  /* GDOFF */
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	mipi_dbi_command(dbi, HX8357D_SETGAMMA,
109*4882a593Smuzhiyun 			 0x02,
110*4882a593Smuzhiyun 			 0x0A,
111*4882a593Smuzhiyun 			 0x11,
112*4882a593Smuzhiyun 			 0x1d,
113*4882a593Smuzhiyun 			 0x23,
114*4882a593Smuzhiyun 			 0x35,
115*4882a593Smuzhiyun 			 0x41,
116*4882a593Smuzhiyun 			 0x4b,
117*4882a593Smuzhiyun 			 0x4b,
118*4882a593Smuzhiyun 			 0x42,
119*4882a593Smuzhiyun 			 0x3A,
120*4882a593Smuzhiyun 			 0x27,
121*4882a593Smuzhiyun 			 0x1B,
122*4882a593Smuzhiyun 			 0x08,
123*4882a593Smuzhiyun 			 0x09,
124*4882a593Smuzhiyun 			 0x03,
125*4882a593Smuzhiyun 			 0x02,
126*4882a593Smuzhiyun 			 0x0A,
127*4882a593Smuzhiyun 			 0x11,
128*4882a593Smuzhiyun 			 0x1d,
129*4882a593Smuzhiyun 			 0x23,
130*4882a593Smuzhiyun 			 0x35,
131*4882a593Smuzhiyun 			 0x41,
132*4882a593Smuzhiyun 			 0x4b,
133*4882a593Smuzhiyun 			 0x4b,
134*4882a593Smuzhiyun 			 0x42,
135*4882a593Smuzhiyun 			 0x3A,
136*4882a593Smuzhiyun 			 0x27,
137*4882a593Smuzhiyun 			 0x1B,
138*4882a593Smuzhiyun 			 0x08,
139*4882a593Smuzhiyun 			 0x09,
140*4882a593Smuzhiyun 			 0x03,
141*4882a593Smuzhiyun 			 0x00,
142*4882a593Smuzhiyun 			 0x01);
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	/* 16 bit */
145*4882a593Smuzhiyun 	mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT,
146*4882a593Smuzhiyun 			 MIPI_DCS_PIXEL_FMT_16BIT);
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	/* TE off */
149*4882a593Smuzhiyun 	mipi_dbi_command(dbi, MIPI_DCS_SET_TEAR_ON, 0x00);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	/* tear line */
152*4882a593Smuzhiyun 	mipi_dbi_command(dbi, MIPI_DCS_SET_TEAR_SCANLINE, 0x00, 0x02);
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	/* Exit Sleep */
155*4882a593Smuzhiyun 	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
156*4882a593Smuzhiyun 	msleep(150);
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	/* display on */
159*4882a593Smuzhiyun 	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
160*4882a593Smuzhiyun 	usleep_range(5000, 7000);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun out_enable:
163*4882a593Smuzhiyun 	switch (dbidev->rotation) {
164*4882a593Smuzhiyun 	default:
165*4882a593Smuzhiyun 		addr_mode = HX8357D_MADCTL_MX | HX8357D_MADCTL_MY;
166*4882a593Smuzhiyun 		break;
167*4882a593Smuzhiyun 	case 90:
168*4882a593Smuzhiyun 		addr_mode = HX8357D_MADCTL_MV | HX8357D_MADCTL_MY;
169*4882a593Smuzhiyun 		break;
170*4882a593Smuzhiyun 	case 180:
171*4882a593Smuzhiyun 		addr_mode = 0;
172*4882a593Smuzhiyun 		break;
173*4882a593Smuzhiyun 	case 270:
174*4882a593Smuzhiyun 		addr_mode = HX8357D_MADCTL_MV | HX8357D_MADCTL_MX;
175*4882a593Smuzhiyun 		break;
176*4882a593Smuzhiyun 	}
177*4882a593Smuzhiyun 	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
178*4882a593Smuzhiyun 	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
179*4882a593Smuzhiyun out_exit:
180*4882a593Smuzhiyun 	drm_dev_exit(idx);
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun static const struct drm_simple_display_pipe_funcs hx8357d_pipe_funcs = {
184*4882a593Smuzhiyun 	.enable = yx240qv29_enable,
185*4882a593Smuzhiyun 	.disable = mipi_dbi_pipe_disable,
186*4882a593Smuzhiyun 	.update = mipi_dbi_pipe_update,
187*4882a593Smuzhiyun 	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static const struct drm_display_mode yx350hv15_mode = {
191*4882a593Smuzhiyun 	DRM_SIMPLE_MODE(320, 480, 60, 75),
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun DEFINE_DRM_GEM_CMA_FOPS(hx8357d_fops);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun static struct drm_driver hx8357d_driver = {
197*4882a593Smuzhiyun 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
198*4882a593Smuzhiyun 	.fops			= &hx8357d_fops,
199*4882a593Smuzhiyun 	DRM_GEM_CMA_DRIVER_OPS_VMAP,
200*4882a593Smuzhiyun 	.debugfs_init		= mipi_dbi_debugfs_init,
201*4882a593Smuzhiyun 	.name			= "hx8357d",
202*4882a593Smuzhiyun 	.desc			= "HX8357D",
203*4882a593Smuzhiyun 	.date			= "20181023",
204*4882a593Smuzhiyun 	.major			= 1,
205*4882a593Smuzhiyun 	.minor			= 0,
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static const struct of_device_id hx8357d_of_match[] = {
209*4882a593Smuzhiyun 	{ .compatible = "adafruit,yx350hv15" },
210*4882a593Smuzhiyun 	{ }
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, hx8357d_of_match);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun static const struct spi_device_id hx8357d_id[] = {
215*4882a593Smuzhiyun 	{ "yx350hv15", 0 },
216*4882a593Smuzhiyun 	{ }
217*4882a593Smuzhiyun };
218*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, hx8357d_id);
219*4882a593Smuzhiyun 
hx8357d_probe(struct spi_device * spi)220*4882a593Smuzhiyun static int hx8357d_probe(struct spi_device *spi)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun 	struct device *dev = &spi->dev;
223*4882a593Smuzhiyun 	struct mipi_dbi_dev *dbidev;
224*4882a593Smuzhiyun 	struct drm_device *drm;
225*4882a593Smuzhiyun 	struct gpio_desc *dc;
226*4882a593Smuzhiyun 	u32 rotation = 0;
227*4882a593Smuzhiyun 	int ret;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	dbidev = devm_drm_dev_alloc(dev, &hx8357d_driver,
230*4882a593Smuzhiyun 				    struct mipi_dbi_dev, drm);
231*4882a593Smuzhiyun 	if (IS_ERR(dbidev))
232*4882a593Smuzhiyun 		return PTR_ERR(dbidev);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	drm = &dbidev->drm;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
237*4882a593Smuzhiyun 	if (IS_ERR(dc)) {
238*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
239*4882a593Smuzhiyun 		return PTR_ERR(dc);
240*4882a593Smuzhiyun 	}
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	dbidev->backlight = devm_of_find_backlight(dev);
243*4882a593Smuzhiyun 	if (IS_ERR(dbidev->backlight))
244*4882a593Smuzhiyun 		return PTR_ERR(dbidev->backlight);
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	device_property_read_u32(dev, "rotation", &rotation);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	ret = mipi_dbi_spi_init(spi, &dbidev->dbi, dc);
249*4882a593Smuzhiyun 	if (ret)
250*4882a593Smuzhiyun 		return ret;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	ret = mipi_dbi_dev_init(dbidev, &hx8357d_pipe_funcs, &yx350hv15_mode, rotation);
253*4882a593Smuzhiyun 	if (ret)
254*4882a593Smuzhiyun 		return ret;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	drm_mode_config_reset(drm);
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	ret = drm_dev_register(drm, 0);
259*4882a593Smuzhiyun 	if (ret)
260*4882a593Smuzhiyun 		return ret;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	spi_set_drvdata(spi, drm);
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	drm_fbdev_generic_setup(drm, 0);
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	return 0;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun 
hx8357d_remove(struct spi_device * spi)269*4882a593Smuzhiyun static int hx8357d_remove(struct spi_device *spi)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun 	struct drm_device *drm = spi_get_drvdata(spi);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	drm_dev_unplug(drm);
274*4882a593Smuzhiyun 	drm_atomic_helper_shutdown(drm);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	return 0;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun 
hx8357d_shutdown(struct spi_device * spi)279*4882a593Smuzhiyun static void hx8357d_shutdown(struct spi_device *spi)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun 	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun static struct spi_driver hx8357d_spi_driver = {
285*4882a593Smuzhiyun 	.driver = {
286*4882a593Smuzhiyun 		.name = "hx8357d",
287*4882a593Smuzhiyun 		.of_match_table = hx8357d_of_match,
288*4882a593Smuzhiyun 	},
289*4882a593Smuzhiyun 	.id_table = hx8357d_id,
290*4882a593Smuzhiyun 	.probe = hx8357d_probe,
291*4882a593Smuzhiyun 	.remove = hx8357d_remove,
292*4882a593Smuzhiyun 	.shutdown = hx8357d_shutdown,
293*4882a593Smuzhiyun };
294*4882a593Smuzhiyun module_spi_driver(hx8357d_spi_driver);
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun MODULE_DESCRIPTION("HX8357D DRM driver");
297*4882a593Smuzhiyun MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
298*4882a593Smuzhiyun MODULE_LICENSE("GPL");
299