1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments 4*4882a593Smuzhiyun * Author: Rob Clark <robdclark@gmail.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __TILCDC_DRV_H__ 8*4882a593Smuzhiyun #define __TILCDC_DRV_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/cpufreq.h> 11*4882a593Smuzhiyun #include <linux/irqreturn.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <drm/drm_print.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct clk; 16*4882a593Smuzhiyun struct workqueue_struct; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct drm_connector; 19*4882a593Smuzhiyun struct drm_connector_helper_funcs; 20*4882a593Smuzhiyun struct drm_crtc; 21*4882a593Smuzhiyun struct drm_device; 22*4882a593Smuzhiyun struct drm_display_mode; 23*4882a593Smuzhiyun struct drm_encoder; 24*4882a593Smuzhiyun struct drm_framebuffer; 25*4882a593Smuzhiyun struct drm_minor; 26*4882a593Smuzhiyun struct drm_pending_vblank_event; 27*4882a593Smuzhiyun struct drm_plane; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Defaulting to pixel clock defined on AM335x */ 30*4882a593Smuzhiyun #define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000 31*4882a593Smuzhiyun /* Defaulting to max width as defined on AM335x */ 32*4882a593Smuzhiyun #define TILCDC_DEFAULT_MAX_WIDTH 2048 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * This may need some tweaking, but want to allow at least 1280x1024@60 35*4882a593Smuzhiyun * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to 36*4882a593Smuzhiyun * be supportable 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct tilcdc_drm_private { 42*4882a593Smuzhiyun void __iomem *mmio; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct clk *clk; /* functional clock */ 45*4882a593Smuzhiyun int rev; /* IP revision */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* don't attempt resolutions w/ higher W * H * Hz: */ 48*4882a593Smuzhiyun uint32_t max_bandwidth; 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * Pixel Clock will be restricted to some value as 51*4882a593Smuzhiyun * defined in the device datasheet measured in KHz 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun uint32_t max_pixelclock; 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * Max allowable width is limited on a per device basis 56*4882a593Smuzhiyun * measured in pixels 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun uint32_t max_width; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Supported pixel formats */ 61*4882a593Smuzhiyun const uint32_t *pixelformats; 62*4882a593Smuzhiyun uint32_t num_pixelformats; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #ifdef CONFIG_CPU_FREQ 65*4882a593Smuzhiyun struct notifier_block freq_transition; 66*4882a593Smuzhiyun #endif 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct workqueue_struct *wq; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct drm_crtc *crtc; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun unsigned int num_encoders; 73*4882a593Smuzhiyun struct drm_encoder *encoders[8]; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun unsigned int num_connectors; 76*4882a593Smuzhiyun struct drm_connector *connectors[8]; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct drm_encoder *external_encoder; 79*4882a593Smuzhiyun struct drm_connector *external_connector; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun bool is_registered; 82*4882a593Smuzhiyun bool is_componentized; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Sub-module for display. Since we don't know at compile time what panels 86*4882a593Smuzhiyun * or display adapter(s) might be present (for ex, off chip dvi/tfp410, 87*4882a593Smuzhiyun * hdmi encoder, various lcd panels), the connector/encoder(s) are split into 88*4882a593Smuzhiyun * separate drivers. If they are probed and found to be present, they 89*4882a593Smuzhiyun * register themselves with tilcdc_register_module(). 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun struct tilcdc_module; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct tilcdc_module_ops { 94*4882a593Smuzhiyun /* create appropriate encoders/connectors: */ 95*4882a593Smuzhiyun int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev); 96*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS 97*4882a593Smuzhiyun /* create debugfs nodes (can be NULL): */ 98*4882a593Smuzhiyun int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor); 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun struct tilcdc_module { 103*4882a593Smuzhiyun const char *name; 104*4882a593Smuzhiyun struct list_head list; 105*4882a593Smuzhiyun const struct tilcdc_module_ops *funcs; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun void tilcdc_module_init(struct tilcdc_module *mod, const char *name, 109*4882a593Smuzhiyun const struct tilcdc_module_ops *funcs); 110*4882a593Smuzhiyun void tilcdc_module_cleanup(struct tilcdc_module *mod); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* Panel config that needs to be set in the crtc, but is not coming from 113*4882a593Smuzhiyun * the mode timings. The display module is expected to call 114*4882a593Smuzhiyun * tilcdc_crtc_set_panel_info() to set this during modeset. 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun struct tilcdc_panel_info { 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* AC Bias Pin Frequency */ 119*4882a593Smuzhiyun uint32_t ac_bias; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* AC Bias Pin Transitions per Interrupt */ 122*4882a593Smuzhiyun uint32_t ac_bias_intrpt; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* DMA burst size */ 125*4882a593Smuzhiyun uint32_t dma_burst_sz; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* Bits per pixel */ 128*4882a593Smuzhiyun uint32_t bpp; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* FIFO DMA Request Delay */ 131*4882a593Smuzhiyun uint32_t fdd; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* TFT Alternative Signal Mapping (Only for active) */ 134*4882a593Smuzhiyun bool tft_alt_mode; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Invert pixel clock */ 137*4882a593Smuzhiyun bool invert_pxl_clk; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ 140*4882a593Smuzhiyun uint32_t sync_edge; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* Horizontal and Vertical Sync: Control: 0=ignore */ 143*4882a593Smuzhiyun uint32_t sync_ctrl; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ 146*4882a593Smuzhiyun uint32_t raster_order; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* DMA FIFO threshold */ 149*4882a593Smuzhiyun uint32_t fifo_th; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun int tilcdc_crtc_create(struct drm_device *dev); 155*4882a593Smuzhiyun irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc); 156*4882a593Smuzhiyun void tilcdc_crtc_update_clk(struct drm_crtc *crtc); 157*4882a593Smuzhiyun void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 158*4882a593Smuzhiyun const struct tilcdc_panel_info *info); 159*4882a593Smuzhiyun void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, 160*4882a593Smuzhiyun bool simulate_vesa_sync); 161*4882a593Smuzhiyun int tilcdc_crtc_max_width(struct drm_crtc *crtc); 162*4882a593Smuzhiyun void tilcdc_crtc_shutdown(struct drm_crtc *crtc); 163*4882a593Smuzhiyun int tilcdc_crtc_update_fb(struct drm_crtc *crtc, 164*4882a593Smuzhiyun struct drm_framebuffer *fb, 165*4882a593Smuzhiyun struct drm_pending_vblank_event *event); 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane); 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #endif /* __TILCDC_DRV_H__ */ 170