1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
4*4882a593Smuzhiyun * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <drm/drm_atomic.h>
8*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
9*4882a593Smuzhiyun #include <drm/drm_crtc.h>
10*4882a593Smuzhiyun #include <drm/drm_crtc_helper.h>
11*4882a593Smuzhiyun #include <drm/drm_fourcc.h>
12*4882a593Smuzhiyun #include <drm/drm_fb_cma_helper.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "tidss_crtc.h"
15*4882a593Smuzhiyun #include "tidss_dispc.h"
16*4882a593Smuzhiyun #include "tidss_drv.h"
17*4882a593Smuzhiyun #include "tidss_plane.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* drm_plane_helper_funcs */
20*4882a593Smuzhiyun
tidss_plane_atomic_check(struct drm_plane * plane,struct drm_plane_state * state)21*4882a593Smuzhiyun static int tidss_plane_atomic_check(struct drm_plane *plane,
22*4882a593Smuzhiyun struct drm_plane_state *state)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun struct drm_device *ddev = plane->dev;
25*4882a593Smuzhiyun struct tidss_device *tidss = to_tidss(ddev);
26*4882a593Smuzhiyun struct tidss_plane *tplane = to_tidss_plane(plane);
27*4882a593Smuzhiyun const struct drm_format_info *finfo;
28*4882a593Smuzhiyun struct drm_crtc_state *crtc_state;
29*4882a593Smuzhiyun u32 hw_plane = tplane->hw_plane_id;
30*4882a593Smuzhiyun u32 hw_videoport;
31*4882a593Smuzhiyun int ret;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun dev_dbg(ddev->dev, "%s\n", __func__);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun if (!state->crtc) {
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun * The visible field is not reset by the DRM core but only
38*4882a593Smuzhiyun * updated by drm_plane_helper_check_state(), set it manually.
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun state->visible = false;
41*4882a593Smuzhiyun return 0;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
45*4882a593Smuzhiyun if (IS_ERR(crtc_state))
46*4882a593Smuzhiyun return PTR_ERR(crtc_state);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun ret = drm_atomic_helper_check_plane_state(state, crtc_state, 0,
49*4882a593Smuzhiyun INT_MAX, true, true);
50*4882a593Smuzhiyun if (ret < 0)
51*4882a593Smuzhiyun return ret;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * The HW is only able to start drawing at subpixel boundary
55*4882a593Smuzhiyun * (the two first checks bellow). At the end of a row the HW
56*4882a593Smuzhiyun * can only jump integer number of subpixels forward to the
57*4882a593Smuzhiyun * beginning of the next row. So we can only show picture with
58*4882a593Smuzhiyun * integer subpixel width (the third check). However, after
59*4882a593Smuzhiyun * reaching the end of the drawn picture the drawing starts
60*4882a593Smuzhiyun * again at the absolute memory address where top left corner
61*4882a593Smuzhiyun * position of the drawn picture is (so there is no need to
62*4882a593Smuzhiyun * check for odd height).
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun finfo = drm_format_info(state->fb->format->format);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if ((state->src_x >> 16) % finfo->hsub != 0) {
68*4882a593Smuzhiyun dev_dbg(ddev->dev,
69*4882a593Smuzhiyun "%s: x-position %u not divisible subpixel size %u\n",
70*4882a593Smuzhiyun __func__, (state->src_x >> 16), finfo->hsub);
71*4882a593Smuzhiyun return -EINVAL;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun if ((state->src_y >> 16) % finfo->vsub != 0) {
75*4882a593Smuzhiyun dev_dbg(ddev->dev,
76*4882a593Smuzhiyun "%s: y-position %u not divisible subpixel size %u\n",
77*4882a593Smuzhiyun __func__, (state->src_y >> 16), finfo->vsub);
78*4882a593Smuzhiyun return -EINVAL;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if ((state->src_w >> 16) % finfo->hsub != 0) {
82*4882a593Smuzhiyun dev_dbg(ddev->dev,
83*4882a593Smuzhiyun "%s: src width %u not divisible by subpixel size %u\n",
84*4882a593Smuzhiyun __func__, (state->src_w >> 16), finfo->hsub);
85*4882a593Smuzhiyun return -EINVAL;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun if (!state->visible)
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun hw_videoport = to_tidss_crtc(state->crtc)->hw_videoport;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun ret = dispc_plane_check(tidss->dispc, hw_plane, state, hw_videoport);
94*4882a593Smuzhiyun if (ret)
95*4882a593Smuzhiyun return ret;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
tidss_plane_atomic_update(struct drm_plane * plane,struct drm_plane_state * old_state)100*4882a593Smuzhiyun static void tidss_plane_atomic_update(struct drm_plane *plane,
101*4882a593Smuzhiyun struct drm_plane_state *old_state)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun struct drm_device *ddev = plane->dev;
104*4882a593Smuzhiyun struct tidss_device *tidss = to_tidss(ddev);
105*4882a593Smuzhiyun struct tidss_plane *tplane = to_tidss_plane(plane);
106*4882a593Smuzhiyun struct drm_plane_state *state = plane->state;
107*4882a593Smuzhiyun u32 hw_videoport;
108*4882a593Smuzhiyun int ret;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun dev_dbg(ddev->dev, "%s\n", __func__);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun if (!state->visible) {
113*4882a593Smuzhiyun dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
114*4882a593Smuzhiyun return;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun hw_videoport = to_tidss_crtc(state->crtc)->hw_videoport;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun ret = dispc_plane_setup(tidss->dispc, tplane->hw_plane_id,
120*4882a593Smuzhiyun state, hw_videoport);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun if (ret) {
123*4882a593Smuzhiyun dev_err(plane->dev->dev, "%s: Failed to setup plane %d\n",
124*4882a593Smuzhiyun __func__, tplane->hw_plane_id);
125*4882a593Smuzhiyun dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
126*4882a593Smuzhiyun return;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
tidss_plane_atomic_disable(struct drm_plane * plane,struct drm_plane_state * old_state)132*4882a593Smuzhiyun static void tidss_plane_atomic_disable(struct drm_plane *plane,
133*4882a593Smuzhiyun struct drm_plane_state *old_state)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct drm_device *ddev = plane->dev;
136*4882a593Smuzhiyun struct tidss_device *tidss = to_tidss(ddev);
137*4882a593Smuzhiyun struct tidss_plane *tplane = to_tidss_plane(plane);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun dev_dbg(ddev->dev, "%s\n", __func__);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
drm_plane_destroy(struct drm_plane * plane)144*4882a593Smuzhiyun static void drm_plane_destroy(struct drm_plane *plane)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun struct tidss_plane *tplane = to_tidss_plane(plane);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun drm_plane_cleanup(plane);
149*4882a593Smuzhiyun kfree(tplane);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun static const struct drm_plane_helper_funcs tidss_plane_helper_funcs = {
153*4882a593Smuzhiyun .atomic_check = tidss_plane_atomic_check,
154*4882a593Smuzhiyun .atomic_update = tidss_plane_atomic_update,
155*4882a593Smuzhiyun .atomic_disable = tidss_plane_atomic_disable,
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun static const struct drm_plane_funcs tidss_plane_funcs = {
159*4882a593Smuzhiyun .update_plane = drm_atomic_helper_update_plane,
160*4882a593Smuzhiyun .disable_plane = drm_atomic_helper_disable_plane,
161*4882a593Smuzhiyun .reset = drm_atomic_helper_plane_reset,
162*4882a593Smuzhiyun .destroy = drm_plane_destroy,
163*4882a593Smuzhiyun .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
164*4882a593Smuzhiyun .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun
tidss_plane_create(struct tidss_device * tidss,u32 hw_plane_id,u32 plane_type,u32 crtc_mask,const u32 * formats,u32 num_formats)167*4882a593Smuzhiyun struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
168*4882a593Smuzhiyun u32 hw_plane_id, u32 plane_type,
169*4882a593Smuzhiyun u32 crtc_mask, const u32 *formats,
170*4882a593Smuzhiyun u32 num_formats)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun struct tidss_plane *tplane;
173*4882a593Smuzhiyun enum drm_plane_type type;
174*4882a593Smuzhiyun u32 possible_crtcs;
175*4882a593Smuzhiyun u32 num_planes = tidss->feat->num_planes;
176*4882a593Smuzhiyun u32 color_encodings = (BIT(DRM_COLOR_YCBCR_BT601) |
177*4882a593Smuzhiyun BIT(DRM_COLOR_YCBCR_BT709));
178*4882a593Smuzhiyun u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) |
179*4882a593Smuzhiyun BIT(DRM_COLOR_YCBCR_LIMITED_RANGE));
180*4882a593Smuzhiyun u32 default_encoding = DRM_COLOR_YCBCR_BT601;
181*4882a593Smuzhiyun u32 default_range = DRM_COLOR_YCBCR_FULL_RANGE;
182*4882a593Smuzhiyun u32 blend_modes = (BIT(DRM_MODE_BLEND_PREMULTI) |
183*4882a593Smuzhiyun BIT(DRM_MODE_BLEND_COVERAGE));
184*4882a593Smuzhiyun int ret;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun tplane = kzalloc(sizeof(*tplane), GFP_KERNEL);
187*4882a593Smuzhiyun if (!tplane)
188*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun tplane->hw_plane_id = hw_plane_id;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun possible_crtcs = crtc_mask;
193*4882a593Smuzhiyun type = plane_type;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun ret = drm_universal_plane_init(&tidss->ddev, &tplane->plane,
196*4882a593Smuzhiyun possible_crtcs,
197*4882a593Smuzhiyun &tidss_plane_funcs,
198*4882a593Smuzhiyun formats, num_formats,
199*4882a593Smuzhiyun NULL, type, NULL);
200*4882a593Smuzhiyun if (ret < 0)
201*4882a593Smuzhiyun goto err;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun drm_plane_create_zpos_property(&tplane->plane, hw_plane_id, 0,
206*4882a593Smuzhiyun num_planes - 1);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun ret = drm_plane_create_color_properties(&tplane->plane,
209*4882a593Smuzhiyun color_encodings,
210*4882a593Smuzhiyun color_ranges,
211*4882a593Smuzhiyun default_encoding,
212*4882a593Smuzhiyun default_range);
213*4882a593Smuzhiyun if (ret)
214*4882a593Smuzhiyun goto err;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun ret = drm_plane_create_alpha_property(&tplane->plane);
217*4882a593Smuzhiyun if (ret)
218*4882a593Smuzhiyun goto err;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun ret = drm_plane_create_blend_mode_property(&tplane->plane, blend_modes);
221*4882a593Smuzhiyun if (ret)
222*4882a593Smuzhiyun goto err;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun return tplane;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun err:
227*4882a593Smuzhiyun kfree(tplane);
228*4882a593Smuzhiyun return ERR_PTR(ret);
229*4882a593Smuzhiyun }
230