1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
4*4882a593Smuzhiyun * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __TIDSS_IRQ_H__
8*4882a593Smuzhiyun #define __TIDSS_IRQ_H__
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/types.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "tidss_drv.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /*
15*4882a593Smuzhiyun * The IRQ status from various DISPC IRQ registers are packed into a single
16*4882a593Smuzhiyun * value, where the bits are defined as follows:
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * bit group |dev|wb |mrg0|mrg1|mrg2|mrg3|plane0-3| <unused> |
19*4882a593Smuzhiyun * bit use |D |fou|FEOL|FEOL|FEOL|FEOL| UUUU | |
20*4882a593Smuzhiyun * bit number|0 |1-3|4-7 |8-11| 12-19 | 20-23 | 24-31 |
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * device bits: D = OCP error
23*4882a593Smuzhiyun * WB bits: f = frame done wb, o = wb buffer overflow,
24*4882a593Smuzhiyun * u = wb buffer uncomplete
25*4882a593Smuzhiyun * vp bits: F = frame done, E = vsync even, O = vsync odd, L = sync lost
26*4882a593Smuzhiyun * plane bits: U = fifo underflow
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define DSS_IRQ_DEVICE_OCP_ERR BIT(0)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define DSS_IRQ_DEVICE_FRAMEDONEWB BIT(1)
32*4882a593Smuzhiyun #define DSS_IRQ_DEVICE_WBBUFFEROVERFLOW BIT(2)
33*4882a593Smuzhiyun #define DSS_IRQ_DEVICE_WBUNCOMPLETEERROR BIT(3)
34*4882a593Smuzhiyun #define DSS_IRQ_DEVICE_WB_MASK GENMASK(3, 1)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define DSS_IRQ_VP_BIT_N(ch, bit) (4 + 4 * (ch) + (bit))
37*4882a593Smuzhiyun #define DSS_IRQ_PLANE_BIT_N(plane, bit) \
38*4882a593Smuzhiyun (DSS_IRQ_VP_BIT_N(TIDSS_MAX_PORTS, 0) + 1 * (plane) + (bit))
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define DSS_IRQ_VP_BIT(ch, bit) BIT(DSS_IRQ_VP_BIT_N((ch), (bit)))
41*4882a593Smuzhiyun #define DSS_IRQ_PLANE_BIT(plane, bit) \
42*4882a593Smuzhiyun BIT(DSS_IRQ_PLANE_BIT_N((plane), (bit)))
43*4882a593Smuzhiyun
DSS_IRQ_VP_MASK(u32 ch)44*4882a593Smuzhiyun static inline dispc_irq_t DSS_IRQ_VP_MASK(u32 ch)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun return GENMASK(DSS_IRQ_VP_BIT_N((ch), 3), DSS_IRQ_VP_BIT_N((ch), 0));
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
DSS_IRQ_PLANE_MASK(u32 plane)49*4882a593Smuzhiyun static inline dispc_irq_t DSS_IRQ_PLANE_MASK(u32 plane)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun return GENMASK(DSS_IRQ_PLANE_BIT_N((plane), 0),
52*4882a593Smuzhiyun DSS_IRQ_PLANE_BIT_N((plane), 0));
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define DSS_IRQ_VP_FRAME_DONE(ch) DSS_IRQ_VP_BIT((ch), 0)
56*4882a593Smuzhiyun #define DSS_IRQ_VP_VSYNC_EVEN(ch) DSS_IRQ_VP_BIT((ch), 1)
57*4882a593Smuzhiyun #define DSS_IRQ_VP_VSYNC_ODD(ch) DSS_IRQ_VP_BIT((ch), 2)
58*4882a593Smuzhiyun #define DSS_IRQ_VP_SYNC_LOST(ch) DSS_IRQ_VP_BIT((ch), 3)
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define DSS_IRQ_PLANE_FIFO_UNDERFLOW(plane) DSS_IRQ_PLANE_BIT((plane), 0)
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct drm_crtc;
63*4882a593Smuzhiyun struct drm_device;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun struct tidss_device;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun void tidss_irq_enable_vblank(struct drm_crtc *crtc);
68*4882a593Smuzhiyun void tidss_irq_disable_vblank(struct drm_crtc *crtc);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun void tidss_irq_preinstall(struct drm_device *ddev);
71*4882a593Smuzhiyun int tidss_irq_postinstall(struct drm_device *ddev);
72*4882a593Smuzhiyun void tidss_irq_uninstall(struct drm_device *ddev);
73*4882a593Smuzhiyun irqreturn_t tidss_irq_handler(int irq, void *arg);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun void tidss_irq_resume(struct tidss_device *tidss);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #endif
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