xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/tidss/tidss_crtc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
4*4882a593Smuzhiyun  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <drm/drm_atomic.h>
8*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
9*4882a593Smuzhiyun #include <drm/drm_crtc.h>
10*4882a593Smuzhiyun #include <drm/drm_crtc_helper.h>
11*4882a593Smuzhiyun #include <drm/drm_fb_cma_helper.h>
12*4882a593Smuzhiyun #include <drm/drm_gem_cma_helper.h>
13*4882a593Smuzhiyun #include <drm/drm_plane_helper.h>
14*4882a593Smuzhiyun #include <drm/drm_vblank.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include "tidss_crtc.h"
17*4882a593Smuzhiyun #include "tidss_dispc.h"
18*4882a593Smuzhiyun #include "tidss_drv.h"
19*4882a593Smuzhiyun #include "tidss_irq.h"
20*4882a593Smuzhiyun #include "tidss_plane.h"
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* Page flip and frame done IRQs */
23*4882a593Smuzhiyun 
tidss_crtc_finish_page_flip(struct tidss_crtc * tcrtc)24*4882a593Smuzhiyun static void tidss_crtc_finish_page_flip(struct tidss_crtc *tcrtc)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun 	struct drm_device *ddev = tcrtc->crtc.dev;
27*4882a593Smuzhiyun 	struct tidss_device *tidss = to_tidss(ddev);
28*4882a593Smuzhiyun 	struct drm_pending_vblank_event *event;
29*4882a593Smuzhiyun 	unsigned long flags;
30*4882a593Smuzhiyun 	bool busy;
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun 	spin_lock_irqsave(&ddev->event_lock, flags);
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	/*
35*4882a593Smuzhiyun 	 * New settings are taken into use at VFP, and GO bit is cleared at
36*4882a593Smuzhiyun 	 * the same time. This happens before the vertical blank interrupt.
37*4882a593Smuzhiyun 	 * So there is a small change that the driver sets GO bit after VFP, but
38*4882a593Smuzhiyun 	 * before vblank, and we have to check for that case here.
39*4882a593Smuzhiyun 	 */
40*4882a593Smuzhiyun 	busy = dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport);
41*4882a593Smuzhiyun 	if (busy) {
42*4882a593Smuzhiyun 		spin_unlock_irqrestore(&ddev->event_lock, flags);
43*4882a593Smuzhiyun 		return;
44*4882a593Smuzhiyun 	}
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	event = tcrtc->event;
47*4882a593Smuzhiyun 	tcrtc->event = NULL;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	if (!event) {
50*4882a593Smuzhiyun 		spin_unlock_irqrestore(&ddev->event_lock, flags);
51*4882a593Smuzhiyun 		return;
52*4882a593Smuzhiyun 	}
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	drm_crtc_send_vblank_event(&tcrtc->crtc, event);
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ddev->event_lock, flags);
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	drm_crtc_vblank_put(&tcrtc->crtc);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
tidss_crtc_vblank_irq(struct drm_crtc * crtc)61*4882a593Smuzhiyun void tidss_crtc_vblank_irq(struct drm_crtc *crtc)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	drm_crtc_handle_vblank(crtc);
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	tidss_crtc_finish_page_flip(tcrtc);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
tidss_crtc_framedone_irq(struct drm_crtc * crtc)70*4882a593Smuzhiyun void tidss_crtc_framedone_irq(struct drm_crtc *crtc)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	complete(&tcrtc->framedone_completion);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun 
tidss_crtc_error_irq(struct drm_crtc * crtc,u64 irqstatus)77*4882a593Smuzhiyun void tidss_crtc_error_irq(struct drm_crtc *crtc, u64 irqstatus)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun 	struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	dev_err_ratelimited(crtc->dev->dev, "CRTC%u SYNC LOST: (irq %llx)\n",
82*4882a593Smuzhiyun 			    tcrtc->hw_videoport, irqstatus);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun /* drm_crtc_helper_funcs */
86*4882a593Smuzhiyun 
tidss_crtc_atomic_check(struct drm_crtc * crtc,struct drm_crtc_state * state)87*4882a593Smuzhiyun static int tidss_crtc_atomic_check(struct drm_crtc *crtc,
88*4882a593Smuzhiyun 				   struct drm_crtc_state *state)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 	struct drm_device *ddev = crtc->dev;
91*4882a593Smuzhiyun 	struct tidss_device *tidss = to_tidss(ddev);
92*4882a593Smuzhiyun 	struct dispc_device *dispc = tidss->dispc;
93*4882a593Smuzhiyun 	struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
94*4882a593Smuzhiyun 	u32 hw_videoport = tcrtc->hw_videoport;
95*4882a593Smuzhiyun 	const struct drm_display_mode *mode;
96*4882a593Smuzhiyun 	enum drm_mode_status ok;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	dev_dbg(ddev->dev, "%s\n", __func__);
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	if (!state->enable)
101*4882a593Smuzhiyun 		return 0;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	mode = &state->adjusted_mode;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	ok = dispc_vp_mode_valid(dispc, hw_videoport, mode);
106*4882a593Smuzhiyun 	if (ok != MODE_OK) {
107*4882a593Smuzhiyun 		dev_dbg(ddev->dev, "%s: bad mode: %ux%u pclk %u kHz\n",
108*4882a593Smuzhiyun 			__func__, mode->hdisplay, mode->vdisplay, mode->clock);
109*4882a593Smuzhiyun 		return -EINVAL;
110*4882a593Smuzhiyun 	}
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	return dispc_vp_bus_check(dispc, hw_videoport, state);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /*
116*4882a593Smuzhiyun  * This needs all affected planes to be present in the atomic
117*4882a593Smuzhiyun  * state. The untouched planes are added to the state in
118*4882a593Smuzhiyun  * tidss_atomic_check().
119*4882a593Smuzhiyun  */
tidss_crtc_position_planes(struct tidss_device * tidss,struct drm_crtc * crtc,struct drm_crtc_state * old_state,bool newmodeset)120*4882a593Smuzhiyun static void tidss_crtc_position_planes(struct tidss_device *tidss,
121*4882a593Smuzhiyun 				       struct drm_crtc *crtc,
122*4882a593Smuzhiyun 				       struct drm_crtc_state *old_state,
123*4882a593Smuzhiyun 				       bool newmodeset)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	struct drm_atomic_state *ostate = old_state->state;
126*4882a593Smuzhiyun 	struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
127*4882a593Smuzhiyun 	struct drm_crtc_state *cstate = crtc->state;
128*4882a593Smuzhiyun 	int layer;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	if (!newmodeset && !cstate->zpos_changed &&
131*4882a593Smuzhiyun 	    !to_tidss_crtc_state(cstate)->plane_pos_changed)
132*4882a593Smuzhiyun 		return;
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	for (layer = 0; layer < tidss->feat->num_planes; layer++) {
135*4882a593Smuzhiyun 		struct drm_plane_state *pstate;
136*4882a593Smuzhiyun 		struct drm_plane *plane;
137*4882a593Smuzhiyun 		bool layer_active = false;
138*4882a593Smuzhiyun 		int i;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 		for_each_new_plane_in_state(ostate, plane, pstate, i) {
141*4882a593Smuzhiyun 			if (pstate->crtc != crtc || !pstate->visible)
142*4882a593Smuzhiyun 				continue;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 			if (pstate->normalized_zpos == layer) {
145*4882a593Smuzhiyun 				layer_active = true;
146*4882a593Smuzhiyun 				break;
147*4882a593Smuzhiyun 			}
148*4882a593Smuzhiyun 		}
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 		if (layer_active) {
151*4882a593Smuzhiyun 			struct tidss_plane *tplane = to_tidss_plane(plane);
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 			dispc_ovr_set_plane(tidss->dispc, tplane->hw_plane_id,
154*4882a593Smuzhiyun 					    tcrtc->hw_videoport,
155*4882a593Smuzhiyun 					    pstate->crtc_x, pstate->crtc_y,
156*4882a593Smuzhiyun 					    layer);
157*4882a593Smuzhiyun 		}
158*4882a593Smuzhiyun 		dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer,
159*4882a593Smuzhiyun 				       layer_active);
160*4882a593Smuzhiyun 	}
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun 
tidss_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_crtc_state * old_crtc_state)163*4882a593Smuzhiyun static void tidss_crtc_atomic_flush(struct drm_crtc *crtc,
164*4882a593Smuzhiyun 				    struct drm_crtc_state *old_crtc_state)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
167*4882a593Smuzhiyun 	struct drm_device *ddev = crtc->dev;
168*4882a593Smuzhiyun 	struct tidss_device *tidss = to_tidss(ddev);
169*4882a593Smuzhiyun 	unsigned long flags;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	dev_dbg(ddev->dev,
172*4882a593Smuzhiyun 		"%s: %s enabled %d, needs modeset %d, event %p\n", __func__,
173*4882a593Smuzhiyun 		crtc->name, drm_atomic_crtc_needs_modeset(crtc->state),
174*4882a593Smuzhiyun 		crtc->state->enable, crtc->state->event);
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	/* There is nothing to do if CRTC is not going to be enabled. */
177*4882a593Smuzhiyun 	if (!crtc->state->enable)
178*4882a593Smuzhiyun 		return;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	/*
181*4882a593Smuzhiyun 	 * Flush CRTC changes with go bit only if new modeset is not
182*4882a593Smuzhiyun 	 * coming, so CRTC is enabled trough out the commit.
183*4882a593Smuzhiyun 	 */
184*4882a593Smuzhiyun 	if (drm_atomic_crtc_needs_modeset(crtc->state))
185*4882a593Smuzhiyun 		return;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	/* If the GO bit is stuck we better quit here. */
188*4882a593Smuzhiyun 	if (WARN_ON(dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport)))
189*4882a593Smuzhiyun 		return;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	/* We should have event if CRTC is enabled through out this commit. */
192*4882a593Smuzhiyun 	if (WARN_ON(!crtc->state->event))
193*4882a593Smuzhiyun 		return;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	/* Write vp properties to HW if needed. */
196*4882a593Smuzhiyun 	dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, false);
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	/* Update plane positions if needed. */
199*4882a593Smuzhiyun 	tidss_crtc_position_planes(tidss, crtc, old_crtc_state, false);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	WARN_ON(drm_crtc_vblank_get(crtc) != 0);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	spin_lock_irqsave(&ddev->event_lock, flags);
204*4882a593Smuzhiyun 	dispc_vp_go(tidss->dispc, tcrtc->hw_videoport);
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	WARN_ON(tcrtc->event);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	tcrtc->event = crtc->state->event;
209*4882a593Smuzhiyun 	crtc->state->event = NULL;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ddev->event_lock, flags);
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun 
tidss_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)214*4882a593Smuzhiyun static void tidss_crtc_atomic_enable(struct drm_crtc *crtc,
215*4882a593Smuzhiyun 				     struct drm_crtc_state *old_state)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun 	struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
218*4882a593Smuzhiyun 	struct drm_device *ddev = crtc->dev;
219*4882a593Smuzhiyun 	struct tidss_device *tidss = to_tidss(ddev);
220*4882a593Smuzhiyun 	const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
221*4882a593Smuzhiyun 	unsigned long flags;
222*4882a593Smuzhiyun 	int r;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	dev_dbg(ddev->dev, "%s, event %p\n", __func__, crtc->state->event);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	tidss_runtime_get(tidss);
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	r = dispc_vp_set_clk_rate(tidss->dispc, tcrtc->hw_videoport,
229*4882a593Smuzhiyun 				  mode->clock * 1000);
230*4882a593Smuzhiyun 	if (r != 0)
231*4882a593Smuzhiyun 		return;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	r = dispc_vp_enable_clk(tidss->dispc, tcrtc->hw_videoport);
234*4882a593Smuzhiyun 	if (r != 0)
235*4882a593Smuzhiyun 		return;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, true);
238*4882a593Smuzhiyun 	tidss_crtc_position_planes(tidss, crtc, old_state, true);
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	/* Turn vertical blanking interrupt reporting on. */
241*4882a593Smuzhiyun 	drm_crtc_vblank_on(crtc);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	dispc_vp_prepare(tidss->dispc, tcrtc->hw_videoport, crtc->state);
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	dispc_vp_enable(tidss->dispc, tcrtc->hw_videoport, crtc->state);
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	spin_lock_irqsave(&ddev->event_lock, flags);
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	if (crtc->state->event) {
250*4882a593Smuzhiyun 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
251*4882a593Smuzhiyun 		crtc->state->event = NULL;
252*4882a593Smuzhiyun 	}
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ddev->event_lock, flags);
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
tidss_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)257*4882a593Smuzhiyun static void tidss_crtc_atomic_disable(struct drm_crtc *crtc,
258*4882a593Smuzhiyun 				      struct drm_crtc_state *old_state)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun 	struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
261*4882a593Smuzhiyun 	struct drm_device *ddev = crtc->dev;
262*4882a593Smuzhiyun 	struct tidss_device *tidss = to_tidss(ddev);
263*4882a593Smuzhiyun 	unsigned long flags;
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	dev_dbg(ddev->dev, "%s, event %p\n", __func__, crtc->state->event);
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	reinit_completion(&tcrtc->framedone_completion);
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	dispc_vp_disable(tidss->dispc, tcrtc->hw_videoport);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	if (!wait_for_completion_timeout(&tcrtc->framedone_completion,
272*4882a593Smuzhiyun 					 msecs_to_jiffies(500)))
273*4882a593Smuzhiyun 		dev_err(tidss->dev, "Timeout waiting for framedone on crtc %d",
274*4882a593Smuzhiyun 			tcrtc->hw_videoport);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	dispc_vp_unprepare(tidss->dispc, tcrtc->hw_videoport);
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	spin_lock_irqsave(&ddev->event_lock, flags);
279*4882a593Smuzhiyun 	if (crtc->state->event) {
280*4882a593Smuzhiyun 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
281*4882a593Smuzhiyun 		crtc->state->event = NULL;
282*4882a593Smuzhiyun 	}
283*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ddev->event_lock, flags);
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	drm_crtc_vblank_off(crtc);
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	dispc_vp_disable_clk(tidss->dispc, tcrtc->hw_videoport);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	tidss_runtime_put(tidss);
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun static
tidss_crtc_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)293*4882a593Smuzhiyun enum drm_mode_status tidss_crtc_mode_valid(struct drm_crtc *crtc,
294*4882a593Smuzhiyun 					   const struct drm_display_mode *mode)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun 	struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
297*4882a593Smuzhiyun 	struct drm_device *ddev = crtc->dev;
298*4882a593Smuzhiyun 	struct tidss_device *tidss = to_tidss(ddev);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	return dispc_vp_mode_valid(tidss->dispc, tcrtc->hw_videoport, mode);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun static const struct drm_crtc_helper_funcs tidss_crtc_helper_funcs = {
304*4882a593Smuzhiyun 	.atomic_check = tidss_crtc_atomic_check,
305*4882a593Smuzhiyun 	.atomic_flush = tidss_crtc_atomic_flush,
306*4882a593Smuzhiyun 	.atomic_enable = tidss_crtc_atomic_enable,
307*4882a593Smuzhiyun 	.atomic_disable = tidss_crtc_atomic_disable,
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	.mode_valid = tidss_crtc_mode_valid,
310*4882a593Smuzhiyun };
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun /* drm_crtc_funcs */
313*4882a593Smuzhiyun 
tidss_crtc_enable_vblank(struct drm_crtc * crtc)314*4882a593Smuzhiyun static int tidss_crtc_enable_vblank(struct drm_crtc *crtc)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun 	struct drm_device *ddev = crtc->dev;
317*4882a593Smuzhiyun 	struct tidss_device *tidss = to_tidss(ddev);
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	dev_dbg(ddev->dev, "%s\n", __func__);
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	tidss_runtime_get(tidss);
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	tidss_irq_enable_vblank(crtc);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	return 0;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun 
tidss_crtc_disable_vblank(struct drm_crtc * crtc)328*4882a593Smuzhiyun static void tidss_crtc_disable_vblank(struct drm_crtc *crtc)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun 	struct drm_device *ddev = crtc->dev;
331*4882a593Smuzhiyun 	struct tidss_device *tidss = to_tidss(ddev);
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	dev_dbg(ddev->dev, "%s\n", __func__);
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	tidss_irq_disable_vblank(crtc);
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	tidss_runtime_put(tidss);
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun 
tidss_crtc_reset(struct drm_crtc * crtc)340*4882a593Smuzhiyun static void tidss_crtc_reset(struct drm_crtc *crtc)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun 	struct tidss_crtc_state *tcrtc;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	if (crtc->state)
345*4882a593Smuzhiyun 		__drm_atomic_helper_crtc_destroy_state(crtc->state);
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	kfree(crtc->state);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	tcrtc = kzalloc(sizeof(*tcrtc), GFP_KERNEL);
350*4882a593Smuzhiyun 	if (!tcrtc) {
351*4882a593Smuzhiyun 		crtc->state = NULL;
352*4882a593Smuzhiyun 		return;
353*4882a593Smuzhiyun 	}
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	__drm_atomic_helper_crtc_reset(crtc, &tcrtc->base);
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun 
tidss_crtc_duplicate_state(struct drm_crtc * crtc)358*4882a593Smuzhiyun static struct drm_crtc_state *tidss_crtc_duplicate_state(struct drm_crtc *crtc)
359*4882a593Smuzhiyun {
360*4882a593Smuzhiyun 	struct tidss_crtc_state *state, *current_state;
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	if (WARN_ON(!crtc->state))
363*4882a593Smuzhiyun 		return NULL;
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	current_state = to_tidss_crtc_state(crtc->state);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	state = kmalloc(sizeof(*state), GFP_KERNEL);
368*4882a593Smuzhiyun 	if (!state)
369*4882a593Smuzhiyun 		return NULL;
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	state->plane_pos_changed = false;
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	state->bus_format = current_state->bus_format;
376*4882a593Smuzhiyun 	state->bus_flags = current_state->bus_flags;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	return &state->base;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun 
tidss_crtc_destroy(struct drm_crtc * crtc)381*4882a593Smuzhiyun static void tidss_crtc_destroy(struct drm_crtc *crtc)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun 	struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	drm_crtc_cleanup(crtc);
386*4882a593Smuzhiyun 	kfree(tcrtc);
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun static const struct drm_crtc_funcs tidss_crtc_funcs = {
390*4882a593Smuzhiyun 	.reset = tidss_crtc_reset,
391*4882a593Smuzhiyun 	.destroy = tidss_crtc_destroy,
392*4882a593Smuzhiyun 	.set_config = drm_atomic_helper_set_config,
393*4882a593Smuzhiyun 	.page_flip = drm_atomic_helper_page_flip,
394*4882a593Smuzhiyun 	.atomic_duplicate_state = tidss_crtc_duplicate_state,
395*4882a593Smuzhiyun 	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
396*4882a593Smuzhiyun 	.enable_vblank = tidss_crtc_enable_vblank,
397*4882a593Smuzhiyun 	.disable_vblank = tidss_crtc_disable_vblank,
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun 
tidss_crtc_create(struct tidss_device * tidss,u32 hw_videoport,struct drm_plane * primary)400*4882a593Smuzhiyun struct tidss_crtc *tidss_crtc_create(struct tidss_device *tidss,
401*4882a593Smuzhiyun 				     u32 hw_videoport,
402*4882a593Smuzhiyun 				     struct drm_plane *primary)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun 	struct tidss_crtc *tcrtc;
405*4882a593Smuzhiyun 	struct drm_crtc *crtc;
406*4882a593Smuzhiyun 	unsigned int gamma_lut_size = 0;
407*4882a593Smuzhiyun 	bool has_ctm = tidss->feat->vp_feat.color.has_ctm;
408*4882a593Smuzhiyun 	int ret;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	tcrtc = kzalloc(sizeof(*tcrtc), GFP_KERNEL);
411*4882a593Smuzhiyun 	if (!tcrtc)
412*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	tcrtc->hw_videoport = hw_videoport;
415*4882a593Smuzhiyun 	init_completion(&tcrtc->framedone_completion);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	crtc =  &tcrtc->crtc;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	ret = drm_crtc_init_with_planes(&tidss->ddev, crtc, primary,
420*4882a593Smuzhiyun 					NULL, &tidss_crtc_funcs, NULL);
421*4882a593Smuzhiyun 	if (ret < 0) {
422*4882a593Smuzhiyun 		kfree(tcrtc);
423*4882a593Smuzhiyun 		return ERR_PTR(ret);
424*4882a593Smuzhiyun 	}
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	drm_crtc_helper_add(crtc, &tidss_crtc_helper_funcs);
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	/*
429*4882a593Smuzhiyun 	 * The dispc gamma functions adapt to what ever size we ask
430*4882a593Smuzhiyun 	 * from it no matter what HW supports. X-server assumes 256
431*4882a593Smuzhiyun 	 * element gamma tables so lets use that.
432*4882a593Smuzhiyun 	 */
433*4882a593Smuzhiyun 	if (tidss->feat->vp_feat.color.gamma_size)
434*4882a593Smuzhiyun 		gamma_lut_size = 256;
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	drm_crtc_enable_color_mgmt(crtc, 0, has_ctm, gamma_lut_size);
437*4882a593Smuzhiyun 	if (gamma_lut_size)
438*4882a593Smuzhiyun 		drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 	return tcrtc;
441*4882a593Smuzhiyun }
442