xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/tegra/mipi-phy.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2013 NVIDIA Corporation
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef DRM_TEGRA_MIPI_PHY_H
7*4882a593Smuzhiyun #define DRM_TEGRA_MIPI_PHY_H
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun  * D-PHY timing parameters
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * A detailed description of these parameters can be found in the  MIPI
13*4882a593Smuzhiyun  * Alliance Specification for D-PHY, Section 5.9 "Global Operation Timing
14*4882a593Smuzhiyun  * Parameters".
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * All parameters are specified in nanoseconds.
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun struct mipi_dphy_timing {
19*4882a593Smuzhiyun 	unsigned int clkmiss;
20*4882a593Smuzhiyun 	unsigned int clkpost;
21*4882a593Smuzhiyun 	unsigned int clkpre;
22*4882a593Smuzhiyun 	unsigned int clkprepare;
23*4882a593Smuzhiyun 	unsigned int clksettle;
24*4882a593Smuzhiyun 	unsigned int clktermen;
25*4882a593Smuzhiyun 	unsigned int clktrail;
26*4882a593Smuzhiyun 	unsigned int clkzero;
27*4882a593Smuzhiyun 	unsigned int dtermen;
28*4882a593Smuzhiyun 	unsigned int eot;
29*4882a593Smuzhiyun 	unsigned int hsexit;
30*4882a593Smuzhiyun 	unsigned int hsprepare;
31*4882a593Smuzhiyun 	unsigned int hszero;
32*4882a593Smuzhiyun 	unsigned int hssettle;
33*4882a593Smuzhiyun 	unsigned int hsskip;
34*4882a593Smuzhiyun 	unsigned int hstrail;
35*4882a593Smuzhiyun 	unsigned int init;
36*4882a593Smuzhiyun 	unsigned int lpx;
37*4882a593Smuzhiyun 	unsigned int taget;
38*4882a593Smuzhiyun 	unsigned int tago;
39*4882a593Smuzhiyun 	unsigned int tasure;
40*4882a593Smuzhiyun 	unsigned int wakeup;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
44*4882a593Smuzhiyun 				 unsigned long period);
45*4882a593Smuzhiyun int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
46*4882a593Smuzhiyun 			      unsigned long period);
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #endif
49