1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef TEGRA_HUB_H
7*4882a593Smuzhiyun #define TEGRA_HUB_H 1
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <drm/drm_plane.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "plane.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct tegra_dc;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun struct tegra_windowgroup {
16*4882a593Smuzhiyun unsigned int usecount;
17*4882a593Smuzhiyun struct mutex lock;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun unsigned int index;
20*4882a593Smuzhiyun struct host1x_client *parent;
21*4882a593Smuzhiyun struct reset_control *rst;
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct tegra_shared_plane {
25*4882a593Smuzhiyun struct tegra_plane base;
26*4882a593Smuzhiyun struct tegra_windowgroup *wgrp;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static inline struct tegra_shared_plane *
to_tegra_shared_plane(struct drm_plane * plane)30*4882a593Smuzhiyun to_tegra_shared_plane(struct drm_plane *plane)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun return container_of(plane, struct tegra_shared_plane, base.base);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct tegra_display_hub_soc {
36*4882a593Smuzhiyun unsigned int num_wgrps;
37*4882a593Smuzhiyun bool supports_dsc;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct tegra_display_hub {
41*4882a593Smuzhiyun struct drm_private_obj base;
42*4882a593Smuzhiyun struct host1x_client client;
43*4882a593Smuzhiyun struct clk *clk_disp;
44*4882a593Smuzhiyun struct clk *clk_dsc;
45*4882a593Smuzhiyun struct clk *clk_hub;
46*4882a593Smuzhiyun struct reset_control *rst;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun unsigned int num_heads;
49*4882a593Smuzhiyun struct clk **clk_heads;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun const struct tegra_display_hub_soc *soc;
52*4882a593Smuzhiyun struct tegra_windowgroup *wgrps;
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static inline struct tegra_display_hub *
to_tegra_display_hub(struct host1x_client * client)56*4882a593Smuzhiyun to_tegra_display_hub(struct host1x_client *client)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun return container_of(client, struct tegra_display_hub, client);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun struct tegra_display_hub_state {
62*4882a593Smuzhiyun struct drm_private_state base;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct tegra_dc *dc;
65*4882a593Smuzhiyun unsigned long rate;
66*4882a593Smuzhiyun struct clk *clk;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun static inline struct tegra_display_hub_state *
to_tegra_display_hub_state(struct drm_private_state * priv)70*4882a593Smuzhiyun to_tegra_display_hub_state(struct drm_private_state *priv)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun return container_of(priv, struct tegra_display_hub_state, base);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun struct tegra_dc;
76*4882a593Smuzhiyun struct tegra_plane;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun int tegra_display_hub_prepare(struct tegra_display_hub *hub);
79*4882a593Smuzhiyun void tegra_display_hub_cleanup(struct tegra_display_hub *hub);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
82*4882a593Smuzhiyun struct tegra_dc *dc,
83*4882a593Smuzhiyun unsigned int wgrp,
84*4882a593Smuzhiyun unsigned int index);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun int tegra_display_hub_atomic_check(struct drm_device *drm,
87*4882a593Smuzhiyun struct drm_atomic_state *state);
88*4882a593Smuzhiyun void tegra_display_hub_atomic_commit(struct drm_device *drm,
89*4882a593Smuzhiyun struct drm_atomic_state *state);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #define DC_CMD_IHUB_COMMON_MISC_CTL 0x068
92*4882a593Smuzhiyun #define LATENCY_EVENT (1 << 3)
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER 0x451
95*4882a593Smuzhiyun #define CURS_SLOTS(x) (((x) & 0xff) << 8)
96*4882a593Smuzhiyun #define WGRP_SLOTS(x) (((x) & 0xff) << 0)
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #endif /* TEGRA_HUB_H */
99