1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015, NVIDIA Corporation. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _FALCON_H_ 7*4882a593Smuzhiyun #define _FALCON_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/types.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define FALCON_UCLASS_METHOD_OFFSET 0x00000040 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define FALCON_UCLASS_METHOD_DATA 0x00000044 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define FALCON_IRQMSET 0x00001010 16*4882a593Smuzhiyun #define FALCON_IRQMSET_WDTMR (1 << 1) 17*4882a593Smuzhiyun #define FALCON_IRQMSET_HALT (1 << 4) 18*4882a593Smuzhiyun #define FALCON_IRQMSET_EXTERR (1 << 5) 19*4882a593Smuzhiyun #define FALCON_IRQMSET_SWGEN0 (1 << 6) 20*4882a593Smuzhiyun #define FALCON_IRQMSET_SWGEN1 (1 << 7) 21*4882a593Smuzhiyun #define FALCON_IRQMSET_EXT(v) (((v) & 0xff) << 8) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define FALCON_IRQDEST 0x0000101c 24*4882a593Smuzhiyun #define FALCON_IRQDEST_HALT (1 << 4) 25*4882a593Smuzhiyun #define FALCON_IRQDEST_EXTERR (1 << 5) 26*4882a593Smuzhiyun #define FALCON_IRQDEST_SWGEN0 (1 << 6) 27*4882a593Smuzhiyun #define FALCON_IRQDEST_SWGEN1 (1 << 7) 28*4882a593Smuzhiyun #define FALCON_IRQDEST_EXT(v) (((v) & 0xff) << 8) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define FALCON_ITFEN 0x00001048 31*4882a593Smuzhiyun #define FALCON_ITFEN_CTXEN (1 << 0) 32*4882a593Smuzhiyun #define FALCON_ITFEN_MTHDEN (1 << 1) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define FALCON_IDLESTATE 0x0000104c 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define FALCON_CPUCTL 0x00001100 37*4882a593Smuzhiyun #define FALCON_CPUCTL_STARTCPU (1 << 1) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define FALCON_BOOTVEC 0x00001104 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define FALCON_DMACTL 0x0000110c 42*4882a593Smuzhiyun #define FALCON_DMACTL_DMEM_SCRUBBING (1 << 1) 43*4882a593Smuzhiyun #define FALCON_DMACTL_IMEM_SCRUBBING (1 << 2) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define FALCON_DMATRFBASE 0x00001110 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define FALCON_DMATRFMOFFS 0x00001114 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define FALCON_DMATRFCMD 0x00001118 50*4882a593Smuzhiyun #define FALCON_DMATRFCMD_IDLE (1 << 1) 51*4882a593Smuzhiyun #define FALCON_DMATRFCMD_IMEM (1 << 4) 52*4882a593Smuzhiyun #define FALCON_DMATRFCMD_SIZE_256B (6 << 8) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define FALCON_DMATRFFBOFFS 0x0000111c 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun struct falcon_fw_bin_header_v1 { 57*4882a593Smuzhiyun u32 magic; /* 0x10de */ 58*4882a593Smuzhiyun u32 version; /* version of bin format (1) */ 59*4882a593Smuzhiyun u32 size; /* entire image size including this header */ 60*4882a593Smuzhiyun u32 os_header_offset; 61*4882a593Smuzhiyun u32 os_data_offset; 62*4882a593Smuzhiyun u32 os_size; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct falcon_fw_os_app_v1 { 66*4882a593Smuzhiyun u32 offset; 67*4882a593Smuzhiyun u32 size; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct falcon_fw_os_header_v1 { 71*4882a593Smuzhiyun u32 code_offset; 72*4882a593Smuzhiyun u32 code_size; 73*4882a593Smuzhiyun u32 data_offset; 74*4882a593Smuzhiyun u32 data_size; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun struct falcon_firmware_section { 78*4882a593Smuzhiyun unsigned long offset; 79*4882a593Smuzhiyun size_t size; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct falcon_firmware { 83*4882a593Smuzhiyun /* Firmware after it is read but not loaded */ 84*4882a593Smuzhiyun const struct firmware *firmware; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Raw firmware data */ 87*4882a593Smuzhiyun dma_addr_t iova; 88*4882a593Smuzhiyun dma_addr_t phys; 89*4882a593Smuzhiyun void *virt; 90*4882a593Smuzhiyun size_t size; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Parsed firmware information */ 93*4882a593Smuzhiyun struct falcon_firmware_section bin_data; 94*4882a593Smuzhiyun struct falcon_firmware_section data; 95*4882a593Smuzhiyun struct falcon_firmware_section code; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct falcon { 99*4882a593Smuzhiyun /* Set by falcon client */ 100*4882a593Smuzhiyun struct device *dev; 101*4882a593Smuzhiyun void __iomem *regs; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun struct falcon_firmware firmware; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun int falcon_init(struct falcon *falcon); 107*4882a593Smuzhiyun void falcon_exit(struct falcon *falcon); 108*4882a593Smuzhiyun int falcon_read_firmware(struct falcon *falcon, const char *firmware_name); 109*4882a593Smuzhiyun int falcon_load_firmware(struct falcon *falcon); 110*4882a593Smuzhiyun int falcon_boot(struct falcon *falcon); 111*4882a593Smuzhiyun void falcon_execute_method(struct falcon *falcon, u32 method, u32 data); 112*4882a593Smuzhiyun int falcon_wait_idle(struct falcon *falcon); 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #endif /* _FALCON_H_ */ 115