1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2013-2019 NVIDIA Corporation. 4*4882a593Smuzhiyun * Copyright (C) 2015 Rob Clark 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef DRM_TEGRA_DP_H 8*4882a593Smuzhiyun #define DRM_TEGRA_DP_H 1 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/types.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct drm_display_info; 13*4882a593Smuzhiyun struct drm_display_mode; 14*4882a593Smuzhiyun struct drm_dp_aux; 15*4882a593Smuzhiyun struct drm_dp_link; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /** 18*4882a593Smuzhiyun * struct drm_dp_link_caps - DP link capabilities 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun struct drm_dp_link_caps { 21*4882a593Smuzhiyun /** 22*4882a593Smuzhiyun * @enhanced_framing: 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * enhanced framing capability (mandatory as of DP 1.2) 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun bool enhanced_framing; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /** 29*4882a593Smuzhiyun * tps3_supported: 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * training pattern sequence 3 supported for equalization 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun bool tps3_supported; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /** 36*4882a593Smuzhiyun * @fast_training: 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * AUX CH handshake not required for link training 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun bool fast_training; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /** 43*4882a593Smuzhiyun * @channel_coding: 44*4882a593Smuzhiyun * 45*4882a593Smuzhiyun * ANSI 8B/10B channel coding capability 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun bool channel_coding; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /** 50*4882a593Smuzhiyun * @alternate_scrambler_reset: 51*4882a593Smuzhiyun * 52*4882a593Smuzhiyun * eDP alternate scrambler reset capability 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun bool alternate_scrambler_reset; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest, 58*4882a593Smuzhiyun const struct drm_dp_link_caps *src); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /** 61*4882a593Smuzhiyun * struct drm_dp_link_ops - DP link operations 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun struct drm_dp_link_ops { 64*4882a593Smuzhiyun /** 65*4882a593Smuzhiyun * @apply_training: 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun int (*apply_training)(struct drm_dp_link *link); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /** 70*4882a593Smuzhiyun * @configure: 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun int (*configure)(struct drm_dp_link *link); 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define DP_TRAIN_VOLTAGE_SWING_LEVEL(x) ((x) << 0) 76*4882a593Smuzhiyun #define DP_TRAIN_PRE_EMPHASIS_LEVEL(x) ((x) << 3) 77*4882a593Smuzhiyun #define DP_LANE_POST_CURSOR(i, x) (((x) & 0x3) << (((i) & 1) << 2)) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /** 80*4882a593Smuzhiyun * struct drm_dp_link_train_set - link training settings 81*4882a593Smuzhiyun * @voltage_swing: per-lane voltage swing 82*4882a593Smuzhiyun * @pre_emphasis: per-lane pre-emphasis 83*4882a593Smuzhiyun * @post_cursor: per-lane post-cursor 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun struct drm_dp_link_train_set { 86*4882a593Smuzhiyun unsigned int voltage_swing[4]; 87*4882a593Smuzhiyun unsigned int pre_emphasis[4]; 88*4882a593Smuzhiyun unsigned int post_cursor[4]; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /** 92*4882a593Smuzhiyun * struct drm_dp_link_train - link training state information 93*4882a593Smuzhiyun * @request: currently requested settings 94*4882a593Smuzhiyun * @adjust: adjustments requested by sink 95*4882a593Smuzhiyun * @pattern: currently requested training pattern 96*4882a593Smuzhiyun * @clock_recovered: flag to track if clock recovery has completed 97*4882a593Smuzhiyun * @channel_equalized: flag to track if channel equalization has completed 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun struct drm_dp_link_train { 100*4882a593Smuzhiyun struct drm_dp_link_train_set request; 101*4882a593Smuzhiyun struct drm_dp_link_train_set adjust; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun unsigned int pattern; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun bool clock_recovered; 106*4882a593Smuzhiyun bool channel_equalized; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /** 110*4882a593Smuzhiyun * struct drm_dp_link - DP link capabilities and configuration 111*4882a593Smuzhiyun * @revision: DP specification revision supported on the link 112*4882a593Smuzhiyun * @max_rate: maximum clock rate supported on the link 113*4882a593Smuzhiyun * @max_lanes: maximum number of lanes supported on the link 114*4882a593Smuzhiyun * @caps: capabilities supported on the link (see &drm_dp_link_caps) 115*4882a593Smuzhiyun * @aux_rd_interval: AUX read interval to use for training (in microseconds) 116*4882a593Smuzhiyun * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...) 117*4882a593Smuzhiyun * @rate: currently configured link rate 118*4882a593Smuzhiyun * @lanes: currently configured number of lanes 119*4882a593Smuzhiyun * @rates: additional supported link rates in kHz (eDP 1.4) 120*4882a593Smuzhiyun * @num_rates: number of additional supported link rates (eDP 1.4) 121*4882a593Smuzhiyun */ 122*4882a593Smuzhiyun struct drm_dp_link { 123*4882a593Smuzhiyun unsigned char revision; 124*4882a593Smuzhiyun unsigned int max_rate; 125*4882a593Smuzhiyun unsigned int max_lanes; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun struct drm_dp_link_caps caps; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /** 130*4882a593Smuzhiyun * @cr: clock recovery read interval 131*4882a593Smuzhiyun * @ce: channel equalization read interval 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun struct { 134*4882a593Smuzhiyun unsigned int cr; 135*4882a593Smuzhiyun unsigned int ce; 136*4882a593Smuzhiyun } aux_rd_interval; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun unsigned char edp; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun unsigned int rate; 141*4882a593Smuzhiyun unsigned int lanes; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun unsigned long rates[DP_MAX_SUPPORTED_RATES]; 144*4882a593Smuzhiyun unsigned int num_rates; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /** 147*4882a593Smuzhiyun * @ops: DP link operations 148*4882a593Smuzhiyun */ 149*4882a593Smuzhiyun const struct drm_dp_link_ops *ops; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /** 152*4882a593Smuzhiyun * @aux: DP AUX channel 153*4882a593Smuzhiyun */ 154*4882a593Smuzhiyun struct drm_dp_aux *aux; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /** 157*4882a593Smuzhiyun * @train: DP link training state 158*4882a593Smuzhiyun */ 159*4882a593Smuzhiyun struct drm_dp_link_train train; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate); 163*4882a593Smuzhiyun int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate); 164*4882a593Smuzhiyun void drm_dp_link_update_rates(struct drm_dp_link *link); 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); 167*4882a593Smuzhiyun int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); 168*4882a593Smuzhiyun int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); 169*4882a593Smuzhiyun int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); 170*4882a593Smuzhiyun int drm_dp_link_choose(struct drm_dp_link *link, 171*4882a593Smuzhiyun const struct drm_display_mode *mode, 172*4882a593Smuzhiyun const struct drm_display_info *info); 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun void drm_dp_link_train_init(struct drm_dp_link_train *train); 175*4882a593Smuzhiyun int drm_dp_link_train(struct drm_dp_link *link); 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun #endif 178