xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2017 Jernej Skrabec <jernej.skrabec@siol.net>
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * This file is licensed under the terms of the GNU General Public
5*4882a593Smuzhiyun  * License version 2.  This program is licensed "as is" without any
6*4882a593Smuzhiyun  * warranty of any kind, whether express or implied.
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #ifndef _SUN8I_VI_SCALER_H_
10*4882a593Smuzhiyun #define _SUN8I_VI_SCALER_H_
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <drm/drm_fourcc.h>
13*4882a593Smuzhiyun #include "sun8i_mixer.h"
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define DE2_VI_SCALER_UNIT_BASE 0x20000
16*4882a593Smuzhiyun #define DE2_VI_SCALER_UNIT_SIZE 0x20000
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define DE3_VI_SCALER_UNIT_BASE 0x20000
19*4882a593Smuzhiyun #define DE3_VI_SCALER_UNIT_SIZE 0x08000
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* this two macros assumes 16 fractional bits which is standard in DRM */
22*4882a593Smuzhiyun #define SUN8I_VI_SCALER_SCALE_MIN		1
23*4882a593Smuzhiyun #define SUN8I_VI_SCALER_SCALE_MAX		((1UL << 20) - 1)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define SUN8I_VI_SCALER_SCALE_FRAC		20
26*4882a593Smuzhiyun #define SUN8I_VI_SCALER_PHASE_FRAC		20
27*4882a593Smuzhiyun #define SUN8I_VI_SCALER_COEFF_COUNT		32
28*4882a593Smuzhiyun #define SUN8I_VI_SCALER_SIZE(w, h)		(((h) - 1) << 16 | ((w) - 1))
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_CTRL(base)		((base) + 0x0)
31*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_SCALE_MODE(base)		((base) + 0x10)
32*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_DIR_THR(base)		((base) + 0x20)
33*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_EDGE_THR(base)		((base) + 0x24)
34*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_EDSCL_CTRL(base)		((base) + 0x28)
35*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_ANGLE_THR(base)		((base) + 0x2c)
36*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_OUTSIZE(base)		((base) + 0x40)
37*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_YINSIZE(base)		((base) + 0x80)
38*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_YHSTEP(base)		((base) + 0x88)
39*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_YVSTEP(base)		((base) + 0x8c)
40*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_YHPHASE(base)		((base) + 0x90)
41*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_YVPHASE(base)		((base) + 0x98)
42*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_CINSIZE(base)		((base) + 0xc0)
43*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_CHSTEP(base)		((base) + 0xc8)
44*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_CVSTEP(base)		((base) + 0xcc)
45*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_CHPHASE(base)		((base) + 0xd0)
46*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_CVPHASE(base)		((base) + 0xd8)
47*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_YHCOEFF0(base, i)	((base) + 0x200 + 0x4 * (i))
48*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_YHCOEFF1(base, i)	((base) + 0x300 + 0x4 * (i))
49*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_YVCOEFF(base, i)	((base) + 0x400 + 0x4 * (i))
50*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_CHCOEFF0(base, i)	((base) + 0x600 + 0x4 * (i))
51*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_CHCOEFF1(base, i)	((base) + 0x700 + 0x4 * (i))
52*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_CVCOEFF(base, i)	((base) + 0x800 + 0x4 * (i))
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_CTRL_EN		BIT(0)
55*4882a593Smuzhiyun #define SUN8I_SCALER_VSU_CTRL_COEFF_RDY		BIT(4)
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_SUB_ZERO_DIR_THR(x)	(((x) << 24) & 0xFF)
58*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_ZERO_DIR_THR(x)		(((x) << 16) & 0xFF)
59*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_HORZ_DIR_THR(x)		(((x) << 8) & 0xFF)
60*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_VERT_DIR_THR(x)		((x) & 0xFF)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_SCALE_MODE_UI		0
63*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_SCALE_MODE_NORMAL	1
64*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_SCALE_MODE_ED_SCALE	2
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_EDGE_SHIFT(x)		(((x) << 16) & 0xF)
67*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_EDGE_OFFSET(x)		((x) & 0xFF)
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_ANGLE_SHIFT(x)		(((x) << 16) & 0xF)
70*4882a593Smuzhiyun #define SUN50I_SCALER_VSU_ANGLE_OFFSET(x)		((x) & 0xFF)
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable);
73*4882a593Smuzhiyun void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
74*4882a593Smuzhiyun 			   u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
75*4882a593Smuzhiyun 			   u32 hscale, u32 vscale, u32 hphase, u32 vphase,
76*4882a593Smuzhiyun 			   const struct drm_format_info *format);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun #endif
79