1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _SUN8I_TCON_TOP_H_ 5*4882a593Smuzhiyun #define _SUN8I_TCON_TOP_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <linux/clk.h> 8*4882a593Smuzhiyun #include <linux/clk-provider.h> 9*4882a593Smuzhiyun #include <linux/reset.h> 10*4882a593Smuzhiyun #include <linux/spinlock.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define TCON_TOP_TCON_TV_SETUP_REG 0x00 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define TCON_TOP_PORT_SEL_REG 0x1C 15*4882a593Smuzhiyun #define TCON_TOP_PORT_DE0_MSK GENMASK(1, 0) 16*4882a593Smuzhiyun #define TCON_TOP_PORT_DE1_MSK GENMASK(5, 4) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define TCON_TOP_GATE_SRC_REG 0x20 19*4882a593Smuzhiyun #define TCON_TOP_HDMI_SRC_MSK GENMASK(29, 28) 20*4882a593Smuzhiyun #define TCON_TOP_TCON_TV1_GATE 24 21*4882a593Smuzhiyun #define TCON_TOP_TCON_TV0_GATE 20 22*4882a593Smuzhiyun #define TCON_TOP_TCON_DSI_GATE 16 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CLK_NUM 3 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct sun8i_tcon_top { 27*4882a593Smuzhiyun struct clk *bus; 28*4882a593Smuzhiyun struct clk_hw_onecell_data *clk_data; 29*4882a593Smuzhiyun void __iomem *regs; 30*4882a593Smuzhiyun struct reset_control *rst; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * spinlock is used to synchronize access to same 34*4882a593Smuzhiyun * register where multiple clock gates can be set. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun spinlock_t reg_lock; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun extern const struct of_device_id sun8i_tcon_top_of_table[]; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun int sun8i_tcon_top_set_hdmi_src(struct device *dev, int tcon); 42*4882a593Smuzhiyun int sun8i_tcon_top_de_config(struct device *dev, int mixer, int tcon); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif /* _SUN8I_TCON_TOP_H_ */ 45