xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/sun4i_tv.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2015 Free Electrons
4*4882a593Smuzhiyun  * Copyright (C) 2015 NextThing Co
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Maxime Ripard <maxime.ripard@free-electrons.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <linux/component.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of_address.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun #include <linux/reset.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
18*4882a593Smuzhiyun #include <drm/drm_of.h>
19*4882a593Smuzhiyun #include <drm/drm_panel.h>
20*4882a593Smuzhiyun #include <drm/drm_print.h>
21*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
22*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include "sun4i_crtc.h"
25*4882a593Smuzhiyun #include "sun4i_drv.h"
26*4882a593Smuzhiyun #include "sunxi_engine.h"
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define SUN4I_TVE_EN_REG		0x000
29*4882a593Smuzhiyun #define SUN4I_TVE_EN_DAC_MAP_MASK		GENMASK(19, 4)
30*4882a593Smuzhiyun #define SUN4I_TVE_EN_DAC_MAP(dac, out)		(((out) & 0xf) << (dac + 1) * 4)
31*4882a593Smuzhiyun #define SUN4I_TVE_EN_ENABLE			BIT(0)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define SUN4I_TVE_CFG0_REG		0x004
34*4882a593Smuzhiyun #define SUN4I_TVE_CFG0_DAC_CONTROL_54M		BIT(26)
35*4882a593Smuzhiyun #define SUN4I_TVE_CFG0_CORE_DATAPATH_54M	BIT(25)
36*4882a593Smuzhiyun #define SUN4I_TVE_CFG0_CORE_CONTROL_54M		BIT(24)
37*4882a593Smuzhiyun #define SUN4I_TVE_CFG0_YC_EN			BIT(17)
38*4882a593Smuzhiyun #define SUN4I_TVE_CFG0_COMP_EN			BIT(16)
39*4882a593Smuzhiyun #define SUN4I_TVE_CFG0_RES(x)			((x) & 0xf)
40*4882a593Smuzhiyun #define SUN4I_TVE_CFG0_RES_480i			SUN4I_TVE_CFG0_RES(0)
41*4882a593Smuzhiyun #define SUN4I_TVE_CFG0_RES_576i			SUN4I_TVE_CFG0_RES(1)
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define SUN4I_TVE_DAC0_REG		0x008
44*4882a593Smuzhiyun #define SUN4I_TVE_DAC0_CLOCK_INVERT		BIT(24)
45*4882a593Smuzhiyun #define SUN4I_TVE_DAC0_LUMA(x)			(((x) & 3) << 20)
46*4882a593Smuzhiyun #define SUN4I_TVE_DAC0_LUMA_0_4			SUN4I_TVE_DAC0_LUMA(3)
47*4882a593Smuzhiyun #define SUN4I_TVE_DAC0_CHROMA(x)		(((x) & 3) << 18)
48*4882a593Smuzhiyun #define SUN4I_TVE_DAC0_CHROMA_0_75		SUN4I_TVE_DAC0_CHROMA(3)
49*4882a593Smuzhiyun #define SUN4I_TVE_DAC0_INTERNAL_DAC(x)		(((x) & 3) << 16)
50*4882a593Smuzhiyun #define SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS	SUN4I_TVE_DAC0_INTERNAL_DAC(3)
51*4882a593Smuzhiyun #define SUN4I_TVE_DAC0_DAC_EN(dac)		BIT(dac)
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define SUN4I_TVE_NOTCH_REG		0x00c
54*4882a593Smuzhiyun #define SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(dac, x)	((4 - (x)) << (dac * 3))
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define SUN4I_TVE_CHROMA_FREQ_REG	0x010
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define SUN4I_TVE_PORCH_REG		0x014
59*4882a593Smuzhiyun #define SUN4I_TVE_PORCH_BACK(x)			((x) << 16)
60*4882a593Smuzhiyun #define SUN4I_TVE_PORCH_FRONT(x)		(x)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define SUN4I_TVE_LINE_REG		0x01c
63*4882a593Smuzhiyun #define SUN4I_TVE_LINE_FIRST(x)			((x) << 16)
64*4882a593Smuzhiyun #define SUN4I_TVE_LINE_NUMBER(x)		(x)
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define SUN4I_TVE_LEVEL_REG		0x020
67*4882a593Smuzhiyun #define SUN4I_TVE_LEVEL_BLANK(x)		((x) << 16)
68*4882a593Smuzhiyun #define SUN4I_TVE_LEVEL_BLACK(x)		(x)
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define SUN4I_TVE_DAC1_REG		0x024
71*4882a593Smuzhiyun #define SUN4I_TVE_DAC1_AMPLITUDE(dac, x)	((x) << (dac * 8))
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define SUN4I_TVE_DETECT_STA_REG	0x038
74*4882a593Smuzhiyun #define SUN4I_TVE_DETECT_STA_DAC(dac)		BIT((dac * 8))
75*4882a593Smuzhiyun #define SUN4I_TVE_DETECT_STA_UNCONNECTED		0
76*4882a593Smuzhiyun #define SUN4I_TVE_DETECT_STA_CONNECTED			1
77*4882a593Smuzhiyun #define SUN4I_TVE_DETECT_STA_GROUND			2
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun #define SUN4I_TVE_CB_CR_LVL_REG		0x10c
80*4882a593Smuzhiyun #define SUN4I_TVE_CB_CR_LVL_CR_BURST(x)		((x) << 8)
81*4882a593Smuzhiyun #define SUN4I_TVE_CB_CR_LVL_CB_BURST(x)		(x)
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define SUN4I_TVE_TINT_BURST_PHASE_REG	0x110
84*4882a593Smuzhiyun #define SUN4I_TVE_TINT_BURST_PHASE_CHROMA(x)	(x)
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #define SUN4I_TVE_BURST_WIDTH_REG	0x114
87*4882a593Smuzhiyun #define SUN4I_TVE_BURST_WIDTH_BREEZEWAY(x)	((x) << 16)
88*4882a593Smuzhiyun #define SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(x)	((x) << 8)
89*4882a593Smuzhiyun #define SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(x)	(x)
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun #define SUN4I_TVE_CB_CR_GAIN_REG	0x118
92*4882a593Smuzhiyun #define SUN4I_TVE_CB_CR_GAIN_CR(x)		((x) << 8)
93*4882a593Smuzhiyun #define SUN4I_TVE_CB_CR_GAIN_CB(x)		(x)
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define SUN4I_TVE_SYNC_VBI_REG		0x11c
96*4882a593Smuzhiyun #define SUN4I_TVE_SYNC_VBI_SYNC(x)		((x) << 16)
97*4882a593Smuzhiyun #define SUN4I_TVE_SYNC_VBI_VBLANK(x)		(x)
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun #define SUN4I_TVE_ACTIVE_LINE_REG	0x124
100*4882a593Smuzhiyun #define SUN4I_TVE_ACTIVE_LINE(x)		(x)
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun #define SUN4I_TVE_CHROMA_REG		0x128
103*4882a593Smuzhiyun #define SUN4I_TVE_CHROMA_COMP_GAIN(x)		((x) & 3)
104*4882a593Smuzhiyun #define SUN4I_TVE_CHROMA_COMP_GAIN_50		SUN4I_TVE_CHROMA_COMP_GAIN(2)
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun #define SUN4I_TVE_12C_REG		0x12c
107*4882a593Smuzhiyun #define SUN4I_TVE_12C_NOTCH_WIDTH_WIDE		BIT(8)
108*4882a593Smuzhiyun #define SUN4I_TVE_12C_COMP_YUV_EN		BIT(0)
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define SUN4I_TVE_RESYNC_REG		0x130
111*4882a593Smuzhiyun #define SUN4I_TVE_RESYNC_FIELD			BIT(31)
112*4882a593Smuzhiyun #define SUN4I_TVE_RESYNC_LINE(x)		((x) << 16)
113*4882a593Smuzhiyun #define SUN4I_TVE_RESYNC_PIXEL(x)		(x)
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun #define SUN4I_TVE_SLAVE_REG		0x134
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #define SUN4I_TVE_WSS_DATA2_REG		0x244
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun struct color_gains {
120*4882a593Smuzhiyun 	u16	cb;
121*4882a593Smuzhiyun 	u16	cr;
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun struct burst_levels {
125*4882a593Smuzhiyun 	u16	cb;
126*4882a593Smuzhiyun 	u16	cr;
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun struct video_levels {
130*4882a593Smuzhiyun 	u16	black;
131*4882a593Smuzhiyun 	u16	blank;
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun struct resync_parameters {
135*4882a593Smuzhiyun 	bool	field;
136*4882a593Smuzhiyun 	u16	line;
137*4882a593Smuzhiyun 	u16	pixel;
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun struct tv_mode {
141*4882a593Smuzhiyun 	char		*name;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	u32		mode;
144*4882a593Smuzhiyun 	u32		chroma_freq;
145*4882a593Smuzhiyun 	u16		back_porch;
146*4882a593Smuzhiyun 	u16		front_porch;
147*4882a593Smuzhiyun 	u16		line_number;
148*4882a593Smuzhiyun 	u16		vblank_level;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	u32		hdisplay;
151*4882a593Smuzhiyun 	u16		hfront_porch;
152*4882a593Smuzhiyun 	u16		hsync_len;
153*4882a593Smuzhiyun 	u16		hback_porch;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	u32		vdisplay;
156*4882a593Smuzhiyun 	u16		vfront_porch;
157*4882a593Smuzhiyun 	u16		vsync_len;
158*4882a593Smuzhiyun 	u16		vback_porch;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	bool		yc_en;
161*4882a593Smuzhiyun 	bool		dac3_en;
162*4882a593Smuzhiyun 	bool		dac_bit25_en;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	const struct color_gains	*color_gains;
165*4882a593Smuzhiyun 	const struct burst_levels	*burst_levels;
166*4882a593Smuzhiyun 	const struct video_levels	*video_levels;
167*4882a593Smuzhiyun 	const struct resync_parameters	*resync_params;
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun struct sun4i_tv {
171*4882a593Smuzhiyun 	struct drm_connector	connector;
172*4882a593Smuzhiyun 	struct drm_encoder	encoder;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	struct clk		*clk;
175*4882a593Smuzhiyun 	struct regmap		*regs;
176*4882a593Smuzhiyun 	struct reset_control	*reset;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	struct sun4i_drv	*drv;
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun static const struct video_levels ntsc_video_levels = {
182*4882a593Smuzhiyun 	.black = 282,	.blank = 240,
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun static const struct video_levels pal_video_levels = {
186*4882a593Smuzhiyun 	.black = 252,	.blank = 252,
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun static const struct burst_levels ntsc_burst_levels = {
190*4882a593Smuzhiyun 	.cb = 79,	.cr = 0,
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun static const struct burst_levels pal_burst_levels = {
194*4882a593Smuzhiyun 	.cb = 40,	.cr = 40,
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun static const struct color_gains ntsc_color_gains = {
198*4882a593Smuzhiyun 	.cb = 160,	.cr = 160,
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun static const struct color_gains pal_color_gains = {
202*4882a593Smuzhiyun 	.cb = 224,	.cr = 224,
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun static const struct resync_parameters ntsc_resync_parameters = {
206*4882a593Smuzhiyun 	.field = false,	.line = 14,	.pixel = 12,
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun static const struct resync_parameters pal_resync_parameters = {
210*4882a593Smuzhiyun 	.field = true,	.line = 13,	.pixel = 12,
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun static const struct tv_mode tv_modes[] = {
214*4882a593Smuzhiyun 	{
215*4882a593Smuzhiyun 		.name		= "NTSC",
216*4882a593Smuzhiyun 		.mode		= SUN4I_TVE_CFG0_RES_480i,
217*4882a593Smuzhiyun 		.chroma_freq	= 0x21f07c1f,
218*4882a593Smuzhiyun 		.yc_en		= true,
219*4882a593Smuzhiyun 		.dac3_en	= true,
220*4882a593Smuzhiyun 		.dac_bit25_en	= true,
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 		.back_porch	= 118,
223*4882a593Smuzhiyun 		.front_porch	= 32,
224*4882a593Smuzhiyun 		.line_number	= 525,
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 		.hdisplay	= 720,
227*4882a593Smuzhiyun 		.hfront_porch	= 18,
228*4882a593Smuzhiyun 		.hsync_len	= 2,
229*4882a593Smuzhiyun 		.hback_porch	= 118,
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 		.vdisplay	= 480,
232*4882a593Smuzhiyun 		.vfront_porch	= 26,
233*4882a593Smuzhiyun 		.vsync_len	= 2,
234*4882a593Smuzhiyun 		.vback_porch	= 17,
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 		.vblank_level	= 240,
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 		.color_gains	= &ntsc_color_gains,
239*4882a593Smuzhiyun 		.burst_levels	= &ntsc_burst_levels,
240*4882a593Smuzhiyun 		.video_levels	= &ntsc_video_levels,
241*4882a593Smuzhiyun 		.resync_params	= &ntsc_resync_parameters,
242*4882a593Smuzhiyun 	},
243*4882a593Smuzhiyun 	{
244*4882a593Smuzhiyun 		.name		= "PAL",
245*4882a593Smuzhiyun 		.mode		= SUN4I_TVE_CFG0_RES_576i,
246*4882a593Smuzhiyun 		.chroma_freq	= 0x2a098acb,
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 		.back_porch	= 138,
249*4882a593Smuzhiyun 		.front_porch	= 24,
250*4882a593Smuzhiyun 		.line_number	= 625,
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 		.hdisplay	= 720,
253*4882a593Smuzhiyun 		.hfront_porch	= 3,
254*4882a593Smuzhiyun 		.hsync_len	= 2,
255*4882a593Smuzhiyun 		.hback_porch	= 139,
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 		.vdisplay	= 576,
258*4882a593Smuzhiyun 		.vfront_porch	= 28,
259*4882a593Smuzhiyun 		.vsync_len	= 2,
260*4882a593Smuzhiyun 		.vback_porch	= 19,
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 		.vblank_level	= 252,
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 		.color_gains	= &pal_color_gains,
265*4882a593Smuzhiyun 		.burst_levels	= &pal_burst_levels,
266*4882a593Smuzhiyun 		.video_levels	= &pal_video_levels,
267*4882a593Smuzhiyun 		.resync_params	= &pal_resync_parameters,
268*4882a593Smuzhiyun 	},
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun static inline struct sun4i_tv *
drm_encoder_to_sun4i_tv(struct drm_encoder * encoder)272*4882a593Smuzhiyun drm_encoder_to_sun4i_tv(struct drm_encoder *encoder)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun 	return container_of(encoder, struct sun4i_tv,
275*4882a593Smuzhiyun 			    encoder);
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun static inline struct sun4i_tv *
drm_connector_to_sun4i_tv(struct drm_connector * connector)279*4882a593Smuzhiyun drm_connector_to_sun4i_tv(struct drm_connector *connector)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun 	return container_of(connector, struct sun4i_tv,
282*4882a593Smuzhiyun 			    connector);
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun /*
286*4882a593Smuzhiyun  * FIXME: If only the drm_display_mode private field was usable, this
287*4882a593Smuzhiyun  * could go away...
288*4882a593Smuzhiyun  *
289*4882a593Smuzhiyun  * So far, it doesn't seem to be preserved when the mode is passed by
290*4882a593Smuzhiyun  * to mode_set for some reason.
291*4882a593Smuzhiyun  */
sun4i_tv_find_tv_by_mode(const struct drm_display_mode * mode)292*4882a593Smuzhiyun static const struct tv_mode *sun4i_tv_find_tv_by_mode(const struct drm_display_mode *mode)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun 	int i;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	/* First try to identify the mode by name */
297*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
298*4882a593Smuzhiyun 		const struct tv_mode *tv_mode = &tv_modes[i];
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 		DRM_DEBUG_DRIVER("Comparing mode %s vs %s",
301*4882a593Smuzhiyun 				 mode->name, tv_mode->name);
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 		if (!strcmp(mode->name, tv_mode->name))
304*4882a593Smuzhiyun 			return tv_mode;
305*4882a593Smuzhiyun 	}
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	/* Then by number of lines */
308*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
309*4882a593Smuzhiyun 		const struct tv_mode *tv_mode = &tv_modes[i];
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 		DRM_DEBUG_DRIVER("Comparing mode %s vs %s (X: %d vs %d)",
312*4882a593Smuzhiyun 				 mode->name, tv_mode->name,
313*4882a593Smuzhiyun 				 mode->vdisplay, tv_mode->vdisplay);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 		if (mode->vdisplay == tv_mode->vdisplay)
316*4882a593Smuzhiyun 			return tv_mode;
317*4882a593Smuzhiyun 	}
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	return NULL;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun 
sun4i_tv_mode_to_drm_mode(const struct tv_mode * tv_mode,struct drm_display_mode * mode)322*4882a593Smuzhiyun static void sun4i_tv_mode_to_drm_mode(const struct tv_mode *tv_mode,
323*4882a593Smuzhiyun 				      struct drm_display_mode *mode)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Creating mode %s\n", mode->name);
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	mode->type = DRM_MODE_TYPE_DRIVER;
328*4882a593Smuzhiyun 	mode->clock = 13500;
329*4882a593Smuzhiyun 	mode->flags = DRM_MODE_FLAG_INTERLACE;
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 	mode->hdisplay = tv_mode->hdisplay;
332*4882a593Smuzhiyun 	mode->hsync_start = mode->hdisplay + tv_mode->hfront_porch;
333*4882a593Smuzhiyun 	mode->hsync_end = mode->hsync_start + tv_mode->hsync_len;
334*4882a593Smuzhiyun 	mode->htotal = mode->hsync_end  + tv_mode->hback_porch;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	mode->vdisplay = tv_mode->vdisplay;
337*4882a593Smuzhiyun 	mode->vsync_start = mode->vdisplay + tv_mode->vfront_porch;
338*4882a593Smuzhiyun 	mode->vsync_end = mode->vsync_start + tv_mode->vsync_len;
339*4882a593Smuzhiyun 	mode->vtotal = mode->vsync_end  + tv_mode->vback_porch;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun 
sun4i_tv_disable(struct drm_encoder * encoder)342*4882a593Smuzhiyun static void sun4i_tv_disable(struct drm_encoder *encoder)
343*4882a593Smuzhiyun {
344*4882a593Smuzhiyun 	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
345*4882a593Smuzhiyun 	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Disabling the TV Output\n");
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
350*4882a593Smuzhiyun 			   SUN4I_TVE_EN_ENABLE,
351*4882a593Smuzhiyun 			   0);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	sunxi_engine_disable_color_correction(crtc->engine);
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun 
sun4i_tv_enable(struct drm_encoder * encoder)356*4882a593Smuzhiyun static void sun4i_tv_enable(struct drm_encoder *encoder)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
359*4882a593Smuzhiyun 	struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Enabling the TV Output\n");
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	sunxi_engine_apply_color_correction(crtc->engine);
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
366*4882a593Smuzhiyun 			   SUN4I_TVE_EN_ENABLE,
367*4882a593Smuzhiyun 			   SUN4I_TVE_EN_ENABLE);
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun 
sun4i_tv_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)370*4882a593Smuzhiyun static void sun4i_tv_mode_set(struct drm_encoder *encoder,
371*4882a593Smuzhiyun 			      struct drm_display_mode *mode,
372*4882a593Smuzhiyun 			      struct drm_display_mode *adjusted_mode)
373*4882a593Smuzhiyun {
374*4882a593Smuzhiyun 	struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
375*4882a593Smuzhiyun 	const struct tv_mode *tv_mode = sun4i_tv_find_tv_by_mode(mode);
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 	/* Enable and map the DAC to the output */
378*4882a593Smuzhiyun 	regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
379*4882a593Smuzhiyun 			   SUN4I_TVE_EN_DAC_MAP_MASK,
380*4882a593Smuzhiyun 			   SUN4I_TVE_EN_DAC_MAP(0, 1) |
381*4882a593Smuzhiyun 			   SUN4I_TVE_EN_DAC_MAP(1, 2) |
382*4882a593Smuzhiyun 			   SUN4I_TVE_EN_DAC_MAP(2, 3) |
383*4882a593Smuzhiyun 			   SUN4I_TVE_EN_DAC_MAP(3, 4));
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	/* Set PAL settings */
386*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_CFG0_REG,
387*4882a593Smuzhiyun 		     tv_mode->mode |
388*4882a593Smuzhiyun 		     (tv_mode->yc_en ? SUN4I_TVE_CFG0_YC_EN : 0) |
389*4882a593Smuzhiyun 		     SUN4I_TVE_CFG0_COMP_EN |
390*4882a593Smuzhiyun 		     SUN4I_TVE_CFG0_DAC_CONTROL_54M |
391*4882a593Smuzhiyun 		     SUN4I_TVE_CFG0_CORE_DATAPATH_54M |
392*4882a593Smuzhiyun 		     SUN4I_TVE_CFG0_CORE_CONTROL_54M);
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	/* Configure the DAC for a composite output */
395*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_DAC0_REG,
396*4882a593Smuzhiyun 		     SUN4I_TVE_DAC0_DAC_EN(0) |
397*4882a593Smuzhiyun 		     (tv_mode->dac3_en ? SUN4I_TVE_DAC0_DAC_EN(3) : 0) |
398*4882a593Smuzhiyun 		     SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS |
399*4882a593Smuzhiyun 		     SUN4I_TVE_DAC0_CHROMA_0_75 |
400*4882a593Smuzhiyun 		     SUN4I_TVE_DAC0_LUMA_0_4 |
401*4882a593Smuzhiyun 		     SUN4I_TVE_DAC0_CLOCK_INVERT |
402*4882a593Smuzhiyun 		     (tv_mode->dac_bit25_en ? BIT(25) : 0) |
403*4882a593Smuzhiyun 		     BIT(30));
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	/* Configure the sample delay between DAC0 and the other DAC */
406*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_NOTCH_REG,
407*4882a593Smuzhiyun 		     SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(1, 0) |
408*4882a593Smuzhiyun 		     SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(2, 0));
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_CHROMA_FREQ_REG,
411*4882a593Smuzhiyun 		     tv_mode->chroma_freq);
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	/* Set the front and back porch */
414*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_PORCH_REG,
415*4882a593Smuzhiyun 		     SUN4I_TVE_PORCH_BACK(tv_mode->back_porch) |
416*4882a593Smuzhiyun 		     SUN4I_TVE_PORCH_FRONT(tv_mode->front_porch));
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun 	/* Set the lines setup */
419*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_LINE_REG,
420*4882a593Smuzhiyun 		     SUN4I_TVE_LINE_FIRST(22) |
421*4882a593Smuzhiyun 		     SUN4I_TVE_LINE_NUMBER(tv_mode->line_number));
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_LEVEL_REG,
424*4882a593Smuzhiyun 		     SUN4I_TVE_LEVEL_BLANK(tv_mode->video_levels->blank) |
425*4882a593Smuzhiyun 		     SUN4I_TVE_LEVEL_BLACK(tv_mode->video_levels->black));
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_DAC1_REG,
428*4882a593Smuzhiyun 		     SUN4I_TVE_DAC1_AMPLITUDE(0, 0x18) |
429*4882a593Smuzhiyun 		     SUN4I_TVE_DAC1_AMPLITUDE(1, 0x18) |
430*4882a593Smuzhiyun 		     SUN4I_TVE_DAC1_AMPLITUDE(2, 0x18) |
431*4882a593Smuzhiyun 		     SUN4I_TVE_DAC1_AMPLITUDE(3, 0x18));
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_CB_CR_LVL_REG,
434*4882a593Smuzhiyun 		     SUN4I_TVE_CB_CR_LVL_CB_BURST(tv_mode->burst_levels->cb) |
435*4882a593Smuzhiyun 		     SUN4I_TVE_CB_CR_LVL_CR_BURST(tv_mode->burst_levels->cr));
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	/* Set burst width for a composite output */
438*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_BURST_WIDTH_REG,
439*4882a593Smuzhiyun 		     SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(126) |
440*4882a593Smuzhiyun 		     SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(68) |
441*4882a593Smuzhiyun 		     SUN4I_TVE_BURST_WIDTH_BREEZEWAY(22));
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_CB_CR_GAIN_REG,
444*4882a593Smuzhiyun 		     SUN4I_TVE_CB_CR_GAIN_CB(tv_mode->color_gains->cb) |
445*4882a593Smuzhiyun 		     SUN4I_TVE_CB_CR_GAIN_CR(tv_mode->color_gains->cr));
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_SYNC_VBI_REG,
448*4882a593Smuzhiyun 		     SUN4I_TVE_SYNC_VBI_SYNC(0x10) |
449*4882a593Smuzhiyun 		     SUN4I_TVE_SYNC_VBI_VBLANK(tv_mode->vblank_level));
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_ACTIVE_LINE_REG,
452*4882a593Smuzhiyun 		     SUN4I_TVE_ACTIVE_LINE(1440));
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	/* Set composite chroma gain to 50 % */
455*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_CHROMA_REG,
456*4882a593Smuzhiyun 		     SUN4I_TVE_CHROMA_COMP_GAIN_50);
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_12C_REG,
459*4882a593Smuzhiyun 		     SUN4I_TVE_12C_COMP_YUV_EN |
460*4882a593Smuzhiyun 		     SUN4I_TVE_12C_NOTCH_WIDTH_WIDE);
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_RESYNC_REG,
463*4882a593Smuzhiyun 		     SUN4I_TVE_RESYNC_PIXEL(tv_mode->resync_params->pixel) |
464*4882a593Smuzhiyun 		     SUN4I_TVE_RESYNC_LINE(tv_mode->resync_params->line) |
465*4882a593Smuzhiyun 		     (tv_mode->resync_params->field ?
466*4882a593Smuzhiyun 		      SUN4I_TVE_RESYNC_FIELD : 0));
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	regmap_write(tv->regs, SUN4I_TVE_SLAVE_REG, 0);
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {
472*4882a593Smuzhiyun 	.disable	= sun4i_tv_disable,
473*4882a593Smuzhiyun 	.enable		= sun4i_tv_enable,
474*4882a593Smuzhiyun 	.mode_set	= sun4i_tv_mode_set,
475*4882a593Smuzhiyun };
476*4882a593Smuzhiyun 
sun4i_tv_comp_get_modes(struct drm_connector * connector)477*4882a593Smuzhiyun static int sun4i_tv_comp_get_modes(struct drm_connector *connector)
478*4882a593Smuzhiyun {
479*4882a593Smuzhiyun 	int i;
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
482*4882a593Smuzhiyun 		struct drm_display_mode *mode;
483*4882a593Smuzhiyun 		const struct tv_mode *tv_mode = &tv_modes[i];
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 		mode = drm_mode_create(connector->dev);
486*4882a593Smuzhiyun 		if (!mode) {
487*4882a593Smuzhiyun 			DRM_ERROR("Failed to create a new display mode\n");
488*4882a593Smuzhiyun 			return 0;
489*4882a593Smuzhiyun 		}
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 		strcpy(mode->name, tv_mode->name);
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun 		sun4i_tv_mode_to_drm_mode(tv_mode, mode);
494*4882a593Smuzhiyun 		drm_mode_probed_add(connector, mode);
495*4882a593Smuzhiyun 	}
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun 	return i;
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun 
sun4i_tv_comp_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)500*4882a593Smuzhiyun static int sun4i_tv_comp_mode_valid(struct drm_connector *connector,
501*4882a593Smuzhiyun 				    struct drm_display_mode *mode)
502*4882a593Smuzhiyun {
503*4882a593Smuzhiyun 	/* TODO */
504*4882a593Smuzhiyun 	return MODE_OK;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun static const struct drm_connector_helper_funcs sun4i_tv_comp_connector_helper_funcs = {
508*4882a593Smuzhiyun 	.get_modes	= sun4i_tv_comp_get_modes,
509*4882a593Smuzhiyun 	.mode_valid	= sun4i_tv_comp_mode_valid,
510*4882a593Smuzhiyun };
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun static void
sun4i_tv_comp_connector_destroy(struct drm_connector * connector)513*4882a593Smuzhiyun sun4i_tv_comp_connector_destroy(struct drm_connector *connector)
514*4882a593Smuzhiyun {
515*4882a593Smuzhiyun 	drm_connector_cleanup(connector);
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun static const struct drm_connector_funcs sun4i_tv_comp_connector_funcs = {
519*4882a593Smuzhiyun 	.fill_modes		= drm_helper_probe_single_connector_modes,
520*4882a593Smuzhiyun 	.destroy		= sun4i_tv_comp_connector_destroy,
521*4882a593Smuzhiyun 	.reset			= drm_atomic_helper_connector_reset,
522*4882a593Smuzhiyun 	.atomic_duplicate_state	= drm_atomic_helper_connector_duplicate_state,
523*4882a593Smuzhiyun 	.atomic_destroy_state	= drm_atomic_helper_connector_destroy_state,
524*4882a593Smuzhiyun };
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun static const struct regmap_config sun4i_tv_regmap_config = {
527*4882a593Smuzhiyun 	.reg_bits	= 32,
528*4882a593Smuzhiyun 	.val_bits	= 32,
529*4882a593Smuzhiyun 	.reg_stride	= 4,
530*4882a593Smuzhiyun 	.max_register	= SUN4I_TVE_WSS_DATA2_REG,
531*4882a593Smuzhiyun 	.name		= "tv-encoder",
532*4882a593Smuzhiyun };
533*4882a593Smuzhiyun 
sun4i_tv_bind(struct device * dev,struct device * master,void * data)534*4882a593Smuzhiyun static int sun4i_tv_bind(struct device *dev, struct device *master,
535*4882a593Smuzhiyun 			 void *data)
536*4882a593Smuzhiyun {
537*4882a593Smuzhiyun 	struct platform_device *pdev = to_platform_device(dev);
538*4882a593Smuzhiyun 	struct drm_device *drm = data;
539*4882a593Smuzhiyun 	struct sun4i_drv *drv = drm->dev_private;
540*4882a593Smuzhiyun 	struct sun4i_tv *tv;
541*4882a593Smuzhiyun 	struct resource *res;
542*4882a593Smuzhiyun 	void __iomem *regs;
543*4882a593Smuzhiyun 	int ret;
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 	tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
546*4882a593Smuzhiyun 	if (!tv)
547*4882a593Smuzhiyun 		return -ENOMEM;
548*4882a593Smuzhiyun 	tv->drv = drv;
549*4882a593Smuzhiyun 	dev_set_drvdata(dev, tv);
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
552*4882a593Smuzhiyun 	regs = devm_ioremap_resource(dev, res);
553*4882a593Smuzhiyun 	if (IS_ERR(regs)) {
554*4882a593Smuzhiyun 		dev_err(dev, "Couldn't map the TV encoder registers\n");
555*4882a593Smuzhiyun 		return PTR_ERR(regs);
556*4882a593Smuzhiyun 	}
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	tv->regs = devm_regmap_init_mmio(dev, regs,
559*4882a593Smuzhiyun 					 &sun4i_tv_regmap_config);
560*4882a593Smuzhiyun 	if (IS_ERR(tv->regs)) {
561*4882a593Smuzhiyun 		dev_err(dev, "Couldn't create the TV encoder regmap\n");
562*4882a593Smuzhiyun 		return PTR_ERR(tv->regs);
563*4882a593Smuzhiyun 	}
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun 	tv->reset = devm_reset_control_get(dev, NULL);
566*4882a593Smuzhiyun 	if (IS_ERR(tv->reset)) {
567*4882a593Smuzhiyun 		dev_err(dev, "Couldn't get our reset line\n");
568*4882a593Smuzhiyun 		return PTR_ERR(tv->reset);
569*4882a593Smuzhiyun 	}
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	ret = reset_control_deassert(tv->reset);
572*4882a593Smuzhiyun 	if (ret) {
573*4882a593Smuzhiyun 		dev_err(dev, "Couldn't deassert our reset line\n");
574*4882a593Smuzhiyun 		return ret;
575*4882a593Smuzhiyun 	}
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	tv->clk = devm_clk_get(dev, NULL);
578*4882a593Smuzhiyun 	if (IS_ERR(tv->clk)) {
579*4882a593Smuzhiyun 		dev_err(dev, "Couldn't get the TV encoder clock\n");
580*4882a593Smuzhiyun 		ret = PTR_ERR(tv->clk);
581*4882a593Smuzhiyun 		goto err_assert_reset;
582*4882a593Smuzhiyun 	}
583*4882a593Smuzhiyun 	clk_prepare_enable(tv->clk);
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	drm_encoder_helper_add(&tv->encoder,
586*4882a593Smuzhiyun 			       &sun4i_tv_helper_funcs);
587*4882a593Smuzhiyun 	ret = drm_simple_encoder_init(drm, &tv->encoder,
588*4882a593Smuzhiyun 				      DRM_MODE_ENCODER_TVDAC);
589*4882a593Smuzhiyun 	if (ret) {
590*4882a593Smuzhiyun 		dev_err(dev, "Couldn't initialise the TV encoder\n");
591*4882a593Smuzhiyun 		goto err_disable_clk;
592*4882a593Smuzhiyun 	}
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	tv->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
595*4882a593Smuzhiyun 								dev->of_node);
596*4882a593Smuzhiyun 	if (!tv->encoder.possible_crtcs) {
597*4882a593Smuzhiyun 		ret = -EPROBE_DEFER;
598*4882a593Smuzhiyun 		goto err_disable_clk;
599*4882a593Smuzhiyun 	}
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	drm_connector_helper_add(&tv->connector,
602*4882a593Smuzhiyun 				 &sun4i_tv_comp_connector_helper_funcs);
603*4882a593Smuzhiyun 	ret = drm_connector_init(drm, &tv->connector,
604*4882a593Smuzhiyun 				 &sun4i_tv_comp_connector_funcs,
605*4882a593Smuzhiyun 				 DRM_MODE_CONNECTOR_Composite);
606*4882a593Smuzhiyun 	if (ret) {
607*4882a593Smuzhiyun 		dev_err(dev,
608*4882a593Smuzhiyun 			"Couldn't initialise the Composite connector\n");
609*4882a593Smuzhiyun 		goto err_cleanup_connector;
610*4882a593Smuzhiyun 	}
611*4882a593Smuzhiyun 	tv->connector.interlace_allowed = true;
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	drm_connector_attach_encoder(&tv->connector, &tv->encoder);
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	return 0;
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun err_cleanup_connector:
618*4882a593Smuzhiyun 	drm_encoder_cleanup(&tv->encoder);
619*4882a593Smuzhiyun err_disable_clk:
620*4882a593Smuzhiyun 	clk_disable_unprepare(tv->clk);
621*4882a593Smuzhiyun err_assert_reset:
622*4882a593Smuzhiyun 	reset_control_assert(tv->reset);
623*4882a593Smuzhiyun 	return ret;
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun 
sun4i_tv_unbind(struct device * dev,struct device * master,void * data)626*4882a593Smuzhiyun static void sun4i_tv_unbind(struct device *dev, struct device *master,
627*4882a593Smuzhiyun 			    void *data)
628*4882a593Smuzhiyun {
629*4882a593Smuzhiyun 	struct sun4i_tv *tv = dev_get_drvdata(dev);
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	drm_connector_cleanup(&tv->connector);
632*4882a593Smuzhiyun 	drm_encoder_cleanup(&tv->encoder);
633*4882a593Smuzhiyun 	clk_disable_unprepare(tv->clk);
634*4882a593Smuzhiyun }
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun static const struct component_ops sun4i_tv_ops = {
637*4882a593Smuzhiyun 	.bind	= sun4i_tv_bind,
638*4882a593Smuzhiyun 	.unbind	= sun4i_tv_unbind,
639*4882a593Smuzhiyun };
640*4882a593Smuzhiyun 
sun4i_tv_probe(struct platform_device * pdev)641*4882a593Smuzhiyun static int sun4i_tv_probe(struct platform_device *pdev)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun 	return component_add(&pdev->dev, &sun4i_tv_ops);
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun 
sun4i_tv_remove(struct platform_device * pdev)646*4882a593Smuzhiyun static int sun4i_tv_remove(struct platform_device *pdev)
647*4882a593Smuzhiyun {
648*4882a593Smuzhiyun 	component_del(&pdev->dev, &sun4i_tv_ops);
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 	return 0;
651*4882a593Smuzhiyun }
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun static const struct of_device_id sun4i_tv_of_table[] = {
654*4882a593Smuzhiyun 	{ .compatible = "allwinner,sun4i-a10-tv-encoder" },
655*4882a593Smuzhiyun 	{ }
656*4882a593Smuzhiyun };
657*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sun4i_tv_of_table);
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun static struct platform_driver sun4i_tv_platform_driver = {
660*4882a593Smuzhiyun 	.probe		= sun4i_tv_probe,
661*4882a593Smuzhiyun 	.remove		= sun4i_tv_remove,
662*4882a593Smuzhiyun 	.driver		= {
663*4882a593Smuzhiyun 		.name		= "sun4i-tve",
664*4882a593Smuzhiyun 		.of_match_table	= sun4i_tv_of_table,
665*4882a593Smuzhiyun 	},
666*4882a593Smuzhiyun };
667*4882a593Smuzhiyun module_platform_driver(sun4i_tv_platform_driver);
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
670*4882a593Smuzhiyun MODULE_DESCRIPTION("Allwinner A10 TV Encoder Driver");
671*4882a593Smuzhiyun MODULE_LICENSE("GPL");
672