xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/sun4i_rgb.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2015 Free Electrons
4*4882a593Smuzhiyun  * Copyright (C) 2015 NextThing Co
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Maxime Ripard <maxime.ripard@free-electrons.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
12*4882a593Smuzhiyun #include <drm/drm_bridge.h>
13*4882a593Smuzhiyun #include <drm/drm_of.h>
14*4882a593Smuzhiyun #include <drm/drm_panel.h>
15*4882a593Smuzhiyun #include <drm/drm_print.h>
16*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
17*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include "sun4i_crtc.h"
20*4882a593Smuzhiyun #include "sun4i_tcon.h"
21*4882a593Smuzhiyun #include "sun4i_rgb.h"
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun struct sun4i_rgb {
24*4882a593Smuzhiyun 	struct drm_connector	connector;
25*4882a593Smuzhiyun 	struct drm_encoder	encoder;
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	struct sun4i_tcon	*tcon;
28*4882a593Smuzhiyun 	struct drm_panel	*panel;
29*4882a593Smuzhiyun 	struct drm_bridge	*bridge;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun static inline struct sun4i_rgb *
drm_connector_to_sun4i_rgb(struct drm_connector * connector)33*4882a593Smuzhiyun drm_connector_to_sun4i_rgb(struct drm_connector *connector)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun 	return container_of(connector, struct sun4i_rgb,
36*4882a593Smuzhiyun 			    connector);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun static inline struct sun4i_rgb *
drm_encoder_to_sun4i_rgb(struct drm_encoder * encoder)40*4882a593Smuzhiyun drm_encoder_to_sun4i_rgb(struct drm_encoder *encoder)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	return container_of(encoder, struct sun4i_rgb,
43*4882a593Smuzhiyun 			    encoder);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun 
sun4i_rgb_get_modes(struct drm_connector * connector)46*4882a593Smuzhiyun static int sun4i_rgb_get_modes(struct drm_connector *connector)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun 	struct sun4i_rgb *rgb =
49*4882a593Smuzhiyun 		drm_connector_to_sun4i_rgb(connector);
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	return drm_panel_get_modes(rgb->panel, connector);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun  * VESA DMT defines a tolerance of 0.5% on the pixel clock, while the
56*4882a593Smuzhiyun  * CVT spec reuses that tolerance in its examples, so it looks to be a
57*4882a593Smuzhiyun  * good default tolerance for the EDID-based modes. Define it to 5 per
58*4882a593Smuzhiyun  * mille to avoid floating point operations.
59*4882a593Smuzhiyun  */
60*4882a593Smuzhiyun #define SUN4I_RGB_DOTCLOCK_TOLERANCE_PER_MILLE	5
61*4882a593Smuzhiyun 
sun4i_rgb_mode_valid(struct drm_encoder * crtc,const struct drm_display_mode * mode)62*4882a593Smuzhiyun static enum drm_mode_status sun4i_rgb_mode_valid(struct drm_encoder *crtc,
63*4882a593Smuzhiyun 						 const struct drm_display_mode *mode)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(crtc);
66*4882a593Smuzhiyun 	struct sun4i_tcon *tcon = rgb->tcon;
67*4882a593Smuzhiyun 	u32 hsync = mode->hsync_end - mode->hsync_start;
68*4882a593Smuzhiyun 	u32 vsync = mode->vsync_end - mode->vsync_start;
69*4882a593Smuzhiyun 	unsigned long long rate = mode->clock * 1000;
70*4882a593Smuzhiyun 	unsigned long long lowest, highest;
71*4882a593Smuzhiyun 	unsigned long long rounded_rate;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Validating modes...\n");
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	if (hsync < 1)
76*4882a593Smuzhiyun 		return MODE_HSYNC_NARROW;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	if (hsync > 0x3ff)
79*4882a593Smuzhiyun 		return MODE_HSYNC_WIDE;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	if ((mode->hdisplay < 1) || (mode->htotal < 1))
82*4882a593Smuzhiyun 		return MODE_H_ILLEGAL;
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	if ((mode->hdisplay > 0x7ff) || (mode->htotal > 0xfff))
85*4882a593Smuzhiyun 		return MODE_BAD_HVALUE;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Horizontal parameters OK\n");
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	if (vsync < 1)
90*4882a593Smuzhiyun 		return MODE_VSYNC_NARROW;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	if (vsync > 0x3ff)
93*4882a593Smuzhiyun 		return MODE_VSYNC_WIDE;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	if ((mode->vdisplay < 1) || (mode->vtotal < 1))
96*4882a593Smuzhiyun 		return MODE_V_ILLEGAL;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	if ((mode->vdisplay > 0x7ff) || (mode->vtotal > 0xfff))
99*4882a593Smuzhiyun 		return MODE_BAD_VVALUE;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Vertical parameters OK\n");
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	/*
104*4882a593Smuzhiyun 	 * TODO: We should use the struct display_timing if available
105*4882a593Smuzhiyun 	 * and / or trying to stretch the timings within that
106*4882a593Smuzhiyun 	 * tolerancy to take care of panels that we wouldn't be able
107*4882a593Smuzhiyun 	 * to have a exact match for.
108*4882a593Smuzhiyun 	 */
109*4882a593Smuzhiyun 	if (rgb->panel) {
110*4882a593Smuzhiyun 		DRM_DEBUG_DRIVER("RGB panel used, skipping clock rate checks");
111*4882a593Smuzhiyun 		goto out;
112*4882a593Smuzhiyun 	}
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	/*
115*4882a593Smuzhiyun 	 * That shouldn't ever happen unless something is really wrong, but it
116*4882a593Smuzhiyun 	 * doesn't harm to check.
117*4882a593Smuzhiyun 	 */
118*4882a593Smuzhiyun 	if (!rgb->bridge)
119*4882a593Smuzhiyun 		goto out;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	tcon->dclk_min_div = 6;
122*4882a593Smuzhiyun 	tcon->dclk_max_div = 127;
123*4882a593Smuzhiyun 	rounded_rate = clk_round_rate(tcon->dclk, rate);
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	lowest = rate * (1000 - SUN4I_RGB_DOTCLOCK_TOLERANCE_PER_MILLE);
126*4882a593Smuzhiyun 	do_div(lowest, 1000);
127*4882a593Smuzhiyun 	if (rounded_rate < lowest)
128*4882a593Smuzhiyun 		return MODE_CLOCK_LOW;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	highest = rate * (1000 + SUN4I_RGB_DOTCLOCK_TOLERANCE_PER_MILLE);
131*4882a593Smuzhiyun 	do_div(highest, 1000);
132*4882a593Smuzhiyun 	if (rounded_rate > highest)
133*4882a593Smuzhiyun 		return MODE_CLOCK_HIGH;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun out:
136*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Clock rate OK\n");
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	return MODE_OK;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun static const struct drm_connector_helper_funcs sun4i_rgb_con_helper_funcs = {
142*4882a593Smuzhiyun 	.get_modes	= sun4i_rgb_get_modes,
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun static void
sun4i_rgb_connector_destroy(struct drm_connector * connector)146*4882a593Smuzhiyun sun4i_rgb_connector_destroy(struct drm_connector *connector)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun 	drm_connector_cleanup(connector);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun static const struct drm_connector_funcs sun4i_rgb_con_funcs = {
152*4882a593Smuzhiyun 	.fill_modes		= drm_helper_probe_single_connector_modes,
153*4882a593Smuzhiyun 	.destroy		= sun4i_rgb_connector_destroy,
154*4882a593Smuzhiyun 	.reset			= drm_atomic_helper_connector_reset,
155*4882a593Smuzhiyun 	.atomic_duplicate_state	= drm_atomic_helper_connector_duplicate_state,
156*4882a593Smuzhiyun 	.atomic_destroy_state	= drm_atomic_helper_connector_destroy_state,
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun 
sun4i_rgb_encoder_enable(struct drm_encoder * encoder)159*4882a593Smuzhiyun static void sun4i_rgb_encoder_enable(struct drm_encoder *encoder)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun 	struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Enabling RGB output\n");
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	if (rgb->panel) {
166*4882a593Smuzhiyun 		drm_panel_prepare(rgb->panel);
167*4882a593Smuzhiyun 		drm_panel_enable(rgb->panel);
168*4882a593Smuzhiyun 	}
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun 
sun4i_rgb_encoder_disable(struct drm_encoder * encoder)171*4882a593Smuzhiyun static void sun4i_rgb_encoder_disable(struct drm_encoder *encoder)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun 	struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	DRM_DEBUG_DRIVER("Disabling RGB output\n");
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	if (rgb->panel) {
178*4882a593Smuzhiyun 		drm_panel_disable(rgb->panel);
179*4882a593Smuzhiyun 		drm_panel_unprepare(rgb->panel);
180*4882a593Smuzhiyun 	}
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs sun4i_rgb_enc_helper_funcs = {
184*4882a593Smuzhiyun 	.disable	= sun4i_rgb_encoder_disable,
185*4882a593Smuzhiyun 	.enable		= sun4i_rgb_encoder_enable,
186*4882a593Smuzhiyun 	.mode_valid	= sun4i_rgb_mode_valid,
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
sun4i_rgb_init(struct drm_device * drm,struct sun4i_tcon * tcon)189*4882a593Smuzhiyun int sun4i_rgb_init(struct drm_device *drm, struct sun4i_tcon *tcon)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun 	struct drm_encoder *encoder;
192*4882a593Smuzhiyun 	struct sun4i_rgb *rgb;
193*4882a593Smuzhiyun 	int ret;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	rgb = devm_kzalloc(drm->dev, sizeof(*rgb), GFP_KERNEL);
196*4882a593Smuzhiyun 	if (!rgb)
197*4882a593Smuzhiyun 		return -ENOMEM;
198*4882a593Smuzhiyun 	rgb->tcon = tcon;
199*4882a593Smuzhiyun 	encoder = &rgb->encoder;
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	ret = drm_of_find_panel_or_bridge(tcon->dev->of_node, 1, 0,
202*4882a593Smuzhiyun 					  &rgb->panel, &rgb->bridge);
203*4882a593Smuzhiyun 	if (ret) {
204*4882a593Smuzhiyun 		dev_info(drm->dev, "No panel or bridge found... RGB output disabled\n");
205*4882a593Smuzhiyun 		return 0;
206*4882a593Smuzhiyun 	}
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	drm_encoder_helper_add(&rgb->encoder,
209*4882a593Smuzhiyun 			       &sun4i_rgb_enc_helper_funcs);
210*4882a593Smuzhiyun 	ret = drm_simple_encoder_init(drm, &rgb->encoder,
211*4882a593Smuzhiyun 				      DRM_MODE_ENCODER_NONE);
212*4882a593Smuzhiyun 	if (ret) {
213*4882a593Smuzhiyun 		dev_err(drm->dev, "Couldn't initialise the rgb encoder\n");
214*4882a593Smuzhiyun 		goto err_out;
215*4882a593Smuzhiyun 	}
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	/* The RGB encoder can only work with the TCON channel 0 */
218*4882a593Smuzhiyun 	rgb->encoder.possible_crtcs = drm_crtc_mask(&tcon->crtc->crtc);
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	if (rgb->panel) {
221*4882a593Smuzhiyun 		drm_connector_helper_add(&rgb->connector,
222*4882a593Smuzhiyun 					 &sun4i_rgb_con_helper_funcs);
223*4882a593Smuzhiyun 		ret = drm_connector_init(drm, &rgb->connector,
224*4882a593Smuzhiyun 					 &sun4i_rgb_con_funcs,
225*4882a593Smuzhiyun 					 DRM_MODE_CONNECTOR_Unknown);
226*4882a593Smuzhiyun 		if (ret) {
227*4882a593Smuzhiyun 			dev_err(drm->dev, "Couldn't initialise the rgb connector\n");
228*4882a593Smuzhiyun 			goto err_cleanup_connector;
229*4882a593Smuzhiyun 		}
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 		drm_connector_attach_encoder(&rgb->connector,
232*4882a593Smuzhiyun 						  &rgb->encoder);
233*4882a593Smuzhiyun 	}
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	if (rgb->bridge) {
236*4882a593Smuzhiyun 		ret = drm_bridge_attach(encoder, rgb->bridge, NULL, 0);
237*4882a593Smuzhiyun 		if (ret) {
238*4882a593Smuzhiyun 			dev_err(drm->dev, "Couldn't attach our bridge\n");
239*4882a593Smuzhiyun 			goto err_cleanup_connector;
240*4882a593Smuzhiyun 		}
241*4882a593Smuzhiyun 	}
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	return 0;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun err_cleanup_connector:
246*4882a593Smuzhiyun 	drm_encoder_cleanup(&rgb->encoder);
247*4882a593Smuzhiyun err_out:
248*4882a593Smuzhiyun 	return ret;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun EXPORT_SYMBOL(sun4i_rgb_init);
251