xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/sun4i_frontend.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2017 Free Electrons
4*4882a593Smuzhiyun  * Maxime Ripard <maxime.ripard@free-electrons.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef _SUN4I_FRONTEND_H_
8*4882a593Smuzhiyun #define _SUN4I_FRONTEND_H_
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/list.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #define SUN4I_FRONTEND_EN_REG			0x000
13*4882a593Smuzhiyun #define SUN4I_FRONTEND_EN_EN				BIT(0)
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define SUN4I_FRONTEND_FRM_CTRL_REG		0x004
16*4882a593Smuzhiyun #define SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL	BIT(23)
17*4882a593Smuzhiyun #define SUN4I_FRONTEND_FRM_CTRL_FRM_START		BIT(16)
18*4882a593Smuzhiyun #define SUN4I_FRONTEND_FRM_CTRL_COEF_RDY		BIT(1)
19*4882a593Smuzhiyun #define SUN4I_FRONTEND_FRM_CTRL_REG_RDY			BIT(0)
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define SUN4I_FRONTEND_BYPASS_REG		0x008
22*4882a593Smuzhiyun #define SUN4I_FRONTEND_BYPASS_CSC_EN			BIT(1)
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define SUN4I_FRONTEND_BUF_ADDR0_REG		0x020
25*4882a593Smuzhiyun #define SUN4I_FRONTEND_BUF_ADDR1_REG		0x024
26*4882a593Smuzhiyun #define SUN4I_FRONTEND_BUF_ADDR2_REG		0x028
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define SUN4I_FRONTEND_TB_OFF0_REG		0x030
29*4882a593Smuzhiyun #define SUN4I_FRONTEND_TB_OFF1_REG		0x034
30*4882a593Smuzhiyun #define SUN4I_FRONTEND_TB_OFF2_REG		0x038
31*4882a593Smuzhiyun #define SUN4I_FRONTEND_TB_OFF_X1(x1)			((x1) << 16)
32*4882a593Smuzhiyun #define SUN4I_FRONTEND_TB_OFF_Y0(y0)			((y0) << 8)
33*4882a593Smuzhiyun #define SUN4I_FRONTEND_TB_OFF_X0(x0)			(x0)
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #define SUN4I_FRONTEND_LINESTRD0_REG		0x040
36*4882a593Smuzhiyun #define SUN4I_FRONTEND_LINESTRD1_REG		0x044
37*4882a593Smuzhiyun #define SUN4I_FRONTEND_LINESTRD2_REG		0x048
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun  * In tiled mode, the stride is defined as the distance between the start of the
41*4882a593Smuzhiyun  * end line of the current tile and the start of the first line in the next
42*4882a593Smuzhiyun  * vertical tile.
43*4882a593Smuzhiyun  *
44*4882a593Smuzhiyun  * Tiles are represented in row-major order, thus the end line of current tile
45*4882a593Smuzhiyun  * starts at: 31 * 32 (31 lines of 32 cols), the next vertical tile starts at:
46*4882a593Smuzhiyun  * 32-bit-aligned-width * 32 and the distance is:
47*4882a593Smuzhiyun  * 32 * (32-bit-aligned-width - 31).
48*4882a593Smuzhiyun  */
49*4882a593Smuzhiyun #define SUN4I_FRONTEND_LINESTRD_TILED(stride)		(((stride) - 31) * 32)
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_REG		0x04c
52*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PLANAR	(0 << 8)
53*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PACKED	(1 << 8)
54*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_SEMIPLANAR	(2 << 8)
55*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_PLANAR	(4 << 8)
56*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_SEMIPLANAR (6 << 8)
57*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV444	(0 << 4)
58*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV422	(1 << 4)
59*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV420	(2 << 4)
60*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV411	(3 << 4)
61*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_RGB		(5 << 4)
62*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UYVY		0
63*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YUYV		1
64*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VYUY		2
65*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YVYU		3
66*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV		0
67*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU		1
68*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_BGRX		0
69*4882a593Smuzhiyun #define SUN4I_FRONTEND_INPUT_FMT_DATA_PS_XRGB		1
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define SUN4I_FRONTEND_OUTPUT_FMT_REG		0x05c
72*4882a593Smuzhiyun #define SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_BGRX8888	1
73*4882a593Smuzhiyun #define SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_XRGB8888	2
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define SUN4I_FRONTEND_CSC_COEF_REG(c)		(0x070 + (0x4 * (c)))
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH0_INSIZE_REG		0x100
78*4882a593Smuzhiyun #define SUN4I_FRONTEND_INSIZE(h, w)			((((h) - 1) << 16) | (((w) - 1)))
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH0_OUTSIZE_REG		0x104
81*4882a593Smuzhiyun #define SUN4I_FRONTEND_OUTSIZE(h, w)			((((h) - 1) << 16) | (((w) - 1)))
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH0_HORZFACT_REG		0x108
84*4882a593Smuzhiyun #define SUN4I_FRONTEND_HORZFACT(i, f)			(((i) << 16) | (f))
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH0_VERTFACT_REG		0x10c
87*4882a593Smuzhiyun #define SUN4I_FRONTEND_VERTFACT(i, f)			(((i) << 16) | (f))
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH0_HORZPHASE_REG	0x110
90*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH0_VERTPHASE0_REG	0x114
91*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH0_VERTPHASE1_REG	0x118
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH1_INSIZE_REG		0x200
94*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH1_OUTSIZE_REG		0x204
95*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH1_HORZFACT_REG		0x208
96*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH1_VERTFACT_REG		0x20c
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH1_HORZPHASE_REG	0x210
99*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH1_VERTPHASE0_REG	0x214
100*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH1_VERTPHASE1_REG	0x218
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH0_HORZCOEF0_REG(i)	(0x400 + i * 4)
103*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH0_HORZCOEF1_REG(i)	(0x480 + i * 4)
104*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH0_VERTCOEF_REG(i)	(0x500 + i * 4)
105*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH1_HORZCOEF0_REG(i)	(0x600 + i * 4)
106*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH1_HORZCOEF1_REG(i)	(0x680 + i * 4)
107*4882a593Smuzhiyun #define SUN4I_FRONTEND_CH1_VERTCOEF_REG(i)	(0x700 + i * 4)
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun struct clk;
110*4882a593Smuzhiyun struct device_node;
111*4882a593Smuzhiyun struct drm_plane;
112*4882a593Smuzhiyun struct regmap;
113*4882a593Smuzhiyun struct reset_control;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun struct sun4i_frontend_data {
116*4882a593Smuzhiyun 	bool	has_coef_access_ctrl;
117*4882a593Smuzhiyun 	bool	has_coef_rdy;
118*4882a593Smuzhiyun 	u32	ch_phase[2];
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun struct sun4i_frontend {
122*4882a593Smuzhiyun 	struct list_head	list;
123*4882a593Smuzhiyun 	struct device		*dev;
124*4882a593Smuzhiyun 	struct device_node	*node;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	struct clk		*bus_clk;
127*4882a593Smuzhiyun 	struct clk		*mod_clk;
128*4882a593Smuzhiyun 	struct clk		*ram_clk;
129*4882a593Smuzhiyun 	struct regmap		*regs;
130*4882a593Smuzhiyun 	struct reset_control	*reset;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	const struct sun4i_frontend_data	*data;
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun extern const struct of_device_id sun4i_frontend_of_table[];
136*4882a593Smuzhiyun extern const u32 sunxi_bt601_yuv2rgb_coef[12];
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun int sun4i_frontend_init(struct sun4i_frontend *frontend);
139*4882a593Smuzhiyun void sun4i_frontend_exit(struct sun4i_frontend *frontend);
140*4882a593Smuzhiyun int sun4i_frontend_enable(struct sun4i_frontend *frontend);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun void sun4i_frontend_update_buffer(struct sun4i_frontend *frontend,
143*4882a593Smuzhiyun 				  struct drm_plane *plane);
144*4882a593Smuzhiyun void sun4i_frontend_update_coord(struct sun4i_frontend *frontend,
145*4882a593Smuzhiyun 				 struct drm_plane *plane);
146*4882a593Smuzhiyun int sun4i_frontend_update_formats(struct sun4i_frontend *frontend,
147*4882a593Smuzhiyun 				  struct drm_plane *plane, uint32_t out_fmt);
148*4882a593Smuzhiyun bool sun4i_frontend_format_is_supported(uint32_t fmt, uint64_t modifier);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun #endif /* _SUN4I_FRONTEND_H_ */
151